RM0391 Embedded memories
Figure 6. SPC58xEx/SPC58xGx Flash memory block diagram
XBAR_0
64
Flash Memory Controller 0
4-Entry, 2-Way Mini-Cache
64
XBAR_1
64
64
Flash Memory Controller 1
4-Entry, 2-Way Mini-Cache
256 Read
2 MB Flash Memory Array
64 Write 256 Read
4 MB Flash Memory Array
64 Write
3.3.1
3.3.2
The remaining sections give the functional details of the Flash controller and Flash array, followed by the memory maps.
Flash memory controller
The SPC58xEx/SPC58xGx Flash memory controllers act as an interface between the system bus and the Flash memory array and serves as the interface to the on-chip overlay
RAM and off-chip Buddy Device
(2)
.
The Flash memory controller contains a four-entry, two-way set-associative mini-cache that delivers Flash read data with a zero-wait state response on lines that reside in the cache.
Each entry contains one Flash read page, a 256-bit (32-byte) memory value. Read requests that miss the cache generate the needed Flash memory array access.
The Flash memory controller contains configuration registers that manage Flash functionality such as read buffering in the mini-cache, access control, calibration RAM overlay remapping, and read wait state management of the Flash memory.
Refer to the Chapter 36: Flash memory controller for details.
Flash memory array
SPC58xEx/SPC58xGx device includes two Flash memory arrays, one with 4 MB and one with 2 MB, referred to as “main space,” plus an independent 16 KB block of one-timeprogrammable (OTP) Flash memory included to support systems that require non-volatile memory for security features or system initialization information. The independent 16 KB block is referred to as “UTEST space.”
For code Flash sectors, reads of the embedded Flash memory return a 256-bit page of data that may be buffered in the mini-cache in the Flash memory controller. Programming of the
2. The Buddy Device is an optional companion chip with additional memory and debug features. A Buddy
Device is combined with a Production Device to form an Emulation and Debug Device (ED) for use during system development. It is not used in production systems.
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Flash may be done by double word (64-bits), page (256-bits), or quad-page (1024-bits).
Flash memory is erased on a block by block basis.
3.3.2.1 Features
• Flash segmentation
– 16 KB, 32 KB, 64 KB, 128 KB, and 256 KB blocks provided for code or data
– Four 64 KB blocks provided for EEPROM emulation
– One 16 KB block and two 64 KB blocks provided for secure code
– Two 16 KB blocks provided for secure data
– Support for reading-while-writing when the accesses are to different partitions
• Flash memory protection: write protection and OTP function available for each block
• Test and initialization data stored in a non-volatile 16 KB OTP UTEST block
• ECC with triple bit detection, double and single bit correction
• Erase suspend, program suspend, and erase-suspended program all supported
3.3.2.2 Flash organization
The embedded Flash memory consists of six address spaces in four groupings:
• 16 KB, 32 KB and 64 KB low address spaces
• 16 KB mid address space
• 64 KB high address space
• 256 KB address space
Address space group (low-, mid- or high-address space) determines which registers/fields are used to select blocks for modify operations or lock them from modify operations. Each address space is independent.
The Flash module is further divided into four partitions that determine locations for valid
Read While Write (RWW) operations. While the embedded Flash memory is performing a
“write” (program or erase) to a given partition, it can simultaneously read from any other partition.
• For program operations, only the address specified by an interlock write determines the partition being written (block locking and block select registers do not determine the
RWW partitions being written).
• For erase operations, only blocks that are selected and unlocked determine the RWW partitions being written.
• For read operation two independent read accesses can be done through both PFlash controller to two Read While Read (RWR) partitions.
Figure 7 shows the Flash block segmentation and Read While Write partitioning for
SPC58xEx/SPC58xGx devices.
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Figure 7. Flash memory segmentation and Read While Write partitioning
Low Address
Space
RWW Partition 0
16 KB UTEST
16 KB TEST
16 KB (block 1)
16 KB (block 2)
32 KB (block 0)
64 KB (block 0)
64 KB (block 1)
128 KB (block 0)
Low Address
Space
RWW Partition 1
16 KB (BAF)
16 KB (HSM 0)
64 KB (HSM 1)
64 KB (HSM 2)
16 KB (block 3)
16 KB (block 4)
32 KB (block 1)
128 KB (block 1)
256 KB Address
Space
256 KB Address
Space
7 x 256 KB 7 x 256 KB
High Address
Space
RWW Partition 2
64 KB (block 0)
64 KB (block 1)
High Address
Space
RWW Partition 3
64 KB (block 2)
64 KB (block 3)
Mid Address
Space
RWW Partition 4
16 KB HSM Data 0
16 KB HSM Data 1
Read-While-Read 1 (RWR)
RWW Partition 5
256 KB Address
Space 8 x 256 KB
Read-While-Read 0 (RWR)
3 x 16 KB
Special Purpose
1 x 16 KB + 2 x 64 KB
Secure code Flash
2 x 16 KB
Secure data Flash
4 x 64 KB EEPROM emulation
Read While Write partition boundaries
Note:
Refer to the Chapter 5: Memory Map
for the SPC58xEx/SPC58xGx Flash memory map.
3.3.2.3 UTEST memory space
Devices in the SPC58xEx/SPC58xGx family contain a 16 KB area of one-timeprogrammable (OTP) Flash memory for storing test information and device configuration
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