FlexRay communication controller (FlexRay) RM0391
57.2.1.5 FR_B_TX – Transmit Data Channel B
The FR_B_TX signal carries the transmit data for channel B to the corresponding FlexRay bus driver
57.2.1.6 FR_B_TX_EN – Transmit Enable Channel B
The FR_B_TX_EN signal indicates to the FlexRay bus driver that the CC is attempting to transmit data on channel B.
57.2.1.7 FR_DBG[3], FR_DBG[2], FR_DBG[1], FR_DBG[0] – Strobe Signals
These signals provide the selected debug strobe signals. For details on the debug strobe
signal selection, refer to Section 57.6.16: Strobe signal support .
57.3 Controller host interface clocking
The clock for the CHI is derived from the system bus clock and has the same phase and frequency as the system bus clock. There are two constraints for the minimum CHI clock frequency.
• The first constraint corresponds to the number of utilized message buffers and is
specified in Section 57.7.5: Number of usable message buffers .
• The second constraint corresponds to the value of the TIMEOUT field in the
Section 57.5.2.33: System Memory Access Timeout Register (FR_SYMATOR)
and is
specified in Section 57.7.1.1: Configure System Memory Access Timeout Register
(FR_SYMATOR) .
57.4 Protocol engine clocking
Note:
The clock for the protocol engine can be generated by two sources. The first source is the internal crystal oscillator and the second source is an internal PLL. The clock source to be used is selected by the clock source select field, CLKSEL, in the
Section 57.5.2.4: Module
Configuration Register (FR_MCR) .
Refer to the device clocking details for the exact clock sources used.
57.4.1 Oscillator clocking
If the protocol engine is clocked by the internal crystal oscillator, a 40 MHz crystal or CMOScompatible clock must be connected to the oscillator pins. The crystal or clock must fulfill the requirements given by the FlexRay Communications System Protocol Specification,
Version 2.1 Rev A.
57.4.2 PLL clocking
If the protocol engine is clocked by the internal PLL, the PLL clock should be divided down appropriately to generate the 40 MHz and 180 degree phase-shifted 40 MHz clocks and provide them to the PE. For more details, refer to the clocking chapter of the device reference manual.
2134/4266 RM0391 Rev 5
