Core (z420n3) Description RM0391
Bit
Table 198. Machine Check Syndrome Register (MCSR) (continued)
Name Description
Exception
Type
(1)
Recoverable
27
28
BUS_IRERR
BUS_DRERR
Read bus error on Instruction recovery linefill
Read bus error on data load or linefill
Async
Mchk
Async
Mchk
Async
Mchk
Precise if data used
Precise if data used
29
30
BUS_WRERR
BUS_WRDSI
Write bus error on store to bus or DMEM imprecise write error
Write bus error on buffered store to bus with DSI signaled. Set concurrently with BUS_WRERR for this case
Reserved
Async
Mchk
Unlikely
Unlikely
31 — —
1. The Exception Type indicates the exception type associated with a given syndrome bit
- “Error Report” indicates that this bit is only set for error report exceptions which cause machine check interrupts. These bits are only updated when the machine check interrupt is actually taken. Error report exceptions are not gated by MSR
ME
.
These are synchronous exceptions. These bits will remain set until cleared by software writing a “1” to the bit position(s) to be cleared.
- “Status” indicates that this bit is provides additional status information regarding the logging of a machine check exception.
These bits will remain set until cleared by software writing a “1” to the bit position(s) to be cleared.
- “NMI” indicates that this bit is only set for the non-maskable interrupt type exception which causes a machine check interrupt. This bit is only updated when the machine check interrupt is actually taken. NMI exceptions are not gated by
MSR
ME
. This is an asynchronous exception. This bit will remain set until cleared by software writing a “1” to the bit position.
- “Async Mchk” indicates that this bit is set for an asynchronous machine check exception. These bits are set immediately upon detection of the error. Once any “Async Mchk” bit is set in the MCSR, a machine check interrupt will occur if
MSR
ME
=1. If MSR
ME
=0, the machine check exception will remain pending. These bits will remain set until cleared by software writing a “1” to the bit position(s) to be cleared.
15.7.4 Interrupt Vector Prefix Registers (IVPR)
The Interrupt Vector Prefix Register is used during interrupt processing for determining the starting address of a software handler used to handle an interrupt. The value of the Vector
Offset selected for a particular interrupt type is concatenated with the Vector Base value held in the Interrupt Vector Prefix register (IVPR) to form an instruction address from which execution is to begin. The format of IVPR is shown in
Figure 115
.
Vector Base 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SPR - 63; Read/Write
Figure 115. Interrupt Vector Prefix Registers (IVPR)
The IVPR fields are defined in Table 199 .
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