Debug Zipwire implementation. STMicroelectronics SPC58 E/G Line - 32 bit Power Architecture automotive MCU Triple z4 cores 180 MHz, 6 MBytes Flash, HSM, ASIL-D, SPC58NE84E7, SPC58EE80E7, SPC58NE84C3, SPC58NG84C3, SPC58NG80E5, SPC58EG80E5, SPC58NE80E7, SPC58EE84E7, SPC58EG84E5

Debug Zipwire RM0391 mode). The Debug SIPI module is a bus master on the low speed XBAR. As the target MCU for a command from the inititating tool, Debug SIPI can perform read and write accesses to any address location within the target MCU. The software running on the local MCU, should configure the system MPU to allow/deny memory accesses to MCU memory and resources as required.

78.5 Debug Zipwire implementation

Figure 2051 shows the modules on the production device which support the Debug Zipwire

function, along with their interconnections to the debug interface signals.

Figure 2051. Block diagram showing connections for Emulation Device

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Internal connections to other debug modules which are used to support other debug interface protocols such as JTAG and JTAG over LFAST are also shown. The Debug SIPI module is connected to the Debug LFAST module via an LFAST switch module, which controls routing of debug LFAST traffic to either the Debug SIPI or the JTAGM module.

Figure 2052 shows the equivalent connections for ED devices utilizing the LFAST switch.

3392/4266 RM0391 Rev 5