RM0391 e200z420n3 Core Debug Support limit DAC event. In this case, the instruction and access will normally have completed, in the same manner as a normal DAC event.
Independent limit checks for supervisor and user accesses may be implemented by allocating independent DACn resources to each, or a single limit may be applied using a single DACn resource. Typically, a DAC1,2 pair operating in exclusive address range mode is utilized for stack limit checking for a single shared limit. For separate limits, DAC3,4 may also be utilized. If more than one DACn resource is utilized, a DAC hit on any resource utilized for stack limit checking will cause the corresponding stack limit exception action to occur. If both a hardware-owned and a software-owned resource generate a stack limit exception for a given load or store, the software resource will have priority, since it is detected prior to completion of the access, and the access is aborted, thus the hardware event will not occur.
Enabling of this functionality is described in more detail in the description of the DACnCFG fields in
Table 1857 and
Table 1860 in
Section 71.3.2, Debug Control and Status registers .
Note that for DAC1 and DAC2, access type (read, write) control is part of DBCR0.
71.5 External debug support
Note:
External debug support is supplied through the OnCE controller serial interface, which allows access to internal CPU registers and other system state while the CPU is halted in debug mode. All debug resources including DBCR0–8, DBSR, IAC1–8, DAC1–4, and
DVC1–2 are accessible through the serial OnCE interface in external debug mode. Setting the EDBCR0
EDM
/DBCR0
EDM bit to ‘1’ through the OnCE interface enables external debug mode, and unless otherwise permitted by the settings in EDBRAC0, disables software updates to the debug control registers. When EDBCR0
EDM
is set, debug events enabled to set respective status bits will also cause the CPU to enter Debug mode if the event is not masked in EDBSRMSK0, as opposed to generating Debug Interrupts, unless the specific events are allocated to software via the settings in EDBRAC0. In Debug mode, the CPU is halted at a recoverable boundary, and an external Debug Control Module may control CPU operation through the On-Chip Emulation logic (OnCE).
Note that the descriptions of events in the subsections of
Section 71.2, Software debug events and exceptions
refer to setting DBSR status bits, however, when resources are owned by hardware, the events for those resources set the respective status bits in
EDBSR0 instead of DBSR.
On the initial setting of EDBCR0
EDM
EDBCR0
EDM
to ‘1’, other bits in DBCR0 will remain unchanged. After
has been set, all debug register resources may be subsequently controlled through the OnCE interface. The CPU should be placed into debug mode via the OCR
DR control bit prior to writing EDM to ‘1’. This gives the debugger the opportunity to cleanly write to the DBCRx registers and the DBSR to clear out any residual state / control information that could cause unintended operation.
It is intended for the CPU to remain in external debug mode (EDBCR0
EDM single step or perform other debug mode entry/ reentry via the OCR
DR go+noexit commands, or by assertion of the jd_de_b signal.
=1) in order to
, by performing
EDBCR0
EDM
operation will be blocked if OnCE operation is disabled ( jd_en_once negated) regardless of whether it is set or cleared. This means that if EDBCR0
EDM
was previously set, and then jd_en_once is negated (this should not occur), entry into debug mode will be blocked, and all hardware debug events are blocked. Watchpoints are not blocked.
RM0391 Rev 5 3189/4266
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