Register Protection (REG_PROT) RM0391
Figure 2424. Enable locking for protected and unprotected addresses
Before write access
0 0 0 0 0 0 0 0
WE[3:0] SLB[3:0]
SLBR 3
After write access
32-Bit write to address 0x200C set lock bits
0 0 0 0
WE[3:0]
0 0 1 1
SLB[3:0] write to
SLBR 3
MR[15:12]
Note:
In the example in Figure 2424
addresses 0x0C and 0x0D are unprotected. Therefore their corresponding lock bits SLBR3.SLB[1:0] are always 0b0 (shown in bold). When doing a 32bit write access to address 0x200C only lock bits SLBR3.SLB[3:2] are set while bits
SLBR3.SLB[1:0] stay 0b0.
Lock bits can only be set via writes to the mirror module space. Reads from the mirror module space will not change the lock bits.
91.4.2.3 Write protection for locking bits
Changing the locking bits through any of the procedures mentioned in
Section 91.4.2.1:
Change lock settings directly via area #4
and Section 91.4.2.2: Enable locking via mirror module space (Area #3) is only possible as long as the bit GCR.HLB is cleared. Once this
bit is set the locking bits can no longer be modified until there is a system reset.
91.4.3 Access errors
The protection module generates transfer errors under several circumstances. For the area definition refer to
Figure 2416
1.
If accessing area #1 or area #3, the protection module will pass on any access error from the underlying Module under Protection.
2. If user mode is not allowed, user writes to all areas will assert a transfer error and the writes will be blocked.
3. If accessing the reserved area #2, a transfer error will be asserted.
4. If accessing unimplemented 32-bit registers in area #4 and area #5 a transfer error will be asserted.
5. If writing to a register in area #1 and area #3 with Soft Lock Bit set for any of the affected bytes a transfer error is asserted and the write will be blocked. Also the complete write operation to non-protected bytes in this word is ignored.
6. If writing to a Soft Lock Register in area #4 with the Hard Lock Bit being set a transfer error is asserted.
7. Any write operation in any access mode to area #3 while Hard Lock Bit GCR is set.
3880/4266 RM0391 Rev 5
