STA382BW
6.14.2 Serial data first bit
Table 32.
Serial data first bit
SAIFB
0
1
MSB-first
LSB-first
Register description: New Map
Format
Table 33.
Support serial audio input formats for MSB-first (SAIFB = 0)
BICKI SAI [3:0] SAIFB Interface format
0000 0 I
2
S 15-bit data
32 * fs
0001
0000
0
0
Left/right-justified 16-bit data
I
2
S 16- to 23-bit data
48 * fs
64 * fs
0001
0010
0110
1010
1110
0000
0001
0010
0110
1010
1110
0
0
0
0
0
0
0
0
0
0
0
Left-justified 16- to 24-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
I
2
S 16- to 24-bit data
Left-justified 16- to 24-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
Obsolete Product(s) - Obsolete Product(s)
Doc ID 022783 Rev 1 61/172
Register description: New Map
Table 34.
Supported serial audio input formats for LSB-first (SAIFB = 1)
BICKI SAI [3:0] SAIFB Interface format
32 * fs
48 * fs
64 * fs
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1001
1101
0010
0110
1010
1110
0000
0100
1000
1100
0001
0101
1001
1101
0010
0110
1010
1110
1100
1110
0100
0100
1000
1100
0001
0101
I
2
S 15-bit data
Left/right-justified 16-bit data
I
2
S 23-bit data
I
2
S 20-bit data
I
2
S 18-bit data
LSB first I
2
S 16-bit data
Left-justified 24-bit data
Left-justified 20-bit data
Left-justified 18-bit data
Left-justified 16-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
I
2
S 24-bit data
I
2
S 20-bit data
I
2
S 18-bit data
LSB first I
2
S 16-bit data
Left-justified 24-bit data
Left-justified 20-bit data
Left-justified 18-bit data
Left-justified 16-bit data
Right-justified 24-bit data
Right-justified 20-bit data
Right-justified 18-bit data
Right-justified 16-bit data
STA382BW synchronous to the PLL output clock. It means that:
● the frequency of PLL clock / frequency of LRCKI = N ±4 cycles, where N depends on the settings in
Table 30
● the PLL must be locked.
If these two conditions are not met, and the IDE bit (reg 0x05 bit 2) is set to 1, the
STA382BW will immediately mute the I
2
S PCM data out (provided to the processing block) and it will freeze any active processing task.
62/172 Doc ID 022783 Rev 1
