The L99DZ120 is a door zone systems IC providing electronic control modules with enhanced power management power supply functionality, including various standby modes, as well as LIN physical communication layers.

The two low-drop voltage regulators of the devices supply the system microcontroller and external peripheral loads such as sensors and provide enhanced system standby functionality with programmable local and remote wake-up capability. In addition 8 high-side drivers to supply LEDs, 2 high-side drivers to supply bulbs increase the system integration level.

Up to 3 DC motors and 4 external MOS transistors in H-bridge configuration can be driven.

All outputs are SC protected and implement an open-load diagnosis.

The ST standard SPI interface (4.0) allows control and diagnosis of the device and enables generic software development.

12/161

DS11567 Rev 5

L99DZ120

2

Block diagram and pin descriptions

Block diagram and pin descriptions

Pin

Figure 1. Block diagram

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CP2M

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Table 2. Pin definitions and functions

Function

Wake-up Input: Input pin for static or cyclic monitoring of external contacts

Charge pump pin for capacitor 2, negative side

Charge pump pin for capacitor 2, positive side

Charge pump output

Charge pump pin for capacitor 1, positive side

Charge pump pin for capacitor 1, negative side

DS11567 Rev 5

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160

Block diagram and pin descriptions L99DZ120

Pin

Symbol

Table 2. Pin definitions and functions (continued)

Function

OUT14

OUT13

OUT12

OUT9

OUT10

OUT11

LS1_FSO

LS2_FSO

Not connected

High-side-driver output to drive LEDs

High-side-driver-output

High-side-driver output to drive LEDs

VS; 2nd pin

OUT7

OUT6

OUT1

Fail Safe low-side switch (Active low)

Power supply voltage for power stage outputs (external reverse battery protection required), for this input a ceramic capacitor as close as possible to GND is recommended. Important: For the capability of driving, the full current at the outputs all pins of VS must be connected externally!

Current capability (pin description see above)

High-side-driver output to drive LEDs or a 10 Watt bulb (programmable

R dson

)

Half-bridge outputs: the output is built by a high-side and a low-side switch which are internally connected. The output stage of both switches is a power DMOS transistor. Each driver has an internal parasitic reverse diode (bulk-drain-diode: high-side driver from output to VS, low-side driver from GND to output)

OUT5

Not connected

, low-side driver

OUT5; 2nd pin Current capability (pin description see above)

SREG

Power supply voltage to supply the internal voltage regulators, OUT15 and the OUT_HS (external reverse battery protection required / Diode) for this input a ceramic capacitor as close as possible to GND and an electrolytic back up capacitor is recommended.

OUT_HS High-side-driver output to drive LEDs or to supply contacts

14/161

DS11567 Rev 5

L99DZ120 Block diagram and pin descriptions

Pin

Symbol

Table 2. Pin definitions and functions (continued)

Function

OUT4

, low-side driver

OUT4; 2 nd

pin Current capability (pin description see above)

VS; 3rd pin

Not connected

Current capability (for the pin description see above)

OUT15

PGND

OUT8

SGND

High-side-driver output to drive LEDs

Power GND

High-side-driver output to drive LEDs or a 5 Watt bulb (programmable

R dson

)

Not connected

Signal Ground

CLK

CSN

TxD_L

RxD_L/NINT

Current monitor output: depending on the selected multiplexer bits

CM_SEL_x ( CR 7 ) of the; Control Register this output sources an image of the instant current; through the corresponding high-side driver with a fixed ratio

Not connected

SPI: serial clock input

SPI: serial data output (push pull output stage)

SPI: serial data input

SPI: chip select not input

LIN Transmit data input

RxDL -> LIN receive data output; NINT -> indicates local/remote wake-up events (push pull output stage)

LIN_FLASH

DIR1

PWMH

DIRH

DIR2

NRESET

5V_1

LIN Flash Mode enable (former TxD_C pin, to guarantee family compatibility)

Not connected

Direct Drive Input 1

PWMH input: this input signal can be used to control the H-bridge Gate

Drivers.

Direction Input: this input controls the H-bridge Drivers for the external

MOSFETs

Direct Drive Input 2

NReset output to micro controller; (reset state = LOW) (low-side switch with drain connected to the output pin and internal pull up resistance to

5V_1)

Voltage regulator 1 output: 5 V supply e.g. micro controller

Not connected

DS11567 Rev 5

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160

Block diagram and pin descriptions

Pin

L99DZ120

GL1

SH1

GH1

GH2

SH2

GL2

Symbol

Table 2. Pin definitions and functions (continued)

Function

NINT

Debug

LIN

5V_2

Interrupt output (low active; push-pull output stage) to indicate V

SREG early warning (Active mode); indicates wake-up events from V1_standby mode

Not connected

Debug input to deactivate the window watchdog (high active)

LIN bus line

Voltage regulator 2 output: 5 V supply for external loads (potentiometer, sensors). V

2 is protected against reverse supply

Gate driver for PowerMOS low-side switch in half-bridge 1

Source of high-side switch in half-bridge 1

Gate driver for PowerMOS high-side switch in half-bridge 1

Gate driver for PowerMOS high-side switch in half-bridge 2

Source of high-side switch in half-bridge 2

Gate driver for PowerMOS low-side switch in half-bridge 2

16/161

DS11567 Rev 5

L99DZ120

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Block diagram and pin descriptions

Figure 2. Pin connection (top view)

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DS11567 Rev 5

17/161

160

Electrical specifications L99DZ120

3.1

18/161

Absolute maximum ratings

Stressing the device above the rating listed in

Table 3

may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.

Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability

Symbol

SREG

5V_1

Table 3. Absolute maximum ratings

Parameter / test condition Value [DC voltage] Unit

DC supply voltage / “jump start”

Load dump

Stabilized supply voltage, logic supply

-0.3 to +28

-0.3 to +40

-0.3 to 6.5

V1 < V

SREG

-0.3 to +28 (2)

V 5V_2 (1)

, V

DO,

CLK

CSN

RXDL/NINT,

NRESET,

CM,

DIR

, V

DIR2

PWMH

, V

DIRH,

INT

LIN_FLASH,

TXDL

Debug

LS1_FSO,

LS2_FSO

Stabilized supply voltage

Logic input / output voltage range

Multi Level Inputs

Debug input pin voltage range

Output voltage range of Fail-Safe low-side

Switches

DC Wake up input voltage / “jump start”

Load dump

LIN

Input

(3)

OUT_INJ

(3)

OUTn,

V out_HS

LIN bus I/O voltage range

Current injection into V

related input pins

Current injection into V

related outputs

Output voltage (n = 1 to 15)

GH1

, V

GH2

Gxy

) High Voltage Signal Pins

GL1,

GL2

, (V

Gxy

) High Voltage Signal Pins

-0.3 to V1+0.3

-0.3 to 40

-0.3 to 35

-0.3 to +28

-0.3 to +40

-20 to +40

-0.3 to V

+0.3

Sxy

-0.3 to

Sxy

+13; V

+0.3

Sxy

-0.3 to

+13; V

-0.3V to +12V; Vcp+0.3V

-1 to 40

SH1

, V

SH2

Sxy

)

CP1P

CP2P

High Voltage Signal Pins

High Voltage Signal Pins; single pulse with t max

= 200ns

High Voltage Signal Pins

-5 to 40

-0.3 to V

+14

-0.6 to V

+14

V mA mA

DS11567 Rev 5

L99DZ120

Note:

Electrical specifications

Symbol

Table 3. Absolute maximum ratings (continued)

Parameter / test condition Value [DC voltage] Unit

CP1M

, V

CP2M

High Voltage Signal Pins

High Voltage Signal Pin V

≤ 26 V

High Voltage Signal Pin V

> 26 V

-0.3 to V

+0.3

-0.3 to V

+14

-0.3 to +40

OUT9,

OUT10,

OUT11,

OUT12,

OUT13,

OUT14,

OUT15,

OUT_HS

OUT8

OUT7

OUT1,6

OUT4,5

Output current

(2)

±1.25

±2.5

±5

±10

VScum

Maximum cumulated current at V

drawn by

OUT1

(2)

Maximum cumulated current at V

drawn by

OUT8 & OUT10

(2)

Maximum cumulated current at V

drawn by

OUT4

(2)

Maximum cumulated current at V

drawn by

OUT5

(2)

Maximum cumulated current at V

drawn by

OUT6 & OUT7

(2)

±7.5

±2.5

±10

±7.5

VSREG

PGNDcum

Maximum cumulated current at V

drawn by

OUT9, OUT11, OUT12, OUT13, OUT14, OUT15 and CP

Maximum current at V

SREG and OUT_HS)

(2)

(5V_1. 5V_2

Maximum cumulated current at PGND drawn by

OUT1 & OUT6

(2)

Maximum cumulated current at PGND drawn by

OUT5

(2)

±2.5

±7.5

±12.5

SGND

GND pins

Maximum cumulated current at PGND drawn by

OUT4 (2)

Maximum current at SGND

(2)

PGND versus SGND

±12.5

±1.25

-0.3 to 0.3

1. 5V_2 is robust against SC to 28 V only in case V

SREG

is supplied.

2. Values for the absolute maximum DC current through the bond wires. This value does not consider maximum power dissipation or other limits.

3. Guaranteed by design.

All maximum ratings are absolute ratings. Leaving the limitation of any of these values may cause an irreversible damage of the integrated circuit!

DS11567 Rev 5

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160

Electrical specifications

Note:

L99DZ120

Loss of ground or ground shift with externally grounded loads: ESD structures are configured for nominal currents only. If external loads are connected to different grounds, the current load must be limited to this nominal current.

All pins

(1)

All power output pins

(2)

LIN

All pins

(5)

Corner pins

(5)

All pins

(7)

Table 4. ESD protection

Parameter

: OUT1 – OUT15, OUT_HS

Value

+/-2

+/-4

+/-8

(2)

+/-10

(3)

+/-6

(4)

+/-500

+/-750

(6)

+/- 200

Unit kV kV kV

1. HBM (human body model, 100 pF, 1.5 k Ω ) according to MIL 883C, Method 3015.7 or EIA/JESD22A114-A.

2. HBM with all none zapped pins grounded.

3. Indirect ESD Test according to IEC 61000-4-2 (150 pF, 330 Ω ) and ‘Hardware Requirements for LIN, CAN and Flexray Interfaces in Automotive Applications’ (version 1.3, 2012-05-04).

4. Direct ESD Test according to IEC 61000-4-2 (150 pF, 330 Ω ) and ‘Hardware Requirements for LIN, CAN and Flexray Interfaces in Automotive Applications’ (version 1.3, 2012-05-04).

5. Charged device model.

6. For WU, these limits are referred to one-zap stress; in case of three-zap stress, the limits are +750V/-400V.

7. Machine model; C = 220 pF, R = 0 Ω .

Note:

Symbol

T j

Table 5. Operating junction temperature

Parameter Value

Operating junction temperature -40 to 175

Unit

°C

All parameters are guaranteed in the junction temperature range -40 to 150°C (unless otherwise specified); the device is still operative and functional at higher temperatures (up to

175°C).

Parameters limits at higher junction temperatures than 150°C may change respect to what is specified as per the standard temperature range.

Device functionality at high junction temperature is guaranteed by characterization.

20/161

DS11567 Rev 5

L99DZ120 Electrical specifications

Symbol

Table 6. Temperature warning and thermal shutdown

Parameter

SD1

SD2

SD12hys

T jtft

Thermal overtemperature warning threshold T j

(1)

Thermal shutdown junction temperature 1

T j

(1)

Cluster 1-4

Cluster 5-6

Thermal shutdown junction temperature 2

Thermal warning / shutdown filter time

1. Non-overlapping.

T j

(1)

Hysteresis

Min. Typ.

Max.

Unit

140 150 160

165

175

185

190

175 185 195

°C

µs

Devices belonging to L99DZxxx family embed a multitude of junctions (i.e. Outputs based on a PowerMOSFET stage) housed in a relatively small piece of silicon. The most complex device contains, among all the described features, 6 half-bridges (12 N-Channel

PowerMOS), 10 high-sides and two voltage regulators; all the other derivatives, even if smaller than the family super set device, still contain a significant number of junctions.

For this reason, using the Thermal Impedance of a single junction (i.e. voltage regulator or major power dissipation contributor) does not allow to predict thermal behavior of the whole device and therefore it is not possible to assess if a device is thermally suitable for a given activation profile and loads characteristics.

Thermal information is provided as temperature reading by different clusters placed close to the most dissipative junctions.

Some representative and realistic worst-case thermal profiles are described in the below paragraph.

Following measurement methods can be easily implemented, by final user, for a specific activation profile.

L99DZ120 thermal profiles

Profile 1

Battery Voltage: 16V, Ambient temperature start: 85°C

DC activation

 V1 charged with 70 mA (DC activation)

 V2 charged with 30 mA (DC activation)

 OUT7: 1 x10W bulb (DC activation)

 OUT8: 1 x 5W bulb (DC activation)

 OUT11: 300 Ω resistor (DC activation)

 OUT12: 300 Ω resistor (DC activation)

 OUT13: 300 Ω resistor (DC activation)

 OUT14: 300 Ω resistor (DC activation)

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Electrical specifications L99DZ120

Cyclic activation

 OUT4 – OUT5: 3,3 Ω resistor placed across those outputs

– 10 activations of Lock/Un-lock (250 ms ON Lock; 500 ms wait; 250 ms ON Unlock unlock; 500 ms wait)

 OUT5 – OUT6: 10 Ω resistor placed across those outputs

– (250 ms ON Safe Lock; 500 ms wait; 250 ms ON Safe unlock; 500 ms wait)

Test execution:

Once thermal equilibrium is reached with all DC load active, the “Cyclic Activation” sequence is applied.

Temperature reading is logged just at the end of the whole sequence.

Figure 3. Activation profile 1

22/161

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Figure 4. Activation profile 1 (first cycle)

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DS11567 Rev 5

L99DZ120

Note:

Electrical specifications

All curves are plotted interpolating measured samples with 15 ms of period .

Profile 2

Battery Voltage: 16V, Ambient temperature start: 85°C

DC activation

 V1 charged with 70 mA (DC activation)

 V2 charged with 30 mA (DC activation)

 OUT7: 1 x10W bulb (DC activation)

 OUT8: 1 x 5W bulb (DC activation)

 OUT11: 300 Ω resistor (DC activation)

 OUT12: 300 Ω resistor (DC activation)

 OUT13: 300 Ω resistor (DC activation

 OUT14: 300 Ω resistor (DC activation)

Cyclic activation

 OUT1 – OUT6: 6,8 Ω resistor placed across those outputs

– 2 activations (3s ON; 1s OFF; 2x)

Test execution:

Once thermal equilibrium is reached with all DC load active, the “Cyclic Activation” sequence is applied.

Figure 5. Activation profile 2

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DS11567 Rev 5

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160

Electrical specifications

Figure 6. Activation profile 2 (first cycle)

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All curves are plotted interpolating measured samples with 15 ms of period.

Figure 7. LQFP64 package and PCB thermal configuration

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24/161

Layout condition for Thermal Characterization (board finishing thickness 1.5 mm +/- 10%, board four layers, board dimension 77 mm x 114 mm, board material FR4, Cu thickness

0,070 mm for outer layers, 0.0035 mm for inner layers, thermal vias separation 1.2 mm).

DS11567 Rev 5

L99DZ120 Electrical specifications

3.4.1 Supply and supply monitoring

All SPI communication, logic and oscillator parameters are working down to V

SREG and parameters are as specified in the following chapters (guaranteed by design).

= 3.5 V

 SPI thresholds

 Oscillator frequency (delay times correctly elapsed)

 Internal register status correctly kept (reset at default values for V

SREG

< V

POR

)

 Reset threshold correctly detected

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V

S otherwise specified.

≤ 28 V; 6 V ≤ V

SREG

≤ 28 V; T j

= -40 °C to 150 °C, unless

Symbol

SUV

V hyst_UV

SOV

V hyst_OV

SREG_UV

V hyst_UV

SREG_OV

V hyst_OV t ovuv_filt

V(act)

V(BAT)

V(BAT)CS

V(BAT)CW

Table 7. Supply and supply monitoring

Parameter Test condition

undervoltage threshold

undervoltage hysteresis

increasing / decreasing

overvoltage threshold

increasing

decreasing

overvoltage hysteresis

SREG

undervoltage threshold

SREG

undervoltage hysteresis

SREG

increasing / decreasing

SREG overvoltage threshold

SREG

increasing

SREG

decreasing

SREG

overvoltage hysteresis

SREG

over/undervoltage filter time

Current consumption in Active mode

Current consumption in

V bat

_standby mode

(1)

Current consumption in

V bat

_standby mode with cyclic sense enabled

(1)

Current consumption in

V bat

_standby mode with cyclic wake enabled

(1)

= V

SREG

= 12 V; 

TxD LIN = high; V1 = ON;

V2 = ON; HS/LS Driver OFF;

CP = ON

= 12 V; Both voltage regulators deactivated; HS/LS

Driver OFF

= 12 V; Both voltage regulators deactivated;

T = 50 ms, t

= 100 µs

= 12 V; Both voltage regulators deactivated during standby phase

Min.

4.7

0.04

18.5

0.5

4.2

0.04

18.5

0.5

Typ.

Max.

Unit

0.1

5.4

0.2

22.5

1.5

4.9

0.2

22.5

1.5

64 µs

130

130 mA

µA

DS11567 Rev 5

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160

Electrical specifications L99DZ120

Symbol

Table 7. Supply and supply monitoring (continued)

Parameter Test condition Min.

Typ.

Max.

Unit

V(V1stby)

I qLIN

OUT_HS

Current consumption in

_standby mode

(1)

Current consumption in

_standby mode

(1) (2)

= 12 V; Voltage regulator V1 active; (I

OFF

= 0); HS/LS Driver

= 12 V; Voltage regulator V1 active; (I

Driver OFF

= I

CMP

); HS/LS

Current consumption in

_standby mode

(1)

= 12V; Voltage regulator V1 active; (I

Driver OFF

= I

PEAK

); HS/LS

Quiescent current adder for LIN wake up activated

Guaranteed by design

Additional bias quiescent current for switched on OUT_HS or

OUT15 by DIR or Timer; value for

1 output

Guaranteed by design

16 50

620

196

436

1100

OUTHS_DIR

I timer

Quiescent current adder if

OUT_HS and/or OUT15 are configured for Direct Drive; value during output off

Quiescent current adder if timer1 and/or timer 2 are active to provide interrupt on NINT upon timer expiration

Guaranteed by design

1. Conditions for specified current consumption: 

— V

LIN

> (V -1.5 V) 

> (V

– 1.5 V)

2. I q

= I q0

+ 2% * I

LOAD

110

µA

3.4.2 Oscillator

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V

S otherwise specified.

≤ 28 V; 6 V ≤ V

SREG

≤ 28 V; T j

= -40 °C to 150 °C, unless

Table 8. Oscillator

Symbol Parameter Test condition f

CLK1

(1) f

CLK2

(1)

Oscillation frequency OSC1

Oscillation frequency OSC2

1. OSC1: charge pump, SPI, output drivers, watchdog 

OSC2: ADC

Min.

1.66

30.4

Typ.

Max.

Unit

2.0

2.34

MHz

32.0

33.6

MHz

SREG

)

All outputs open; T j

= -40 °C to 150 °C, unless otherwise specified.

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DS11567 Rev 5

L99DZ120 Electrical specifications

Symbol Parameter

Table 9. Power-on reset (V

SREG

)

Test condition Min.

POR_R

POR_F

POR

threshold

SREG

rising

SREG

falling

(1)

2.45

1. This threshold is valid if V

SREG

had already reached V

POR_R(max)

previously.

Typ.

Max.

Unit

3.45

4.5

3.5

3.4.4 Voltage regulator V1

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 4.5 V ≤ V

≤ 28 V; 4.5 V ≤ V

SREG

≤ 28 V; T j

= -40 °C to 150 °C, unless otherwise specified.

Symbol

_low_acc

V1_ hi_acc

V1_

250mA

DP1

CC1

CCmax1

C load1 t

TSD

CMP_ris

CMP_fal

SREG_absmin

Parameter

Table 10. Voltage regulator V1

Test condition

Output voltage

SREG

absolute minimum value for controlling NRESET output

SREG

= 13.5V

rising/falling

Output voltage tolerance low accuracy mode

Output voltage tolerance high accuracy mode

LOAD

= 0 mA to I mode) or I

LOAD

(V1stdby); V

SREG

CMP

; (Active

= 0 mA to I

PEAK

= 13.5 V

LOAD

= I

CMP

to 100 mA; (Active mode) or I

LOAD

= I

PEAK

100 mA (V1stdby);

SREG

= 13.5 V

Output voltage tolerance (100 to

250mA)

LOAD

= 250 mA;

SREG

= 13.5 V

Drop-out Voltage

LOAD

= 50 mA; V

SREG

= 5 V

LOAD

= 100 mA; V

SREG

= 5 V

LOAD

= 150 mA; V

SREG

= 5 V

Output current in Active mode

Max. continuous load current

Short circuit output current

Load capacitor1

V1 deactivation time after thermal shut-down

Current comp. rising thresh

Current comp. falling threshold

Current limitation

Ceramic (+/- 20%)

Rising current

Falling current

Min.

-3

-2

-3

340

0.22

(1)

1.4

Typ.

5.0

0.2

0.3

0.45

600

2.8

Max.

Unit

0.4

0.5

0.6

250

900

4.2

% mA mA

V mA mA

µF sec

DS11567 Rev 5

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160

Electrical specifications L99DZ120

Symbol

Table 10. Voltage regulator V1 (continued)

Parameter Test condition Min.

Typ.

Max.

Unit

CMP_hys

Peak_ris

(2)

Peak_fal

(2)

Peak_hys

(2) t t t

V1short t fail

V1fail

V1FS

V1off

Current comp.

Hysteresis

Current comp. rising thresh.

Current comp. falling threshold

Current comp.

Hysteresis

Rising current

Falling current

V1 fail threshold

V1 fail filter time

V1 short filter time

V1 Fail-Safe Filter Time

V1 forced

V1 deactivation time after 8 consecutive WD failures

Tested by scan

150

1.2

200

250 mA mA mA mA ms

1. Nominal capacitor value required for stability of the regulator. Tested with 220 nF ceramic (+/- 20%). Capacitor must be located close to the regulator output pin. A 2.2 µF capacitor is recommended to minimize the DPI stress in the application.

2. In Active mode, V1 regulator is switched to high accuracy mode, dropping below the I low accuracy mode.

CMP

threshold regulator switches to

µs ms ms

Figure 8. Voltage regulator V1 characteristics (quiescent current and accuracy)

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DS11567 Rev 5

L99DZ120 Electrical specifications

3.4.5 Voltage regulator V2

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 4.5 V ≤ V

≤ 28 V; 4.5 V ≤ V

SREG

≤ 28 V; T j

= -40 °C to 150 °C, unless otherwise specified.

Symbol Parameter

Table 11. Voltage regulator V2

Test condition Min.

Typ.

Max.

Unit

_1mA

_25mA

V2_

50mA

Output voltage

Output voltage tolerance

(0 to 1 mA)

Output voltage tolerance

(1 to 25 mA)

Output voltage tolerance

(25 to 50 mA)

SREG

LOAD

= 13.5 V

= 1 mA; V

SREG

= 25 mA; V

= 50 mA; V

= 13.5 V

SREG

= 13.5 V

-6.5

-3

-4

5.0

6.5

V2_

100mA

Output voltage tolerance

(50 to 100 mA)

LOAD

= 100 mA; V

SREG

= 13.5 V -4 4 %

DP2

Drop-out voltage

LOAD

= 25 mA; V

SREG

= 5.25 V

LOAD

= 50 mA; V

SREG

= 5.25 V

LOAD

= 100 mA; V

SREG

= 13.5 V

0.3

0.4

0.8

1.6

CC2

Output current in Active mode

Max. continuous load current 50 mA

CCmax2

Short circuit output current

Current limitation 100 150 250 mA

C load

V2 fail t

V2fail t

V2short

Load capacitor

V2 fail threshold

V2 fail filter time

V2 short filter time

Ceramic (+/- 20%)

V2 forced

0.22 (1)

µs ms

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 4V ≤ V

SREG

≤ 28V; T j

= -40 °C to 150 °C, unless otherwise specified.

Table 12. Reset output

Test condition Min.

Typ.

Max.

Unit Symbol Parameter

RT1falling

RT2falling

RT3falling

Reset threshold voltage1

Reset threshold voltage2

Reset threshold voltage3

decreasing

3.25

3.55

3.75

3.5

3.8

4.0

3.7

4.2

DS11567 Rev 5

29/161

160

Electrical specifications

Symbol Parameter

Table 12. Reset output (continued)

Test condition Min.

RT4falling

RTrising t

RESET

RESET t t t

UV1

V1R

WDR

Reset threshold voltage4

decreasing

increasing

Reset Pin low output voltage

V1 > 1 V; I

RESET

= 5 mA

Reset pull up int. resistor

Reset reaction time I

LOAD

= 1 mA

V1 undervoltage filter time

Reset pulse duration

(V1 undervoltage and V1 power on reset)

Reset pulse duration

(watchdog failure)

4.1

4.67

1.5

L99DZ120

Typ.

Max.

Unit

4.3

4.5

4.8

4.87

V 0.2

0.4

16 k Ω

µs

2.0

2.5

4 5 ms

30/161

DS11567 Rev 5

L99DZ120 Electrical specifications

4.5 V ≤ V

SREG

≤ 28 V; T j

= -40 °C to 150 °C, unless otherwise specified.

Symbol

EFW3

LFW3

SW3

EFW4

LFW4

SW4 t

EFW1

LFW1

SW1

EFW2

LFW2

SW2

Parameter

Long open window

Early Failure Window 1

Late Failure Window 1

Safe Window 1

Early Failure Window 2

Late Failure Window 2

Safe Window 2

Early Failure Window 3

Late Failure Window 3

Safe Window 3

Early Failure Window 4

Late Failure Window 4

Safe Window 4

Table 13. Watchdog timing

Test condition Min.

160

7.5

100

37.5

200

400

150

Typ.

Max.

Unit

200 240

4.5

12 ms

22.3

45 ms ms ms ms

120

240 ms ms ms ms ms ms ms

DS11567 Rev 5

31/161

160

Electrical specifications

Figure 9. Watchdog timing

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32/161

DS11567 Rev 5

L99DZ120 Electrical specifications

Figure 10. Watchdog early, late and safe windows

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3.4.8 Current monitor output (CM)

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V

S otherwise specified

≤ 28V; 6 V ≤ V

SREG

≤ 28 V; T j

= -40 °C to 150 °C, unless

Symbol

CMr

Parameter

Table 14. Current monitor output (CM)

Test condition Min.

0 Functional voltage range

Current monitor output ratio:

OUT1,4,5,6 and 7 resistance)

(low on-

OUT8

(low on-resistance)

OUT 7,8

(high on-resistance)

OUT9,10,11,12,13,14,15 and HS

0 V ≤ V

≤ (V

- 1 V)

Typ.

1/10000

1/6500

1/2000

1/1000

Max.

Unit

-1V V

DS11567 Rev 5

33/161

160

Electrical specifications L99DZ120

Symbol

CM acc

Table 14. Current monitor output (CM) (continued)

Parameter Test condition Min.

Current monitor accuracy accI

CMOUT1,4,5,6 and 7 resistance)

(low on-

Current monitor accuracy accI

CMOUT 8

(low on-resistance)

Current monitor accuracy accI

CMOUT9,10,11,12,13,14,15 ,HS and OUT7,8

(high on-resistance)

Current monitor accuracy accI

CMOUT1,4,5,6 and 7 resistance)

(low on-

CM acc_2ol

Current monitor accuracy accI

CMOUT 8

(low on-resistance)

Current monitor accuracy accI

CMOUT9,11,12,13,14,15, HS and

OUT7,8

(high on-resistance)

Current monitor accuracy accI

CMOUT10

0 V ≤ V

OUTmin

≤ (V

- 1 V);

= 500 mA;

OUT4,5max

OUT1,6max

OUT7max

=7.4 A;

= 2.9 A;

= 1.4 A

0 V ≤ V

OUTmin

= 100 mA;

OUT8max

≤ (V

- 1 V);

=0.9 A

0 V ≤ V

≤ (V

- 1 V);

OUT.min

= 100 mA; I

OUT11,12,

15 HS

= 0.2 A; I

OUT7,8 max

= 0.3 A

0 V ≤ V

≤ (V

- 1 V);

OUTmin

= 2 * I

OLD

OUT4,5max

OUT1,6max

OUT7max

= 1.4 A

;

= 7.4 A;

= 2.9 A;

0 V ≤ V

≤ (V

- 1 V);

OUTmin

= 2 * I

OLD

OUT8max

= 0.9 A

;

0 V ≤ V

≤ (V

- 1 V);

OUT.min

= 2 * I

OLD

OUT9,13,14max

OUT11,12,15 HS

OUT7,8 max

;

= 0.3 A;

= 0.2 A;

= 0.3 A

0 V ≤ V

≤ (V

- 1 V);

OUT.min

= 2 * I

OLD

OUT10max

= 0.4 A

;

Typ.

Max.

Unit

4% + 1%

(1)

8% + 2%

(1)

4% + 1%

(1)

8% + 2%

(1)

4% + 1%

(1)

8% + 4%

(1) t cmb

Current monitor blanking time

1. FS (full scale) = I

OUTmax

* I

CMr

32 µs

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V

≤ 28V; T j

= -40 °C to 150 °C, unless otherwise specified.

Symbol

Table 15. Charge pump electrical characteristics

Parameter

Charge pump output voltage

Charge pump output current

(1)

Test condition

= 6 V, I

= -15 mA

≥ 10 V, I

= -15 mA

= V

+ 10 V; 

= 13.5 V;

= C

= 100 nF

Min.

22.5

Typ.

Max.

+6 V

+11 V

+12 V

+13.5

Unit

V mA

34/161

DS11567 Rev 5

L99DZ120 Electrical specifications

Symbol

Table 15. Charge pump electrical characteristics (continued)

Parameter Test condition Min.

Typ.

Max.

CPlim

Charge pump output current limitation

(2)

= V

; 

= 13.5 V;

= C

= 100 nF

CP_low

Charge pump low threshold voltage

+4.5

CP f

Charge pump low filter time

Charge Pump frequency

400

1. I

is the minimum current the device can provide to an external circuit without V

going below V

+ 10 V.

2. I

CPlim

is the maximum current, which flows out of the device in case of a short to V

+5.5

Unit mA

µs kHz

Symbol r

ON OUT1,6 r

ON OUT4 r

ON OUT5 r

ON OUT7

The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V

T j

≤ 28 V; 6 V ≤ V

= -40 °C to 150 °C, unless otherwise specified.

SREG

≤ 28 V, all outputs open; 

Table 16. Outputs OUT1 - OUT15, OUT_HS

Parameter Test condition Min.

On-resistance to supply or

GND

On-resistance to supply or

GND

On-resistance to supply or

GND

On-resistance to supply in low resistance mode

On-resistance to supply in high resistance mode

= 13.5 V; T j

OUT1,6

= ±1.5A

= 25 °C;

= 13.5V; T

OUT1,6 j

= 130 °C 

= ±1.5 A

= 13.5V; T

OUT4

= ±3 A j

= 25 °C;

= 13.5 V; T j

OUT4

= ±3 A

= 130 °C ;

= 13.5 V; T

OUT5

= ±3 A j

= 25°C;

= 13.5 V; T

OUT5

= 3 A j

= 130 °C ;

= 13.5 V; T

OUT7

= -0.8 A j

= 25 °C; 

= 13.5 V; T

OUT7

= -0.8 A j

= 130 °C ; 

= 13.5 V; T

OUT7

= -0.2 A j

= 25°C; 

= 13.5 V; T

OUT7

= -0.2 A j

= 130 °C; 

Typ.

300

150

100

500

1600

Max.

Unit

600

300

200

1000

3200 m Ω m Ω m Ω m Ω m Ω m Ω m Ω m Ω m Ω m Ω

DS11567 Rev 5

35/161

160

Electrical specifications

Symbol

Table 16. Outputs OUT1 - OUT15, OUT_HS (continued)

Parameter Test condition r r

ON OUT8

ON OUT9,10,13,14 r

ON OUT11,12,15, HS

QLH

QLL

On-resistance to supply in low resistance mode

On-resistance to supply in high resistance mode

On-resistance to supply

Switched-off output current  high-side drivers of OUT7-

15, OUT_HS

= 13.5 V; T

OUT8

= -0.4 A j

= 25 °C;

= 13.5 V; T

OUT8

= -0.4 A j

= 130 °C; 

= 13.5 V; T

OUT8

= -0.2 A j

= 25 °C; 

= 13.5 V; T

OUT8

= -0.2 A j

= 130 °C; 

= 13.5 V; T j

OUT9,10,13,14

= 25 °C;

= -75 mA

= 13.5 V; T j

OUT9,10,13,14

= 130 °C

= -75 mA

;

= 13.5 V; T j

OUT11,12,15, HS

= 25 °C;

= -75 mA

= 13.5 V; T j

OUT11,12,15, HS

= 130 °C

= -75 mA

;

OUT

= 0 V; standby mode

OUT

= 0 V; active mode

Switched-off output current  high-side drivers of OUT1-6

Switched-off output current low-side drivers of OUT1-6



OUT

= 0 V; standby mode

OUT

= 0 V; Active mode

OUT

= V

; standby mode

OUT mode

= V

- 0.5 V; active

Min.

-5

-10

-5

-100

Typ.

800

1600

2000

L99DZ120

Max.

Unit m Ω

1600 m Ω m Ω

3200 m Ω m Ω

4000 m Ω

165

Ω

µA

36/161

DS11567 Rev 5

L99DZ120 Electrical specifications

The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V otherwise specified.

≤ V

≤ 28 V; 6 V ≤ V

SREG

≤ 28 V; T j

= -40 °C to 150 °C, unless

Symbol t d ON H t d OFF H t d ON H t d OFF H t d ON L t d OFF L t d HL t d LH

Table 17. Power outputs switching times

Parameter Test condition Min.

Output delay time high-side driver on (OUT

1,4,5,6

)

Output delay time high-side driver on (OUT

7,8

)

Output delay time high-side driver off (OUT

1,4,5,6

)

Output delay time high-side driver off (OUT

7,8

)

= 13.5 V; V

= 5 V; corresponding low-side driver is not active

(1)(2)(3)

(from CSN 50% to OUT

50%) see Figure 20

V = 13.5 V; V

= 5 V

(from CSN 50% to

OUT 50%) see

Figure 20

Output delay time high-side driver on (OUT9 …OUT15, OUT_HS)

Output switch off delay time highside driver on (OUT9 …OUT15,

OUT_HS)

Output delay time low-side driver

(OUT

1-6

) on

Output delay time low-side driver

(OUT

1-6

) off

Cross current protection time

(OUT

1-6

) dV

OUT

/dt Slew rate of OUT

-OUT

SREG

= 13.5 V;

= 5 V; (from CSN 80% to

OUT 80%)

SREG

= 13.5 V;

= 5 V; (from CSN 80% to

OUT 20%)

= 13.5 V; V

= 5 V; corresponding high-side driver is not active

(1)(2)(3)

(from CSN 50% to OUT

50%) see Figure 20

V = 13.5 V; V

= 5 V

(from CSN 50% to

OUT 50%) see

Figure 20

t cc ONLS_OFFHS

– t d OFF H

(4) t cc ONHS_OFFLS

– t d OFF L

(4)

V = 13.5 V; V

= 5 V

0.1

f dVmax/dt dV

OUT f

PWMx

/dt

Maximum external applied slew rate on OUT1-OUT6 without switching on the LS and HS (only in

Active mode)

Guaranteed by design

Slew rate of OUT9-OUT15,

OUT_HS

(00) PWM switching frequency

(01) PWM switching frequency

= 5 V

= 13.5 V;

SREG

= 5 V

= 13.5 V;

SREG

= 5 V

= 13.5 V;

Typ.

150

200

0.2

100

200

Max.

Unit

300

130

300

400

0.6

µs

V/µs

DS11567 Rev 5

37/161

160

Electrical specifications L99DZ120

Symbol

Table 17. Power outputs switching times (continued)

Parameter Test condition f f

PWMx

(10) PWM switching frequency

(11) PWM switching frequency

SREG

= 5 V

= 13.5 V;

SREG

= 5 V

= 13.5 V;

1. R

LOAD

= 16 Ω at OUT

1,6

and OUT

7,8

in low on-resistance mode

2. R

LOAD

= 4 Ω at OUT

4,5

3. R

LOAD

= 128 Ω at OUT

4,9,10,11,12,13,15,15,HS

and OUT

7,8

in high on-resistance mode

4. t

is the switch-on delay time if complement in half bridge has to switch off

Min.

Typ.

330

500

Max.

Unit

Table 18. Half bridges (OUT1, OUT4, OUT5 and OUT6) OCR timing parameters

Symbol Parameter Test condition Min.

Typ.

Max.

Tblanking 40 47

Tocr_hb

Toff_hb

Guaranteed by Design 33

Over current filter time for half bridges

OFF Time for half bridges OCR_FREQ=0

OFF Time for half bridges OCR_FREQ=1

Guaranteed by Design 26

Guaranteed by Design

218

106

264

128

310

150

Unit

µs

Table 19. High-side (OUT7, OUT8 and OUT_HS) OCR timing parameters

Symbol Parameter Test condition Min.

Typ.

Max.

Tblanking 40 47

Tocr_hs

Toff_hs

Guaranteed by Design 33

Over current filter time for high-side

OFF Time for high-side

OCR_FREQ=0

Guaranteed by Design

398

OFF Time for high-side

OCR_FREQ=1

192

480

232

562

272

Unit

µs

38/161

DS11567 Rev 5

L99DZ120 Electrical specifications

Figure 11. Hard Short case, the OC threshold is reached before end of blanking time

Figure 12. Overload case, the OC threshold is reached after end of blanking time

The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V otherwise specified.

≤ V

≤ 28 V; 6 V ≤ V

SREG

≤ 28 V; T j

= -40 °C to 150 °C, unless

DS11567 Rev 5

39/161

160

Electrical specifications

Symbol

OC1

OC6

OC4

Parameter

Table 20. Current monitoring

Test condition

Overcurrent threshold HS & LS

= 13.5 V; V1 = 5 V; sink and source

= 13.5 V; V1 = 5 V; sink and source; T j

= -40 °C to

70 °C

= 13.5 V; V1 = 5 V; sink and source; T j

= 130 °C

OC5_1

OC5_2

OC5_3

= 13.5 V; V1 = 5 V; sink and source

OC7

OC_HS t

OC8

OC9

OC13

OC14

OC10

OC11

OC12

OC15

Overcurrent threshold HS in low onresistance mode

Overcurrent threshold HS in high on-resistance mode

Overcurrent threshold HS in low onresistance mode

Overcurrent threshold HS in high on-resistance mode

Overcurrent threshold HS in high current mode

Overcurrent threshold to HS in low current mode

Overcurrent threshold HS in high current mode

Overcurrent threshold HS in low current mode

Overcurrent threshold HS in high current mode

Overcurrent threshold HS in low current mode

SREG

= 13.5 V;

= 5 V; source

OUT1 to OUT6

Auto recovery time limit

OUT7, OUT8, OUT_HS

OLD1

OLD6

OLD4

OLD5

Under-current threshold HS & LS

= 13.5 V; V and source

= 5 V; sink

Min.

7.5

0.35

0.7

0.35

0.15

0.5

0.25

0.15

4.5

7.5

1.5

Typ.

100

120

150

L99DZ120

Max.

Unit

5 A

10 A

300

A ms ms mA mA

0.65

0.7

0.3

7.5

2.5

0.65

1.3

0.5

0.3

40/161

DS11567 Rev 5

L99DZ120 Electrical specifications

Symbol

OLD7

OLD8

OLD9

OLD13

OLD14

OLD10

OLD11

OLD12

OLD15

OLD_HS

| t

OL_out

Table 20. Current monitoring (continued)

Parameter Test condition Min.

Under-current threshold HS in low on-resistance mode

Under-current threshold HS in high on-resistance mode

Under-current threshold HS in low on-resistance mode

Under-current threshold HS in high on-resistance mode

Under-current threshold HS in high current mode

Under-current threshold HS in low current mode

Under -current threshold HS in high current mode

Under -current threshold HS in low current mode

Under -current threshold HS in high current mode

Under -current threshold HS in low current mode

SREG

= 13.5 V;

= 5 V; source

Filter time of open-load signal

Duration of open-load condition to set the status bit

0.5

0.3

0.85

150

Typ.

200 250 µs

Max.

Unit

60 mA

45 mA mA mA mA mA mA mA mA mA

The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V

S otherwise specified.

≤ 28 V; 6 V ≤ V

SREG

≤ 28 V; T j

= -40°C to 150 °C, unless

Symbol

GHx(Ch)

GHx

GHHx

Parameter

Average charge current

(charge stage)

Table 21. H-bridge driver

Test condition Min.

Drivers for external high-side PowerMOS

T j

= 25 °C

On-resistance (dischargestage)

Gate-on voltage

Typ.

0.3

Max.

Unit

SHx

T j

= 0 V; I

= 25 °C

GHx

= 50 mA;

6 10 14 Ω

SHx

T j

= 0 V; I

= 130 °C

GHx

= 50 mA;

= SH = 6 V; I

= 15 mA V

SHx

+ 6

14 20 Ω

= SH = 12 V; I

= 15 mA V

SHx

+ 8 V

SHx

+ 10 V

SHx

+ 11.5

DS11567 Rev 5

41/161

160

Electrical specifications L99DZ120

Symbol

GSHx

GLx(Ch)

GLx

GHLx

GSLx

Parameter

Table 21. H-bridge driver (continued)

Test condition Min.

Typ.

Max.

Unit

Passive gate-clamp resistance

GHx

= 0.5 V 15 k Ω

Average charge-current

(charge stage)

Drivers for external low-side Power-MOS

T j

= 25 °C

On-resistance (dischargestage)

Gate-on voltage

SLx

T j

= 0 V; I

= 25 °C

GHx

= 50 mA;

SLx

T j

= 0 V; I

= 130 °C

GHx

= 50 mA;

= 6 V; I

= 15 mA

= 12 V; I

= 15 mA

SLx

+ 6

0.3

Ω

SLx

+ 8 V

SLx

+ 10 V

SLx

+ 11.5

Passive gate-clamp resistance

15 k Ω

3.4.15 Gate drivers for the external Power-MOS switching times

The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V otherwise specified.

≤ V

≤ 28 V; 6 V ≤ V

SREG

≤ 28 V; T j

= -40 °C to 150 °C, unless

Symbol

GHxrmax

GHxfmax dI dI

IGHxr

IGHxf

Table 22. Gate drivers for the external Power-MOS switching times mode) mode)

Parameter

G(HL)xHL

Propagation delay time high to low

(switch mode (1)

G(HL)xLH

Propagation delay time low to high

(switch mode)

(1)

Maximum source current (current

Maximum sink current (current

Source current accuracy

Sink current accuracy

Test condition

= 13.5 V; V

SHx

= 0 Ω ; C

= 0;

= 2.7 nF

= 13.5 V; V

SLx

= 0 Ω ; C

= 0;

= 2.7 nF

= 13.5 V; V

SHx

GHx

= 1 V;

= 0;

SLEW<4:0> = 1 F

= 13.5 V, V

SHx

= 2 V;

= 0;

GHx

SLEW<4:0> = 1 F

= 13.5 V; V

SHx

GHx

= 1 V

= 0;

= 13.5 V; V

SHx

GHx

= 2 V

= 0;

Min.

Typ.

1.5

Max.

Unit

See

Figure 14: IGHxr ranges

See Figure 15: IGHxf ranges

µs

µs mA mA

DSHxrSW

DSHxfSW

Switching voltage (V

-V

) between current mode and switch mode (rising)

Switching voltage (V

-V

) between switch mode and current mode (falling)

= 13.5 V

2.8

42/161

DS11567 Rev 5

L99DZ120 Electrical specifications

Symbol

Table 22. Gate drivers for the external Power-MOS switching times (continued)

Parameter Test condition Min.

Typ.

Max.

Unit t0

GHxr t0

GHxf t0

GLxr t0

GLxf

Rise time (switch mode)

Fall time (switch mode)

Rise time

Fall time

= 13.5 V; V

SHx

= 0 Ω ; C

= 0;

= 2.7 nF

= 13.5 V; V

SHx

= 0 Ω ; C

= 0;

= 2.7 nF

= 13.5 V; V

SLx

= 0 Ω ; C

= 0;

= 2.7 nF

= 13.5 V; V

SLx

= 0 Ω ; C

= 0;

= 2.7 nF

85 ns ns ns ns tccp

0001 tccp

0010 tccp

0011 tccp

0100 tccp

0101 tccp

0110 tccp

0111 tccp

1000 tccp

1001 tccp

1010 tccp

1011 tccp

1100 tccp

1101 tccp

1110 tccp

1111

Programmable cross-current protection time

500

750

1000

1250

1500

1750

2000

2250

2500

2750

3000

3250

3500

3750

4000 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns f

PWMH

PWMH switching frequency

= 13.5 V; V

SLx

= 0 Ω ; C

= 0;

= 2.7 nF;

PWMH-Duty-Cycle = 50%; tccp configured as 0001

50 kHz

DS11567 Rev 5

43/161

160

Electrical specifications

&613:0+',5

Figure 13. H-driver delay times

*+/[/+

*+/[+/

L99DZ120

*6+/[

*$3*&)7

Figure 14. IGHxr ranges

,*+[U DFFXUDF\

44/161

,*+[U0D[

,*+[U7\S

,*+[U0LQ

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("1($'5

DS11567 Rev 5

L99DZ120

Figure 15. IGHxf ranges

,*+[I DFFXUDF\

Electrical specifications

,*+[I0D[

,*+[I7\S

,*+[I0LQ

'DWDLQSXW

("1($'5

3.4.16 Drain source monitoring external H-bridge

The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V

S otherwise specified.

≤ 28 V; 6 V ≤ V

SREG

≤ 28 V; T j

= -40°C to 150 °C, unless

Symbol

SCd1_HB

SCd2_HB

SCd3_HB

SCd4_HB

SCd5_HB

SCd6_HB

SCd7_HB t

SCd_HB t scs_HB

Table 23. Drain source monitoring external H-bridge

Parameter Test condition Min.

Typ.

Max.

Unit

Drain-source threshold voltage

Drain-source monitor filter time

Drain-source comparator settling time

= 13.5 V;

= jump from GND to V

0.375

0.6

0,85

1,06

1,27

1,49

1,7

0,5 0.625

0,75 0.9

1 1,15 V

1,25

1,5

1,75

1,43

1,73

2,01

2,3 V

µs

5 µs

The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V otherwise specified.

≤ V

≤ 28 V; 6 V ≤ V

SREG

≤ 28 V; T j

= -40 °C to 150 °C, unless

DS11567 Rev 5

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160

Electrical specifications L99DZ120

Symbol

ODSL

ODSH

OLSHx

R pdOL t

OL_HB

Table 24. Open-load monitoring external H-bridge

Parameter Test condition Min.

Low-side drain-source monitor low off-threshold voltage

Low-side drain-source monitor high off-threshold voltage

Output voltage of selected SHx in open-load test mode

Pull-down resistance of the nonselected SHx pin in open-load mode

Open-load filter time

SLx

= 0 V; V

= 13.5 V

SLx

= 0 V; V

= 13.5 V

SLx

= 0 V; V

= 13.5 V

SLx

= 0 V; V

SHX

= 4.5 V

= 13.5 V;

Typ.

0.15 V

0.85 V

0.5 V

Max.

Unit

V k Ω ms

The voltages are referred to power ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V

≤ 18 V; T j

= 40 °C to 150 °C, unless otherwise specified.

Symbol

OUT_max

R t

I t

DSON

OLimit

ONHL

OFFLH dV t

SCF max

/dt

Parameter

Table 25. Fail safe low-side switch

Test condition

Max output voltage in case of missing supply

OUT

= 1 mA; V

= V

SREG

= 0 V

DC output resistance

LOAD

= 250 mA; T j

= 25 °C

LOAD

= 250 mA; T j

= 130 °C

8 V < V

< 16 V Overcurrent limitation

Turn on delay time to

10% V

OUT

Turn off delay time to

90% V

OUT

Short circuit filter time

Maximum external applied slew rate on

LS1_FSO and LS2_FSO without switching on LS

Guaranteed by design

Min.

500

Typ.

1.4

Max.

Unit

2.5

2.2

1500

100

Ω

Ω mA

µs

V/µs

46/161

DS11567 Rev 5

L99DZ120 Electrical specifications

3.4.19 Wake up input WU

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V

SREG

≤ 28 V; T j

= 40 °C to 150 °C, unless otherwise specified.

Symbol

Table 26. Wake-up inputs

Test condition

WUthn

WUthp

HYST t

WU_stat

WU_stdby

WU_act t

WU_cyc

Parameter

Wake-up negative edge threshold voltage

Wake-up positive edge threshold voltage

Hysteresis

Static wake filter time

Input current in standby mode

Input resistor to GND in Active mode and in

Standby mode during

Wake-up input sensing

Cyclic wake filter time

< 1 V or 

> (V

SREG

– 1.5 V)

Min.

0.4

SREG

0.5

SREG

0.05

SREG

Typ.

0.45

SREG

0.55

SREG

0.1

SREG

160

Max.

Unit

0.5

SREG

0.6

SREG

0.15

SREG

µs

300

μ A k Ω

µs

LIN 2.2 compliant for bit-rates up to 20 kBit/s SAE J2602 compatible.

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V specified.

≤ V

SREG

≤ 18 V; T junction

= -40 °C to 150°C unless otherwise

Symbol

TXDLOW

TXDHIGH

TXDHYS

TXDPU

Table 27. LIN transmit data input: pin TxD

Parameter Test condition Min.

Input voltage dominant level

Input voltage recessive level

TXDHIGH

-V

TXDLOW

TXD pull up resistor

Active mode

1.0

0.2

Typ.

Max.

Unit

2.3

V k Ω

Symbol

RXDLOW

RXDHIGH

Table 28. LIN receive data output: pin RxD

Parameter Test condition Min.

Output voltage dominant level Active mode

Output voltage recessive level Active mode V1-0.5

Typ.

0.2

V1-0.2

Max.

Unit

0.5

DS11567 Rev 5

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160

Electrical specifications L99DZ120

Symbol

THdom

Table 29. LIN transmitter and receiver: pin LIN

Parameter

Receiver threshold voltage recessive to dominant state

Test condition

Min.

0.4

SREG

Typ.

0.45

SREG

Busdom

Receiver dominant state

THrec

Busrec

Receiver threshold voltage dominant to recessive state

Receiver recessive state

THhys

THcnt

THwkup

THwkdwn

Receiver threshold hysteresis: V

THrec

-V

THdom

Receiver tolerance center value: (V

THrec

THdom

)/2

Activation threshold for wake-up comparator

I t t

LINBUS dom_LIN

LINDomSC

I bus_PAS_dom bus_PAS_rec bus_NO_GND

LINdom

I bus

LINrec

LINup

LIN

LIN Bus Wake-up Dominant

Filter time

Sleep mode; edge: rec-dom

LIN Bus Wake-up Dominant

Filter time

Sleep mode; edge: rec-domrec

Transmitter input current limit in dominant state

Input leakage current at the receiver incl. pull-up resistor

Transmitter input current in recessive state

Input current if loss of GND at device

Input current if loss of V at device

BAT

TXD

= V

TXDLOW

LIN

= V

BATMAX

;

= 18 V

TXD

BAT

= V

TXDHIGH

; V

LIN

= 0 V;

= 12 V; Slave mode

In standby modes;

TXD

BAT

= V

TXDHIGH

; V

LIN

> 8 V;

< 18 V; V

LIN

≥ V

BAT

GND = V

BAT

SREG

;

0 V < V

LIN

< 18 V;

= 12 V

GND = V

; 0 V < V

Tj=-40 °C ....105 °C

< 18 V

GND = V

; 0 V < V

Tj= 130 °C (2)

LIN

< 18 V

LIN voltage level in dominant state

LIN voltage level in recessive state

Active mode;

TXD bus

= V

TXDLOW

; 

= 500 Ω

Active mode;

TXD

LIN

= V

TXDHIGH

= 10 µA

;

LIN output pull up resistor V

LIN

= 0 V

LIN input capacitance Guaranteed by design

1.0

SREG

3.5

-1

0.8*V

0.5

SREG

0.6

SREG

0.07

SREG

0.475

SREG

0.55

SREG

0.1

SREG

0.5

SREG

1.5

SREG

2.5

100

Max.

Unit

0.5

SREG

0.4V

SRE

0.6

SREG

0.175

SREG

0.525

SREG

1.5

180

1.2

100

μ mA mA

μ mA

μ k

V s s

Ω pF

48/161

DS11567 Rev 5

L99DZ120 Electrical specifications

1. 105°C is the maximum junction temperature of an unpowered device according to this test condition within the specified ambient temperature range

2. Used for device test only

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6V < V

< 28V; T j

= -40 °C to 150 °C, unless otherwise specified.

Symbol t

RXpd t

RXpd_sym

D4 t dom(TXDL)

Parameter

Table 30. LIN transceiver timing

Test condition

Receiver propagation delay time t t t

RXpd

RXpdf

= max(t

RXpdr

= t(0.5 V

RXD

)-t(0.45 V

RXD

, t

RXpdf

);

)-t(0.55 V

LIN

);

=20 pF;

LIN

SREG

= 12 V; C

RXD

C bus bus bus

= 1 k Ω , C bus

= 6.8 nF; R

= 10 nF

= 1 nF; R bus bus

= 500 Ω ,

= 660 Ω ,

Symmetry of receiver propagation delay time

(rising vs. falling edge) t

RXpd_sym

R bus

= t

RXpdr

- t

RXpdf

; V

SRE

= 1 k Ω ; C bus

= 1 nF ; C

RXD

= 12 V;

= 20 pF

Duty Cycle 1

Duty Cycle 2

Duty Cycle 3

Duty Cycle 4

Rec

Dom

(max) = 0.744 * V

SREG

(max) = 0.581 * V

= 7 to 18 V, t bit

= 50 µs;

(min) / (2 x t bit

= 1 k Ω , C bus

);

;

SREG

;

SREG

D1 = t bus_rec

R bus

C bus

= 1 nF; R bus

= 6.8 nF; R bus

= 10 nF

= 500 Ω ,

= 660 Ω ,

Rec

(min) = 0.422* V

SREG

;

Dom

(min) = 0.284* V

SREG

= 7.6 to 18 V, t bit

D2 = t bus_rec

(max) / (2 x t bit

);

;

= 50 µs;

R bus

C bus

= 1 k Ω , C bus

= 1 nF; R bus

= 6.8 nF; R bus

= 10 nF

= 500 Ω ,

= 660 Ω ,

Rec

(max) = 0.778* V

SREG

;

Dom

(max) = 0.616* V

SREG

= 96 µs;

; V

SREG

= 7 to 18 V, t bit

D3 = t

R bus

C bus

C bus bus_rec

= 10 nF

(min) / (2 x t bit

= 1 k Ω , C bus

= 6.8 nF; R

);

= 1 nF; R bus

= 500 Ω bus

= 660 Ω ,

Rec

(min) = 0.389* V

SREG

;

Dom

(min) = 0.251* V

SREG

= 7.6 to 18 V, t bit

D4 = t bus_rec

(max) / (2 x t bit

);

;

= 96 µs;

R bus

C bus

= 1 k Ω , C bus

= 1 nF; R bus

= 6.8 nF; R bus

= 10 nF

= 500 Ω ,

= 660 Ω ,

TXDL dominant timeout

Min.

-2

0.396

0.417

Typ.

Max.

Unit

0.581

0.590

μ s

μ s ms

DS11567 Rev 5

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160

Electrical specifications L99DZ120

Symbol t

LIN t dom(bus)

Parameter

Table 30. LIN transceiver timing (continued)

Test condition Min.

LIN permanent recessive time-out

LIN Bus permanent dominant time-out

Typ.

Max.

Unit

40 μ s

12 ms

Figure 16. LIN transmit, receive timing

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3.4.21 SPI

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V < V

SREG unless otherwise specified.

< 18 V; V1 = 5 V; all outputs open; T j

= -40 °C to 150 °C,

Symbol

CSNLOW

CSNHIGH

CSNHYS

CSNPU

Parameter

Table 31. Input: CSN

Test condition

Input voltage low level Normal mode

Input voltage high level Normal mode

CSNHIGH

- V

CSNLOW

CSN Pull up resistor

Normal mode

Min.

Typ.

Max.

Unit

1.0

0.2

13 29

2.3

V k Ω

Symbol t set t set_CP

Parameter

Table 32. Inputs: CLK, DI

Test condition

Delay time from standby to Active mode

Time until SPI, ADC and

OUT15/OUT_HS are operative

Delay time from standby to Active mode

Time until power stages that are supplied by the CP are operative

Min.

Typ. Max.

Unit

560 750 960

µs

50/161

DS11567 Rev 5

L99DZ120 Electrical specifications

Symbol Parameter

Table 32. Inputs: CLK, DI (continued)

Test condition Min.

Typ. Max.

Unit

V in_L in_H in_Hyst

C f pdin in

(1)

CLK

Input low level

Input high level

Input hysteresis

Pull down current at input

V in

= 1.5 V

Input capacitance at input CSN, CLK, DI and

PWM

1,2

SPI input frequency at

CLK

Guaranteed by design

1.0

0.2

5 30

1. Value of input capacity is not measured in production test. Parameter guaranteed by design.

2.3

µA pF

MHz

Symbol t

CLK t

CLKH t

CLKL t set_CSN t set_CLK t set_DI t hold_DI t r_in t f_in

Table 33. DI, CLK and CSN timing

Parameter Test condition Min.

Clock period

Clock high time

Clock low time

CSN setup time, CSN low before rising edge of CLK

CLK setup time, CLK high before rising edge of CSN

DI setup time

DI hold time

Rise time of input signal DI,

CLK, CSN

Fall time of input signal DI,

CLK, CSN

250

100

150

Typ.

Max.

Unit ns ns ns ns

25 ns ns ns ns ns

Note: See

Figure 18: SPI input timing

Symbol

DOL

DOH

DOLK

Parameter

Table 34. Output: DO

Test condition

Output low level I

= -4 mA

Output high level I

= 4 mA

3-state leakage current

CSN

= V1, 0 V < V

< V1

3-state input capacitance

Guaranteed by design

Min.

V1 - 0.5

-10

Typ.

Max.

Unit

0.5

10 μ A

10 15 pF

DS11567 Rev 5

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160

Electrical specifications L99DZ120

Note:

Symbol t r DO t f DO t en DO tri L t dis DO L tri t en DO tri H t dis DO H tri t d DO

Parameter

DO rise time

DO fall time

DO enable time from

3-state to low level

DO disable time from low level to 3-state

DO enable time from

3-state to high level

DO disable time from high level to 3-state

DO delay time

Table 35. DO timing

Test condition

= 50 pF; I

LOAD

= -1 mA

= 50 pF; I

LOAD

= -1 mA

= 50 pF; I

LOAD pull-up load to V1

= -1 mA;

= 50 pF; I

LOAD pull-up load to V1

= -1 mA;

= 50 pF; I

LOAD

= -1 mA; pull-down load to GND

= 50 pF; I

LOAD

= -1 mA; pull-down load to GND

< 0.3 V1;

> 0.7 V1; C

= 50 pF

Min.

Typ.

Max.

Unit

25 ns ns

50 100 ns

100 ns 50

50 100 ns

100

60 ns ns

See

Figure 19: SPI output timing .

Table 36. CSN timing

Test condition Symbol t

CSN_HI,min t

CSNfail

Parameter

Minimum CSN high time, active mode

CSN low timeout

Transfer of SPI-command to

Input Register

Min.

Typ.

Max.

Unit

35 50

μ s ms

Note: See

Figure 20: SPI CSN - output timing .

3.4.22 Input LIN_FLASH for Flash mode

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6V ≤ V

SREG

≤ 18; V1 = 5 V; T j

= -40 °C to 150 °C.

Symbol

V flashL

V flashH

V flashHYS

Table 37. Inputs LIN_FLASH for Flash mode

Parameter Test condition Min.

Input low level (V

LIN_FLASH for exit from Flash mode)

Input high level (V

LIN_FLASH for transition into Flash mode)

Input voltage hysteresis

6.1

7.4

0.6

Typ.

Max. Unit

7.25

8.4

0.8

8.4

9.4

1.0

52/161

DS11567 Rev 5

L99DZ120 Electrical specifications

3.4.23 Inputs DIR, DIRH, PWMH

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V

SREG

≤ 18 V; T j

= -40 °C to 150 °C.

Symbol

IHYS

I in

Parameter

Table 38. Inputs DIR, DIRH, PWMH

Input voltage low level

Input voltage high level

Input hysteresis

Input pull-down current

Test condition

SREG

= 13.5 V

SREG

= 13.5 V

SREG

= 13.5 V

SREG

= 13.5 V

Min.

Typ.

Max.

Unit

0.2

5 30

2.3

µA

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V

SREG

≤ 18 V; T j

= -40 °C to 150 °C.

Symbol

V dIL

V dIH

V dIHYS

R din

Parameter

Table 39. Debug input

Test condition

Input voltage low level V

SREG

= 13.5 V

Input voltage high level V

SREG

= 13.5 V

Input hysteresis

Pull-down resistor

SREG

= 13.5 V

DEBUG

= 6 to 18 V

Min.

Typ.

Max.

Unit

0.2

2.5

2.3

7.5

V k Ω

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V

SREG

≤ 18 V, T j

= -40 °C to 150 °C.

Symbol t con f

ADC

Acc

Parameter

Table 40. ADC characteristics

Test condition

Conversion time

Clock frequency (see f clk

Accuracy

Voltage divider + reference

(1)

Overall accuracy for WU input: WU = 22 V

Overall accuracy for WU input: WU = 18 V

Overall accuracy for WU input: WU = 6 V

Overall accuracy for WU input: WU = 4.5 V

Min.

Typ.

Max.

Unit

2.5

µs

-2

-3

-3.5

-4

-4.6

3.5

4.6

MHz

DS11567 Rev 5

53/161

160

Electrical specifications L99DZ120

Symbol

Table 40. ADC characteristics (continued)

Parameter

AINVS

Integral linearity error

Differential linearity error

Conversion voltage range (V

WU)

, V

SREG

AINTemp

Conversion voltage range (T

1 …T

1. Guaranteed by design.

Test condition Min.

Typ.

Max.

Unit

LSB

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V

SREG

≤ 18 V, T j

= -40 °C to 150 °C

Symbol

Table 41. Temperature diode characteristics

Parameter

TROOM 1-6

TSENSE1-6

SENSE output voltage at 25 °C

SENSE output voltage 1 - 8

Test condition

= 12 V; T = 25 °C

T = 25 °C; T = 130 °C; 

T = -40 °C

Min.

—

Typ.

Max.

Unit

1.4

-4

V mV/K

The voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 V ≤ V

SREG

≤ 18 V, T j

= -40 °C to 150°C

Symbol

INTL

INTH

INTLK t

Interrupt t

Int_react

Parameter

Table 42. Interrupt outputs

Test condition

Output low level I

INT

= -4 mA

Output high level I

INT

= 4 mA

3-state leakage current 0 V < V

INT

< V1

Interrupt pulse duration

(NINT, RxD_L/NINT)

Interrupt reaction time Tested by scan chain

Min.

V1 - 0.5

-10

Typ.

Max.

Unit

0.5

μ A

 s

µs

54/161

DS11567 Rev 5

L99DZ120 Electrical specifications

3.4.28 Timer1 and Timer2

6 V ≤ V

SREG

≤ 18 V; T j

= -40 °C to 150 °C

Table 43. Timer1 and Timer2

Test condition Min.

Symbol

T8 ton 1 ton 2 ton 3 ton 4 ton 5

Parameter

Timer on time

Timer period

Typ.

Max.

Unit

100

200

500

1000

2000

0.1

0.3

1 ms ms ms ms ms ms ms ms ms ms ms ms ms

Figure 17. SPI – transfer timing diagram

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The SPI can be driven by a micro controller with its SPI peripheral running in the following mode:

CPOL = 0 and CPHA = 0.

For this mode input data is sampled by the low to high transition of the clock CLK, and output data is changed from the high to low transition of CLK.

DS11567 Rev 5

55/161

160

Electrical specifications

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56/161

DS11567 Rev 5

L99DZ120

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Figure 19. SPI output timing

&/.

Electrical specifications

9FF

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DS11567 Rev 5

57/161

160

Electrical specifications L99DZ120

Figure 20. SPI CSN - output timing

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Figure 21. SPI – CSN high to low transition and global status bit access

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58/161

T j

= -40 °C to 150 °C, unless otherwise specified.

Symbol Parameter

Table 44. SGND loss comparator

Test condition Min.

SGNDloss t

SGNDloss

SGND loss threshold (V

SGND

– V

PGND )

SGND loss filter time

100

Typ.

Max.

Unit

270

500

9 mV

µs

DS11567 Rev 5

L99DZ120 Application information

, V

SREG

supplies voltage regulators V1 and V2, all internal regulated voltages for analog and digital functionality, LIN and both P-channel high-side switches OUT15 and OUT_HS.

All other high-sides, Fail Safe block and the charge pump are supplied by V

In case the V

SREG switched off.

pin is disconnected, all power outputs connected to V

are automatically

The device contains two independent and fully protected low drop voltage regulators designed for very fast transient response and do not require electrolytic output capacitors for stability.

The output voltage is stable with ceramic load capacitors >220 nF.

The V1 voltage regulator provides 5 V supply voltage and up to 250 mA continuous load current to supply the system microcontroller. The V1 regulator is embedded in the power management and fail-safe functionality of the device and operates according to the selected operating mode. The V1 voltage regulator is supplied by pin V

SREG

In addition, the V1 regulator supplies the devices internal loads. The voltage regulator is protected against overload and overtemperature. An external reverse current protection has to be provided by the application circuitry to prevent the input capacitor from being discharged by negative transients or low input voltage. Current limitation of the regulator ensures fast charge of external bypass capacitors. The output voltage is stable for ceramic load capacitors >220 nF.

In case the device temperature exceeds the TSD1 threshold (either cluster or grouped mode) the V1 regulator remains on. The micro controller has the possibility for interaction or error logging. If the chip temperature exceeds the TSD2 threshold (TSD2 > TSD1), V1 will be deactivated and all wakeup sources (LIN, WU and Timer) are disabled. After t

TSD

, the voltage regulator will restart automatically. If the restart fails 7 times within one minute the devices enter the Forced Vbat_standby mode. The status bit

FORCED_SLEEP_TSD2/V1SC (SR1) is set.

The voltage regulator V2 is supplied by pin V

SREG

and can supply additional 5 V loads such as sensors or potentiometers. The maximum continuous load current is 50 mA. The regulator is protected against:

 Overload

 Overtemperature

 Short-circuit (short to ground and battery supply voltage)

 Reverse biasing

DS11567 Rev 5

59/161

160

Application information

4.2.3

4.2.4

Voltage regulator failure

L99DZ120

The V1, and V2 regulator output voltages are monitored.

In case of a drop below the failure thresholds (V1 < V1 fail t > t

V2fail

for t > t

), the failure bits V1FAIL, V2FAIL (SR 2) are latched.

V1fail

, V2 < V2 fail

for

Short to ground detection

At turn-on of the V1 and V2 regulators, a short-to-GND condition is detected by monitoring the regulator output voltage.

If V1 or V2 is below the V1 fail

(or V2 fail

) threshold for t > t

V1short

(t > t

V2short

) after turn-on, the devices will identify a short circuit condition at the related regulator will be switched off.

In case of V1 short-to-GND the device enters Forced Vbat_standby mode automatically. Bits

FORCED_SLEEP_TSD2/V1SC and (SR 1) V1FAIL (SR 2) are set.

In case of a V2 short-to-GND failure the V2SC (SR 2) and V2FAIL (SR 2) bits are set.

Once the output voltage of the corresponding regulator exceeded the V1 fail

(V2 fail

) threshold the short-to-ground detection is disabled. In case of a short-to-ground condition, the regulator is switched off due to thermal shutdown. V1 is switched off at TSD2, V2 is switched off at TSD1.

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L99DZ120

4.2.5

Application information

Voltage regulator behavior

Figure 22. Voltage regulator behaviour and diagnosis during supply voltage

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The devices can be operated in the following operating modes:

 Active

 LIN Flash

 V1_standby

 VBAT_standby

 Debug

All functions are available and the device is controlled by SPI.

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Application information L99DZ120

To program the system microcontroller via LIN bus signals, the devices can be operated in

LIN Flash mode. The watchdog is disabled in this mode.

The Flash mode is entered by applying an external voltage at the pin:

 V

LIN_FLASH

≥ V

FlashH

(LIN Flash mode)

In LIN Flash mode the maximum bitrate is increased to 100 kbit/s automatically

(LIN_HS_EN = 1).

A transition from Flash mode to V1_standby or Vbat_standby mode is not possible.

At exit from Flash modes (V

LIN_FLASH

< V

FlashL

) no NReset pulse is generated. The watchdog starts with a Long Open Window (t

Note:

To allow software debugging, the watchdog can be deactivated by applying an external voltage to the DEBUG input pin (V debug

> V diH

In Debug mode, all device functionality and Operating modes are available. The watchdog is deactivated. At Exit from Debug mode (V debug

Open Window.

< V diL

) the watchdog starts with a Long

The device includes a test mode. This mode is activated by a dedicated sequence which includes a high voltage at the Debug Pin. The Debug Pin must be kept at nominal voltage levels in order to avoid accidental activation of the test mode.

The transition from Active mode to V1_standby mode is controlled by SPI.

To supply the micro controller in a low power mode, the V1 voltage regulator remains active.

After the V1_standby command (CSN low to high transition), the device enters V1_standby mode immediately and the watchdog starts a Long Open Window (t

). The watchdog is deactivated as soon as the V1 load current drops below the I

CMP

threshold (I

< I cmp_fal

The V1 load current monitoring can be deactivated by setting ICMP = 1. In this configuration the watchdog will be deactivated upon transition into V1_standby mode without monitoring the V1 load current.

Writing ICMP (CR 34) = 1 is only possible with the first SPI command after setting

ICMP_CONFIG_EN (Config Reg) = 1.

The ICMP_CONFIG_EN bit is reset to 0 automatically with the next SPI command.

Power outputs (except OUT_HS & OUT15) are switched off in V1_standby mode. OUT_HS

& OUT15 remain in the configuration programmed prior to the standby command in order to enable (cyclic) supply of external contacts. The timer signal (Timer1 or Timer2) can be mirrored to the NINT output pin during V1_standby mode.

LIN transmitter (TxDL) is off.

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L99DZ120

4.3.5 Interrupt

Figure 23. NINT pins

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RxDL/NINT indicates:

 a wake-up event from V1_standby mode and the programmable timer interrupt

RxDL/NINT pin is pulled low for t = t interrupt

NINT indicates:

 In Active mode:

SREG

dropped below the programmed early warning threshold in Control Register 3

SREG

< VSREG_EW_TH); feature is deactivated if VSREG_EW_TH is set to 0 V.

In V1_standby mode

– Programmable timer interrupt; An NINT pulse is generated at the beginning of the timer on-time (Timer 1 or Timer2)

– Wake-up from V1_standby mode by any wake-up source

NINT is pulled low for t = t interrupt

In case of increasing V1 load current during V1_standby mode (I

> I cmp_ris

), the device remains in standby mode and the watchdog starts with a Long Open Window. No Interrupt signal is generated.

4.4

The transition from Active mode to Vbat_standby mode is initiated by an SPI command. In

Vbat_standby mode, the voltage regulators V1 and V2 (depending on configuration in

CR 1), the power outputs (except OUT15 and OUT_HS) as well as LIN transmitter are switched off.

An NReset pulse is generated upon wake-up from Vbat_standby mode.

Wake-up from Standby modes

A wake-up from standby mode will switch the device to Active mode. This can be initiated by one or more of the following events:

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Application information L99DZ120

Wake up source

Table 45. Wake-up events description

Description

LIN bus activity

Level change of WU

Always enabled

Can be configured or disabled by SPI

>I cmp_ris

Timer Interrupt / Wake up of µC by TIMER

Device remains in V1_standby mode but watchdog is enabled (If

CMP

= 0). No interrupt is generated.

Programmable by SPI:

– V

_standby mode : device wakes up after programmable timer expiration. NINT and RxDL/NINT interrupt signals are generated

– V bat

_standby mode : device wakes up after programmable timer expiration, V1 regulator is turned on and NReset signal is generated

SPI Access

Always active (except in V

BAT_STANDBY

mode )

Wake up event: CSN is low and first rising edge on CLK

The WU input can be configured as wake-up source. The wake-up input is sensitive to any level transition (positive and negative edge) and can be configured for static or cyclic monitoring of the input voltage level.

For static contact monitoring, a filter time of t

WU_STAT

is implemented. The filter is started when the input voltage passes the specified threshold V

WU_THP

or V

WU_THN

Cyclic contact monitoring allows periodical activation of the wake-up input to read the status of the external contact. The periodical activation can be configured to Timer 1 or Timer 2.

The input signal is filtered with a filter time of t

WU_CYC

after a delay (80% of the configured

Timer on-time). A Wake-up will be processed if the status has changed versus the previous cycle. The buffered output OUT_HS can be used to supply the external contacts with the timer setting according to the cyclic monitoring of the wake-up input.

In standby modes, the input WU is configurable with an internal pull-up or pull-down current source according to the setup of the external contact. In Active mode the inputs have an internal pull down resistor (R

WU_act

) and the input status can be read by SPI. Static sense should be configured before the read operation is started in order to reflect the actual input level.

Table 46. Status of different functions/features vs operating modes

Operating modes

Function Comments

Voltage regulator V1

Voltage regulator V2

Reset generator

OUT

= 5 V

OUT

= 5 V

Active mode

On/ Off

(2)

-standby static mode (cyclic sense)

(1)

(2)

/ Off

V bat

-standby static mode (cyclic sense)

Off

(2)

/ Off

Off

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DS11567 Rev 5

L99DZ120 Application information

Table 46. Status of different functions/features vs operating modes (continued)

Operating modes

Function Comments

Active mode

-standby static mode (cyclic sense)

V bat

-standby static mode (cyclic sense)

Window watchdog

Wake up

monitor On

Off

Off (on if I

V1 and I

CMP

> I

CMP

= 0)

Active

(3)

Off

Active

(3)

HS-cyclic supply

LIN

Oscillator OSC1

Oscillator OSC2

SREG-Monitor

S-Monitor

H-bridge Gate Driver, bridge drivers, all high-side drivers

(except OUT_HS & OUT15) supplied by V

Fail-safe low-side switches

Short circuit protection for fail-safe low-side switches (in case LS is switched on)

OUT_HS & OUT15 (Pchannel HS) supplied by

SREG

Charge pump

ADC (SPI read out and

SREG

early warning interrupt)

Thermal shutdown TSD2

Thermal shutdown TSD1x for

OUT_HS and OUT15 (Pchannel HS)

Oscillator time base

LIN 2.2a

2 MHz

32 MHz

On / Off

On/ Off

(2)

(7)

(2)

Off

/ Off

(4)

On/Off

Off

(6)

Off

On/ Off

Off

On/ Off

(5)

(2)

Off

/ Off

(4)

On/Off

Off

(6)

Off

On/ Off

Off

On/ Off

(5)

(2)

1. Supply the processor in low current mode.

2. According to SPI setting and DIR.

3. Unless disabled by SPI.

4. The bus state is internally stored when going to standby mode. A change of bus state will lead to a wake-up after exceeding of internal filter time.

5. ON, if cyclic sense is enabled or during wake-up request.

6. Cyclic activation = pulsed ON during cyclic sense.

7. ON in Fail-Safe mode; if standby mode is entered with active Fail-safe mode the output remains ON in standby mode.

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Application information L99DZ120

Figure 24. Main operating modes

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Configurable window watchdog

During normal operation, the watchdog monitors the micro controller within a programmable trigger cycle.

After power-on or standby mode, the watchdog is started with a timeout (Long Open

Window t

). The timeout allows the micro controller to run its own setup and then to start the window watchdog by setting TRIG (CR1,ConfigReg) =1

Subsequently, the micro controller has to serve the watchdog by alternating the watchdog trigger bit TRIG (CR1,Config Reg) within the safe trigger area T

SWX

The trigger time is configurable by SPI. A correct watchdog trigger signal will immediately start the next cycle. After 8 watchdog failures in sequence, the V1 regulator is switched off for t

V1OFF

. After 7 additional watchdog failures the V1 regulator is turned off permanently and the device goes into Forced Vbat_standby mode. The status bit FORCED_SLEEP_WD

(SR 1) is set. A wake-up is possible by LIN.

After wake-up from Forced Vbat_standby mode and the watchdog trigger still fails, the device enters Forced Vbat_standby mode again after one Long Open Window.

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DS11567 Rev 5

L99DZ120 Application information

This actually produces an additional watchdog failure but the watchdog fail counter will remain at maximum value of 15 failures.

This sequence is repeated until a valid watchdog trigger event is performed by writing

TRIG = 1.

In case of a Watchdog failure, the power outputs and V2 are switched off and the status bit

WDFAIL (SR 1) is set to 1. A reset pulse is generated at NReset output and the device enters Fail-safe mode. Control registers are set to their Fail Safe values and the Fail-safe

low-side switches are turned on. Please refer to chapter Section 4.7: Fail-safe mode for

more details.

The following diagrams illustrate the Watchdog behavior of the devices. The diagrams are split into 3 parts. The first diagram shows the functional behavior of the watchdog without any error. The second diagram covers the behavior covering all the error conditions, which

can affect the watchdog behavior. Figure 27: Watchdog in Flash mode

shows the transition in and out of Flash modes.

Figure 25

, Figure 26 and Figure 27 can be overlapped to get all

the possible state transitions under all circumstances. For a better readability, they were split in normal operating, operating with errors and Flash mode.

Figure 25. Watchdog in normal operating mode (no errors)

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DS11567 Rev 5

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160

Application information

Figure 26. Watchdog with error conditions

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Whenever the device is operated without servicing the mandatory watchdog trigger events, a sequence of 15 consecutive reset events is performed and the device enters the

Forced_Vbat_Stby mode with bit FORCED_SLEEP_WD in SR1 set.

If the device is woken up after such a forced VBAT_Standby condition and the watchdog is still not serviced, the device, after one long open watchdog window will re-enter the same

Forced_Vbat_Stby mode until the next wake up event. In this case, an additional watchdog failure is generated, but the fail counter is not cleared, keeping the maximum number of 15 failures. This sequence is repeated until a valid watchdog trigger event is performed by writing TRIG = 1.

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DS11567 Rev 5

L99DZ120 Application information

The watchdog trigger time is configured by setting WD_TIME_x (CR 2). Writing to these bits is possible only using the first SPI command after setting WD_CONFIG_EN = 1 (Config

Reg). The WD_CONFIG_EN bit is reset to 0 automatically with the next SPI command.

The devices enter Fail-safe mode in case of:

 Watchdog failure

 V1 turn on failure

– V1 short (V1 < V1 fail

for t > t

V1short

)

 V1 failure (V1 < V

RTxfalling

for t > t

V1FS

)

 Thermal Shutdown TSD2

The Fail Safe functionality is also available in V1_Standby mode. During V1_Standby mode the Fail Safe mode is entered in the following cases:

 V1 failure (V1 < V

RTxfalling

for t > t

V1FS

)

 Watchdog failure (if watchdog still running due to I

> I cmp_fal

)

 Thermal Shutdown TSD2

In Fail Safe mode the devices return to a fail safe state. The Fail Safe condition is indicated to the system in the Global Status Byte. The conditions during Fail Safe mode are:

 All outputs beside LS1_FSO and LS2_FSO are turned off

 All Control Registers are set to fail safe default values

 Write operations to Control Registers are blocked until the Fail Safe condition is cleared. The following bits are not WRITE protected:

– TRIG (CR1<bit 0>, Config Register <bit 0>): watchdog trigger bit

– V2_x (CR1<bit 4:5>): Voltage Regulator V2 control

– CR2 (bit <8:23>): Timer1 and Timer2 settings

– OUT_HS_x (CR5 <bit 0:3>): OUT_HS configuration

– OUT15_x (CR6<bit 0:3>): OUT15 configuration

– PWMx_freq_y (CR12): PWM frequency configuration

– PWMx_DC_y (CR13 – CR17): PWM duty cycle configuration

 LIN transmitter and SPI remain on (transmitters are deactivated in case of thermal shutdown TSD1 (TSD1 cluster 5 or 6 in cluster mode)

 Corresponding Failure Bits in Status Registers are set

 FS Bit (Global Status Byte) is set

 LS1_FSO and LS2_FSO will be turned on

 Charge pump is switched off

If the Fail Safe mode was entered it keeps active until the Fail safe condition is removed and the Fail Safe was read by SPI. Depending on the root cause of the Fail Safe operation, the actions to exit Fail safe mode are as shown in the following table.

DS11567 Rev 5

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Application information L99DZ120

Failure source

Table 47. Temporary failures description

Failure condition Diagnosis Exit from Fail-safe mode

Microcontroller

(oscillator)

Temperature

Watchdog early write failure or expired window

Short at turn-on

Undervoltage

T j

> T

SD2

FS (Global Status Byte) =1;

WDFAIL (SR 1) =1;

WDFAIL_CNT_x (SR 1) = n+1

FS (Global Status Byte) =1;

FORCED_SLEEP_TSD2/V1SC

(SR 1) =1

FS (Global Status Byte) = 1; V1UV

(SR 1) = 1; V1fail (SR 2) = 1

(1)

FS (Global Status Byte) = 1; TW

(SR 2) = 1; 

TSD1 (SR 1) =1; 

TSD2 (SR 1) =1

1. If V1 < V1 fail

(for t > t

V1fail

). The Fail-safe Bit is located in the Global Status Register.

TRIG (CR 1) = 1 during long open window Read&Clear

SR1

Wake-up; 

Read&Clear SR1

V1 >V

RTrising

; 

Read&Clear SR1

T j

< T

SD2

; 

Read&Clear SR1

If the Fail-safe condition persists and all attempts to return to normal system operation fail, the devices enter the Forced Vbat_standby mode in order to prevent damage to the system.

The Forced Vbat_standby mode can be terminated by any wake-up source. The root cause of the Forced Vbat_standby mode is indicated in the SPI Status Registers.

In Forced Vbat_standby mode, all Control Registers are set to power-on default values except:

 CP_DITH_DIS (Config. Reg <bit 5>)

The Forced Vbat_standby mode is entered in case of:

 Multiple watchdog failures: FORCED_SLEEP_WD (SR 1) = 1 (15 x watchdog failure)

 Multiple thermal shutdown 2: FORCED_SLEEP_TSD2/V1SC (SR 1) = 1 (7 x TSD2)

 V1 short at turn-on (V1 < V1 fail

for t > t

V1short

FORCED_SLEEP_TSD2/V1SC (SR 1) = 1

Failure source Failure condition

Microcontroller

(Oscillator)

15 consecutive

Watchdog Failures

V1 Short at turn-on

Temperature 7 times TSD2

Table 48. Non-recoverable failure

Diagnosis Exit from Fail-safe mode

FS (Global Status Byte) = 1; WDFAIL (SR

1) = 1; FORCED_SLEEP_WD (SR 1) = 1

FS (Global Status Byte) = 1;

FORCED_SLEEP_TSD2/V1SC (SR 1) = 1

Wake-up;

TRIG (CR 1) = 1 during long open window; Read&Clear

SR1

Wake-up; 

Read&Clear SR1

FS (Global Status Byte) =1; TW (SR 2) = 1;

TSD1 (SR 1) = 1; TSD2 (SR 1) = 1;

FORCED_SLEEP_TSD2/V1SC (SR 1) = 1

Wake-up; 

Read&Clear SR1

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4.8 Reset output (NReset)

Figure 28. NReset pin

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If V1 is turned on and the voltage exceeds the V1 reset threshold, the reset output NReset is pulled up to V1 by an internal pull-up resistor after a reset delay time (t

V1R

). This is necessary for a defined start of the micro controller when the application is switched on.

Since the NReset output is realized as an open drain output it is also possible to connect an external NReset open drain NReset source to the output. As soon as the NReset is released by the devices the watchdog starts with a long open window.

A reset pulse is generated in case of:

 V1 drops below V

RTxfalling

(configurable by SPI) for t > t

UV1

 Watchdog failure

 Turn-on of the V1 regulator (V

SREG

Power-on or wake-up from Vbat_standby mode)

LIN Bus Interface

Figure 29. RxDL pin

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71/161

160

Application information L99DZ120

4.9.1 Features

 LIN 2.2a compliant (SAEJ2602 compatible) transceiver

 LIN Cell has been designed according to “Hardware requirements for transceivers

(version 1.3)”

 Bitrate up to 20 kbit/s

 Dedicated LIN Flash mode with bitrate up to 100 kbit/s

 GND disconnection fail safe at module level

 Off mode: does not disturb network

 GND shift operation at system level

 Micro controller Interface with CMOS-compatible I/O pins

 Internal pull-up resistor

 Receive-only mode

 ESD and transient immunity according to ISO7637 and EN / IEC61000-4-2

 Matched output slopes and propagation delay

 Wake-up behaviour according to LIN2.2a and Hardware Requirements for LIN, CAN and Flexray Interfaces (version 1.3)

At V

SREG

> V

POR

(i.e. V

SREG

power-on reset threshold), the LIN transceiver is enabled. The

LIN transmitter is disabled in case of the following errors:

 Dominant TxDL time out

 LIN permanent recessive

 Thermal shutdown 1

 V

SREG

overvoltage/ undervoltage

The LIN receiver is not disabled in case of any failure condition.

The default bitrate of the transceiver allows communication up to 20 kbit/s. To enable fast flashing via the LIN bus, the transceiver can be operated in high speed mode by setting bit

LIN_HS_EN (Config Reg) = 1. This feature is enabled automatically in LIN Flash mode.

The devices LIN transceiver provides the following 3 error handling features.

Dominant TxDL time out

If TXD_L is in dominant state (low) for t > t dom(TXDL) status bit LIN_TXD_DOM (SR 2) will be set.

the transmitter will be disabled, the

The transmitter remains disabled until the status bit is cleared.

The TxD dominant timeout detection can be disabled via SPI (LIN_TXD_TOUT_EN = 0).

Permanent recessive

If TXD_L changes to dominant (low) state but RXD_L signal does not follow within t < t

LIN the transmitter will be disabled, the status bit LIN_PERM_REC (SR 2) will be set.

The transmitter remains disabled until the status bit is cleared.

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4.9.3

Application information

Permanent dominant

If the bus state is dominant (low) for t > tdom(bus) a bus permanent dominant failure will be detected. The status bit LIN_PERM_DOM (SR 2) will be set.

The transmitter will not be disabled.

Wake up from Standby modes

In low power modes (V1_standby mode and Vbat_standby mode) the devices can receive two types of wake up signals from the LIN bus (configurable by SPI bit LIN_WU_CONFIG

(Config Reg)):

 Recessive-Dominant-recessive pattern with t > t dom_LIN

(default, according to LIN 2.2a)

 State Change recessive-to-dominant or dominant-to-recessive (according to LIN 2.1)

Pattern Wake-up (default)

Figure 30. Wake-up behavior according to LIN 2.2a

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Status change wake-up - Recessive-to-dominant

Normal wake-up can occur when the LIN transceiver was set in standby mode while LIN was in recessive (high) state. A dominant level at LIN for t > t to Active mode.

LINBUS

, will switch the devices

Status change wake-up - Dominant-to-recessive

If the LIN transceiver was set in standby mode while LIN was in dominant (low) state, recessive level at LIN for t > t

LINBUS

, will switch the devices to Active mode.

The LIN transmitter can be disabled in Active mode by setting the bit LIN_REC_ONLY

(CR2). In this mode it is possible to listen to the bus but not sending to it.

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Application information L99DZ120

4.10 Serial Peripheral Interface (ST SPI Standard)

Note:

A 32-bit SPI is used for bi-directional communication with the microcontroller.

The SPI is driven by a microcontroller with its SPI peripheral running in following mode:

CPOL = 0 and CPHA = 0. For this mode input data is sampled by the low to high transition of the clock CLK, and output data is changed from the high to low transition of CLK.

This device is not limited to microcontroller with a built-in SPI. Only three CMOS-compatible output pins and one input pin is needed to communicate with the device. A fault condition can be detected by setting CSN to low. If CSN = 0, the DO-Pin reflects the global error flag

(fault condition) of the device.

 Chip Select Not (CSN)

The input Pin is used to select the serial interface of this device. When CSN is high, the output Pin (DO) is in high impedance state. A low signal activates the output driver and a serial communication can be started.

The state during CSN = 0 is called a communication frame.

If CSN = low for t > t

CSNfail

the DO output is switched to high impedance in order not to block the signal line for other SPI nodes.

 Serial Data In (DI)

The input Pin is used to transfer data serial into the device. The data applied to the DI is sampled at the rising edge of the CLK signal and shifted into an internal 32-bit shift register. At the rising edge of the CSN signal the content of the shift register is transferred to Data Input Register. The writing to the selected Data Input Register is only enabled if exactly 32-bit are transmitted within one communication frame (i.e. CSN low). If more or less clock pulses are counted within one frame the complete frame is ignored. This safety function is implemented to avoid an activation of the output stages by a wrong communication frame.

Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel operation of the SPI bus by controlling the CSN signal of the connected IC's is recommended.

 Serial Data Out (DO)

The data output driver is activated by a logical low level at the CSN input and will go from high impedance to a low or high level depending on the global error flag (fault condition). The first rising edge of the CLK input after a high to low transition of the

CSN Pin will transfer the content of the selected status register into the data out shift register. Each subsequent falling edge of the CLK will shift the next bit out.

 Serial Clock (CLK)

The CLK input is used to synchronize the input and output serial bit streams. The data input (DI) is sampled at the rising edge of the CLK and the data output (DO) will change with the falling edge of the CLK signal. The SPI can be driven with a CLK Frequency up to 4 MHz.

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DS11567 Rev 5

L99DZ120 Application information

4.11.1 V

supply failure

V

overvoltage

If the supply voltages V

reaches the overvoltage threshold V

SOV

 LIN remains enabled

 OUT1 to OUT_14 are turned off (default).

The shutdown of outputs may be disabled by SPI (VS_OV_SD_EN (CR 3) = 0)

 Charge pump is disabled (and is switched on automatically in case the supply voltage recovers to normal operating voltage)

 H-bridge gate driver is switched into sink condition

 Recovery of outputs after overvoltage condition is configurable by SPI:

– VS_LOCK_EN (CR 3) = 1: outputs are off until Read&Clear VS_OV (SR 2).

– VS_LOCK_EN (CR 3) = 0: outputs turned on automatically after V

S condition has recovered.

overvoltage

 The overvoltage bit VS_OV (SR 2) is set and can be cleared with a ‘Read&Clear’ command. The overvoltage bit is reset automatically if VS_LOCK_EN (CR 3) = 0 and the overvoltage condition has recovered.

V

undervoltage

If the supply voltage V

drops below the under voltage threshold voltage (V

SUV

 LIN remains enabled

 OUT1 to OUT14 are turned off (default).

 The shutdown of outputs may be disabled by SPI (VS_UV_SD_EN (CR 3) = 0)

 Recovery of outputs after undervoltage condition is configurable by SPI:

– VS_LOCK_EN (CR 3) = 1: outputs are off until Read&Clear VS_UV (SR 2).

– VS_LOCK_EN (CR 3) = 0: outputs turned on automatically after V

S condition has recovered.

undervoltage

 The undervoltage bit VS_UV (SR 2) is set and can be cleared with a ‘Read&Clear’ command. The undervoltage bit is removed automatically if VS_LOCK_EN (CR 3) = 0 and the undervoltage condition has recovered.

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Application information L99DZ120

4.11.2 V

SREG

supply failure

V

SREG

overvoltage

If the supply voltages V

SREG

reaches the overvoltage threshold V

SREG_OV

 LIN is switched to high impedance

 OUT15 and OUT_HS are turned off (default).

The shutdown of outputs may be disabled by SPI (V

SREG_OV_SD_EN

(CR 3) = 0)

 Recovery of outputs after overvoltage condition is configurable by SPI:

– VSREG_LOCK_EN (CR 3) = 1: outputs are off until Read&Clear VSREG_OV

(SR 2).

– VSREG_LOCK_EN (CR 3) = 0: outputs turned on automatically after V

SREG overvoltage condition has recovered.

 The overvoltage bit VSREG_OV (SR 2) is set and can be cleared with a ‘Read&Clear’ command. The overvoltage bit is reset automatically if VSREG_LOCK_EN (CR 3) = 0 and the overvoltage condition has recovered.

V

SREG

undervoltage

If the supply voltage V

SREG

drops below the under voltage threshold voltage (V

SREG_UV

 LIN is switched to high impedance

 OUT15 and OUT_HS are turned off (default).

 The shutdown of outputs may be disabled by SPI (VSREG_UV_SD_EN (CR 3) = 0)

 Recovery of outputs after undervoltage condition is configurable by SPI:

– VSREG_LOCK_EN (CR 3) = 1: outputs are off until Read&Clear VSREG_UV

(SR 2).

– VSREG_LOCK_EN (CR 3) = 0: Outputs turned on automatically after V

SREG undervoltage condition has recovered.

 The undervoltage bit VSREG_UV (SR 2) is set and can be cleared with a ‘Read&Clear’ command. The undervoltage bit is removed automatically if

VSREG_LOCK_EN (CR 3) = 0 and the undervoltage condition has recovered.

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DS11567 Rev 5

L99DZ120 Application information

Figure 31. Thermal shutdown protection and diagnosis

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The Thermal State machine will recover the same state as before entering Standby mode. In case of a TSD2 it will enter TSD1 state.

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Application information L99DZ120

Note:

The component provides a total of 4 half bridges outputs OUT1, OUT4-6 to drive motors and

10 stand alone high-side outputs OUT7..15 and OUT_HS to drive e.g. LED’s, bulbs or to supply contacts. All high-side outputs beside OUT_HS and OUT15 are supplied by the pin

VS and OUT_HS and OUT15 are supplied by the buffered supply V

SREG

. OUT_HS is intended to be used as contact supply. Beside OUT15 and OUT_HS the high-side switches can be activated only in case of running charge pump. OUT15 and OUT_HS can be activated also in standby modes.

All high-side and low-side outputs switch off in case of:

 V

SREG

) overvoltage and undervoltage (depending on configuration, see

Section 4.11.2: V

SREG

supply failure

)

 Overcurrent (depending on configuration, auto recovery mode (see below)

 Overtemperature (TSD1x/ cluster or single mode)

 Fail safe event

 Loss of GND at SGND pin

In case of overcurrent or overtemperature (TSD1_CLx (SR 6)) condition, the drivers will switch off. The relevant status bit will be latched and can be read and optionally cleared by

SPI. The drivers remain off until the status is cleared. In case overvoltage/ undervoltage condition, the drivers will be switched off. The relevant status bit will be latched and can be read and optionally cleared by SPI. If VSREG_LOCK_EN (CR 3) respectively

VS_LOCK_EN (CR 3) are set, the drivers remain off until the status is cleared. If the

VS_LOCK_EN or VSREG_LOCK_EN) bit is set to 0, the drivers will switch on automatically if the error condition disappears. Undervoltage and overvoltage shutdown can be disabled by SPI. In case of open-load condition, the relevant status register will be latched. The status can be read and optionally cleared by SPI. The high and low-side outputs are not switched off in case of open-load condition.

For OUT1, OUT4-8 and OUT_HS the auto recovery feature (OUTx_OCR (CR 7)) can be enabled; half-bridges and high-side drivers have different Auto recovery frequencies

(frecx_hs and frecx_hb). If these bits are set to 1 the driver will automatically restart from an overload condition. This overload recovery feature is intended for loads which have an initial current higher than the overcurrent limit of the output (e.g. Inrush current of cold light bulbs).

The SPI bits OUTx_OCR_ALERT (SR4) indicate that the output reached auto-recovery condition.

The maximum voltage and current applied to the high-side Outputs is specified in the

‘Absolute Maximum Ratings’. Appropriate external protection may be required in order to respect these limits under application conditions. In case of outputs switch off due to loss of ground at SGND pin, the device has to be re-started through a power off on both V

SREG

and

Each of the stand alone high-side driver outputs OUT7 … OUT15 and OUT_HS can be driven with an internally generated PWM signal, an internal Timer or with DIR1 respectively

DIR2. See Table 49

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DS11567 Rev 5

L99DZ120 Application information

Table 49. Power output settings

OUTx_3 OUTx_2 OUTx_1 OUTx_0 Description

OFF

Timer1 output is controlled by timer1; starting with ON phase after timer restart

Timer2 output is controlled by timer2; starting with ON phase after timer restart

PWM1

PWM2

PWM3

PWM4

PWM5

PWM6

PWM7

PWM8

PWM9

PWM10

DIR1

DIR2

4.14 Auto-recovery alert and thermal expiration

The thermal expiration feature provides a robust protection against possible microcontroller malfunction, switching off a given channel if continuously driven in auto-recovery. If the temperature of the related cluster increases by more than 30 °C after reaching the autorecovery time t

, the channel is switched off. The thermal expiration status bit

OUTx_TH_EX (SR 3) is set.

During auto-recovery condition, OUTx_OCR_ALERT (SR 4) is set. The Alert bit indicates that an overload condition (load in-rush, short-circuit, etc) is present.

The thermal expiration feature is controlled by SPI (OUTx_OCR_THX_EN (CR 8).

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Application information L99DZ120

Figure 32. Example of long auto-recovery on OUT7. Temperature acquisition starts after t

AR thermal expiration occurs after a ∆ T = 30°

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DS11567 Rev 5

L99DZ120 Application information

Figure 33. Block diagram of physical realization of AR alert and thermal expiration

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The charge pump uses two external capacitors, which are switched with f

. The output of the charge pump has a current limitation. In standby mode and after a thermal shutdown has been triggered the charge pump is disabled. If the charge pump output voltage remains too low for longer than T

, the power-MOS outputs and the EC-control are switched off.

The H-bridge MOSFET gate drivers are switched to resistive low and CP_LOW (SR 2) is set. This bit has to be cleared to reactivate the drivers. If the bit CP_LOW_CONFIG

(Configuration Register 0x3F) is set to ‘1’, CP_LOW (SR2) behaves as a ‘live’ bit and the outputs are re-activated automatically upon recovery of the charge pump output voltage.

In case of reaching the overvoltage shutdown threshold V

SOV and automatically restarted after V

the charge pump is disabled

recovered to normal operating voltage.

Figure 34. Charge pump low filtering and start up implementation

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Each of the half bridges is built by internally connected high-side and low-side power DMOS transistors. Due to the built-in reverse diodes of the output transistors, inductive loads can

DS11567 Rev 5

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Application information L99DZ120 be driven at the outputs OUT1 and OUT4-6 without external freewheeling diodes. The highside drivers OUT7 to OUT15 and OUT_HS are intended to drive resistive loads only.

Therefore only a limited energy (E < 1 mJ) can be dissipated by the internal ESD-diodes in freewheeling condition. For inductive loads (L > 100 μ H) an external freewheeling diode connected between GND and the corresponding output is required.

The open-load detection monitors the load current in each activated output stage. If the load current is below the open-load detection threshold for t > t

OL_OUT load bit OUTx_OL (SR 5) is set in the status register.

the corresponding open-

An overcurrent condition is detected after a filter time (see Figure 11

and

Figure 12 ) and is

indicated by the status bit OUTx_OC (SR 3). In case of overcurrent, the corresponding driver switches off to reduce the power dissipation and to protect the integrated circuit. If the outputs are not configured in recovery mode, the microcontroller has to clear the relevant status bits to reactivate the corresponding drivers.

The current monitor sources a current image of the power stage output current at the current monitor pin CM, which has a fixed ratio (I

CMr

) of the instantaneous current of the selected high-side driver. The signal at output CM is blanked for t cmb

after switching on the driver until the correct settlement of the circuitry. The bits CM_SELx (CR 7) define which of the outputs is multiplexed to the current monitor output CM. The current monitor output allows a more precise analysis of the actual state of the load rather than the detection of an open-load or overload condition. For example, it can be used to detect the motor state

(starting, free running, stalled). The current monitor output is enabled after the currentmonitor blanking time, when the selected output is switched on. If this output is off, the current monitor output is in high impedance mode. The current monitor can be deactivated by CM_EN (CR 7).

4.20 PWM mode of the power outputs

Description see Section 7.3: Status register overview

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The four half-bridges of the device are cross-current protected by an internal delay time. If one driver (LS or HS) is turned off, the activation of the other driver of the same half-bridge will be automatically delayed by the crosscurrent protection time. After the crosscurrent protection time is expired the slew-rate limited switch-off phase of the driver is changed to a fast turn-off phase and the opposite driver is turned-on with slew-rate limitation. Due to this behavior, it is always guaranteed that the previously activated driver is completely turned off before the opposite driver starts to conduct.

DS11567 Rev 5

L99DZ120 Application information

4.22 Programmable soft-start function to drive loads with higher inrush current

Loads with start-up currents higher than the overcurrent limits (e.g. inrush current of lamps, start current of motors) can be driven by using the programmable soft-start function (i.e. overcurrent recovery mode). Each driver has a corresponding overcurrent recovery bit

OUTx_OCR (CR 7). If this bit is set, the device automatically switches the outputs on again after a programmable recovery time. The PWM modulated current will provide sufficient average current to power up the load (e.g. heat up the bulb) until the load reaches operating condition.

The PWM frequency is defined by setting OCR_FREQ (CR7).

The device itself cannot distinguish between a real overload (e.g. short-circuit condition) and a load characterized by operation currents exceeding the short-circuit threshold.

Examples are non-linear loads like a light bulb used on the HS outputs or a motor used on the half bridge output with inrush and stall currents that shall be limited by the auto recovery feature.

For the bulb, a real overload condition can only be qualified by time. For overload detection the microcontroller can switch on the light bulbs by setting the overcurrent recovery bit for the first e.g. 50 ms. After clearing the recovery bit, the output will be switched off automatically if the overload condition remains.

For the half bridges the high current can be present during all motor activation and another

SW strategy must be applied to identify a SC to GND or Supply. Before running the motor e.g. with a first SPI command all bridges LS are switched on (without auto recovery functionality / cleared overcurrent recovery bit), all HS are switched off and a SC to Battery can be diagnosed. With a next SPI command, all HS are switched on (without auto recovery functionality/ cleared overcurrent recovery bit) and all LS are switched off. In this sequence, a short to GND can be diagnosed. If in both sequences no overload condition is identified, the motor can be run by switching on the relevant HS and LS each configured in auto

recovery mode (see Figure 35 ). Such sequence can be applied before any motor activation

to identify SC just before operating the motor (in case the delay due to the 2 additional SPI commands is not limiting the application) or in case of power up of the system resp. applied on a certain time base.

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Application information L99DZ120

Figure 35. Software strategy for half bridges before applying auto-recovery mode

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As soon as an output reaches auto-recovery condition, OUTx_OCR_ALERT (SR 4)) is set.

The Alert bit indicates that an overload condition (load in-rush, short-circuit, etc) is present.

84/161

DS11567 Rev 5

L99DZ120

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Figure 36. Overcurrent recovery mode

Application information

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The PWMH and DIRH inputs control the drivers of the external H-bridge transistors. In single Motor mode the motor direction can be chosen with the direction input (DIRH), the duty cycle (a) and frequency with the PWMH input (single mode). With the SPI bits SD (CR

10) and SDS (CR 10) four different slow-decay modes (via drivers and via diode) can be selected using the high-side or the low-side transistors. Unconnected inputs are defined by internal pull-down current. a. If tccp is programmed to 4 µs and frequency to 50 kHz, max duty cycle achievable is 92%.

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Application information

Control pins

Control bits

Table 50. H-bridge control truth table

Failure bits Output pins

Motor config

Comment

L99DZ120

11 x

0 x

1 x x

0 x

1 x x

1 x

0 x

RL RL RL RL

2 x x 1 x x 1 0 0 0 0 RL RL RL RL

3 x x 1 x x 0 x x x 1 RL RL RL RL

4 x x 1 x x 0 1 0 0 0 L L L L

5 x x 1 x x 0 0 0 1 0 L

(1)

12 0 0 1 1 1 0 0 0 0 0 L L H L

13 1 0 1 1 1 0 0 0 0 0 H L L L

Single

H-bridge disabled

Charge pump voltage too low

Thermal shutdown

Overvoltage

Short-circuit

(1)

Bridge H2/L1 on

Slow-decay mode LS1 and

LS2 on

Slow-decay mode LS1 on

Slow-decay mode LS2 on

Bridge H1/L2 on

Slow-decay mode HS1 and

HS2 on

Slow-decay mode HS1 on

Slow-decay mode HS2 on

1. Only the H-bridge leg (low-side and high-side), in which one MOSFET is in short-circuit condition is switched off. Both

MOSFETs of the other H-bridge leg remain active and driven by DIRH and PWMH.

During watchdog long-open window, the H-bridge drivers are forced off until the first valid watchdog trigger in window mode (setting TRIG = 0 during safe window). The Control

Registers remain accessible during long open window.

86/161

The rising and falling slope of the drivers for the external high-side Power-MOS can be slew rate controlled. If this mode is enabled the gate of the external high-side Power-MOS is driven by a current source instead of a low-impedance output driver switch as long as the drain-source voltage over this Power-MOS is below the switch threshold. The current is programmed using the bits SLEW_x<4:0> (CR 10), which represent a binary number. This number is multiplied by the minimum current step. This minimum current step is the maximum source-/sink-current (I

GHxrmax

/ I

GHxfmax

) divided by 31. Programming

SLEW_x <4:0> to 0 disables the slew rate control and the output is driven by the lowimpedance output driver switch.

DS11567 Rev 5

L99DZ120

Figure 37. H-bridge GSHx slope

Application information

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The resistive output mode protects the devices and the H-bridge in the standby mode and in some failure modes (thermal shutdown TSD1 (SR 1), charge pump low CP_LOW (SR 2) and DI pin stuck at ‘1’ SPI_INV_CMD (SR 2)). When a gate driver changes into the resistive output mode due to a failure a sequence is started. In this sequence the concerning driver is switched into sink condition for 32 μ s to 64 μ s to ensure a fast switch-off of the H-bridge transistor. If slew rate control is enabled, the sink condition is slew-rate controlled.

Afterwards the driver is switched into the resistive output mode (resistive path to source).

4.26 Short circuit detection / drain source monitoring

The Drain - Source voltage of each activated external MOSFET of the H-bridge is monitored by comparators to detect shorts to ground or battery. If the voltage-drop over the external

MOSFET exceeds the configurable threshold voltage V

SCd_HB t > t

SCd_HB

(DIAG_x (CR 10) for longer

the corresponding gate driver switches off the external MOSFET and the corresponding drain source monitoring flag DS_MON_x (SR 2) is set. The DSMON_x bits have to be cleared through the SPI to reactivate the gate drivers. This monitoring is only active while the corresponding gate driver is activated. If a drain-source monitor event is detected, the corresponding gate-driver remains activated for at maximum the filter time.

When the gate driver switches on, the drain-source comparator requires the specified settling time until the drain-source monitoring is valid. During this time, this drain-source

DS11567 Rev 5

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Application information L99DZ120 monitor event may start the filter time. The threshold voltage V

SCd_HB using the SPI bits DIAG_x (CR 10).

can be programmed

Figure 38. H-bridge diagnosis

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The drain source voltages of the H-bridge driver external transistors can be monitored, while the transistors are switched off. If either bit OL_H1L2 (CR 10) or OL_H2L1 (CR 10) is set to

1, while bit HEN (CR 1) = 1, the H-drivers enter resistive low mode and the drain-source voltages can be monitored. Since the pull-up resistance is equal to the pull-down resistance on both sides of the bridge a voltage of 2/3 V

on the pull-up highside and 1/3 V

on the lowside is expected, if they drive a low-resistive inductive load (e.g. motor). If the drain source voltage on each of these Power-MOS is less than 1/6 V

S associated driver is set.

, the drain-source monitor bit of the

The open-load filter time is t

OL_HB

88/161

DS11567 Rev 5

L99DZ120 Application information

Figure 39. H-bridge open-load-detection (no open-load detected)

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Figure 40. H-bridge open-load-detection (open-load detected)

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DS11567 Rev 5

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Application information L99DZ120

Figure 41. H-bridge open-load-detection (short to ground detected)

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Table 51. H-bridge monitoring in off-mode

Control bits Failure bits

Nb OL H1L2 OL H2L1 H OLTH High DSMON LS1 DSMON LS2

1 x

0 x

Comments

Drain-Source monitor disabled

No open-load detected

Open-load SH2

Short to GND

Short to VS

No open-load detected

Open-load SH1

DS11567 Rev 5

L99DZ120 Application information

Table 51. H-bridge monitoring in off-mode (continued)

Control bits Failure bits

Comments

Nb OL H1L2 OL H2L1 H OLTH High DSMON LS1 DSMON LS2

Short to GND

Short to VS

The external PowerMOSFETs transistors in H-bridge (two half-bridges) configuration are switched on with an additional delay time t cross current protection time t

CCP

to prevent cross current in the halfbridge. The

can be programmed with the SPI bits COPT_x<3:0>

(CR 10). The timer is started when the gate driver is switched on in the device.

The PWMH module has 2 timers to configure locking time for high-side and freewheeling low-side. The programmable time t in PWM mode is the following:

CCP-TIM1

/ t

CCP-TIM2

is the same. Sequence for switching

 HS switch off after locking t

CCP-TIM1

 LS switch on after 2nd locking t

CCP-TIM1

 HS switch on after locking t

CCP-TIM2

which starts with rising edge on PWM input

Figure 43. PWMH cross current protection time implementation

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The two LS Switches LS1_FSO and LS2_FSO are intended to be used to switch off the gates of the external high-side MOSFETs in the power window h-bridge if a fatal error happens. This block must work also in case the MOSFET driver and the according control blocks on the chip are destroyed. Therefore it is necessary to have a complete separated safety block on the device, which has it’s own supply and GND connection, separated from the other supplies and GNDs. In the block is implemented an own voltage regulator and oscillator.

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The safety block is surrounded by a GND isolation ring realized by deep trench isolation.

The LS driver must work down to a lower voltage than the other circuits. The block has its own internal supply and an own oscillator for monitoring the failure signals (WWD, V1 fail,

SPI fail & Tj) which are Manchester encoded and decoupled by high ohmic resistances. In case of fail-safe event, both LS switches LS1_FSO and LS2_FSO are switched on.

In case of entering V1_standby mode or Vbat_standby mode both fail safe low-side switches are switched on to minimize the current drawn by the fail safe block (e.g. oscillator is switched off and Manchester Encoding is deactivated). Short circuit protection to V

S active in both standby modes limiting the current to I

OLimit

for a filter of t

SCF

After this filter time the fail-safe switches are switched off and LSxFSO_OC (SR 3) is set. To reactivate the low-side functionality this bit has to be set back by a read and clear command.

In case of V

loss the fail safe switches are biased by their own output voltage to turn on the low-side switches down to VOUT_max.

To allow verification of the Fail-Safe path, the low-side switches LS1_FSO and LS2_FSO can be turned on by SPI (Configuration Register 0x3F bit 4: FS_FORCED)

Figure 44. LSx_FSO: low-side driver “passively” turned on, taking supply from output pin (if main supply fails), can guarantee V

LSx_FSO

< V

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Figure 45. Safety concept

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If any of the cluster (see Section 4.31: Thermal clusters ) junction temperatures rises above

the temperature warning threshold TW, the temperature warning flag TW (SR 2) is set after the temperature warning filter time t jtft

and can be read via SPI. If the junction temperature increases above the temperature shutdown threshold (TSD1), the thermal shutdown bit

TSD1 (SR 1) is set and the power transistors of all output stages are switched off to protect the device after the thermal shutdown filter time. The gates of the H-bridge is discharged by the ‘Resistive Low’ mode. After these bits have been cleared, the output stages are reactivated. If the temperature is still above the thermal warning threshold, the thermal warning bit is set after t jtft

. Once this bit is set and the temperature is above the temperature shutdown threshold, temperature shutdown is detected after t jtft

and the outputs are switched off. Therefore the minimum time after which the outputs are switched off after the bits have been cleared in case the temperature is still above the thermal shutdown threshold is twice the thermal warning/ thermal shutdown filter time t jtft

In order to provide an advanced on-chip temperature control, the power outputs are grouped in six clusters with dedicated thermal sensors. The sensors are suitably located on the device (see

Figure 46: Thermal clusters identification ). In case the temperature of an

output cluster reaches the thermal shutdown threshold, the outputs assigned to this cluster are shut down (all other outputs remain active). Each output cluster has a dedicated temperature warning and shutdown flag (SR 6) and the cluster temperature can be read out by SPI.

Hence, the thermal cluster concept allows to identify a group of outputs in which one or more channels are in overload condition.

If thermal shutdown has occurred within an output cluster, or if temperature is rising within a cluster, it may be desired to identify which of the output (s) is (are) determining the temperature increase. An additional evaluation, based on current monitoring and cluster temperature read-out, supports identification of the outputs mainly contributing to the temperature increase. The cluster temperatures are available in SR 7, SR 8 and SR 9 and can be calculated from the binary coded register value using the following formula:

Decimal code = (350 – Temp) / 0.488

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Application information

Note:

L99DZ120

Example:

T = -40 °C => decimal code is 799 (0x31F)

T = 25 °C => decimal code is 666 (0x29A)

Thermal clusters can be configured using bit TSD_CONFIG (Config Reg):

 Standard mode (default): as soon as any cluster reaches thermal threshold the device is switched off. V1 regulator remains on and is switched off reaching TSD2.

 Cluster mode: only the cluster which reached shutdown temperature is switched off.

If Cluster Th_CL6 (global) or Cluster Th_CL5 (Voltage Regulators) reachTSD1, the whole device is OFF (beside V1).

Clusters related to power outputs (clusters 1 to 4, see

Figure 46: Thermal clusters identification

) will be managed digitally only, by mean of the ADC conversion of related thermal sensors, while clusters 5 and 6 will be managed in an analog way (comparators) since ADC can be off, e.g. in V1_standby mode. Temperature reading provided by ADC may differ from real junction temperature of a specific output due to spatial placement of thermal sensor. Such an effect is more visible during fast thermal increases of junction temperature.

Figure 46. Thermal clusters identification

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L99DZ120 Application information

Th_CL1

5 W Driver +

OUT15

Th_CL2

Door lock +

OUT_HS

Table 52. Thermal cluster definition

Th_CL3 Th_CL4

OUT1 + OUT6

10W driver high ohmic channels

TW & TSD1 Both digitally managed

Th_CL5

VREG 1

VREG 2

TW digitally managed

TSD1 & TSD2

Both analog managed

Th_CL6

Global

TW digitally managed

TSD1 Analog managed

4.32 V

S

compensation (duty cycle adjustment) module

All stand-alone HS outputs can be programmed to calculate some internal duty cycle adjustment to adapt the duty cycle to a changing supply voltage at V

. This feature is aimed to avoid LED brightness flickering in case of alternating supply voltage. The correction of the duty cycle is based on the following formula:

Equation 1: Duty cycle correction

DutyCycle =

Bat

–

LED

 DC nom

V th

= Duty cycle reference voltage: defined as 10 V

Bat

= Reference voltage: defined as voltage at pin VS

LED

= Voltage drop on the external LED

DC nom

= Nominal Duty Cycle programmed by SPI< PWMx DCx>

To be compatible to different LED load characteristics the value for V

LED

can be programmed for each output by a dedicated control register OUT7_VLED …

OUT_HS_VLED (CR 18 to CR 22). Auto compensation features can be activated for all HS outputs each by setting OUTx_AUTOCOMP_EN (CR 18 to CR 22).

The programmed LED voltage (OUTx_V_LED (CR18 to CR22)) must be lower than V th

(10 V).

Figure 47. Block diagram V

compensation (duty cycle adjustment) module

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Application information L99DZ120

4.33 Analog digital converter

Voltage signals V

, V

SREG

, V

and TH_CL1..6 are read out sequentially. The voltage signals are multiplexed to an ADC. The ADC is realized as a 10 Bit SAR, that is sampled with the main clock f clk2

/ f

ADC

Each channel will be converted with a conversion time tcon, therefore an update of the ADC value is available every t con

* 9. In case of WU is directly connected to Clamp 30, the input must be protected by a series resistance of typical 1k Ω to sustain reverse battery condition.

Figure 48. Sequential ADC Read Out for V

SREG

, V

, WU and THCL1 ..THCL6

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5 Serial Peripheral Interface (SPI)

Serial Peripheral Interface (SPI)

Note:

A 32-bit SPI is used for bi-directional communication with the microcontroller.

The SPI is driven by a microcontroller with its SPI peripheral running in the following mode:

CPOL = 0 and CPHA = 0.

For this mode input data is sampled by the low to high transition of the clock CLK, and output data is changed from the high to low transition of CLK. This device is not limited to microcontroller with a built-in SPI. Only three CMOS-compatible output Pins and one input

Pin will be needed to communicate with the device. A fault condition can be detected by setting CSN to low. If CSN = 0, the DO-Pin will reflect the global error flag (fault condition) of the device.

 Chip Select Not (CSN)

CSNfail

the DO output will be switched to high impedance in order to not block the signal line for other SPI nodes.

 Serial Data In (DI)

The input Pin is used to transfer data serial into the device. The data applied to the DI will be sampled at the rising edge of the CLK signal and shifted into an internal 32-bit shift register. At the rising edge of the CSN signal the content of the shift register will be transferred to Data Input Register. The writing to the selected Data Input Register is only enabled if exactly 32-bit are transmitted within one communication frame (i.e. CSN low). If more or less clock pulses are counted within one frame the complete frame will be ignored. This safety function is implemented to avoid an activation of the output stages by a wrong communication frame.

Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel operation of the SPI bus by controlling the CSN signal of the connected IC's is recommended.

 Serial Data Out (DO)

CSN Pin will transfer the content of the selected status register into the data out shift register. Each subsequent falling edge of the CLK will shift the next bit out.

 Serial Clock (CLK)

The ST-SPI is a standard used in ST Automotive ASSP devices.

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This chapter describes the SPI protocol standardization. It defines a common structure of the communication frames and defines specific addresses for product and status information.

The ST-SPI allows usage of generic software to operate the devices while maintaining the required flexibility to adapt it to the individual functionality of a particular product. In addition, failsafe mechanisms are implemented to protect the communication from external influences and wrong or unwanted usage.

The devices Serial Peripheral Interface are compliant to the ST SPI Standard Rev. 4.0.

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 Chip Select Not (CSN)

The communication interface is de-selected, when this input signal is logically high. A falling edge on CSN enables and starts the communication while a rising edge finishes the communication and the sent command is executed when a valid frame was sent.

During communication start and stop the Serial Clock (SCK) has to be logically low.

The Serial Data Out (SDO) is in high impedance when CSN is high or a communication timeout was detected.

 Serial Clock (SCK)

This SCK provides the clock of the SPI. Data present at Serial Data Input (SDI) is latched on the rising edge of Serial Clock (SCK) into the internal shift registers while on the falling edge data from the internal shift registers are shifted out to Serial Data Out

(SDO).

 Serial Data Input (SDI)

This input is used to transfer data serially into the device. Data is latched on the rising edge of Serial Clock (SCK).

 Serial Data Output (SDO)

This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (SCK).

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Figure 50. SDO pin

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Clock and Data Characteristics

The ST-SPI can be driven by a microcontroller with its SPI peripheral running in the following mode:

CPOL = 0

CPHA = 0

Figure 51. SPI signal description

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The communication frame starts with the falling edge of the CSN (Communication Start).

SCK has to be low.

The SDI data is then latched at all following rising SCK edges into the internal shift registers.

After Communication Start the SDO will leave 3-state mode and present the MSB of the data shifted out to SDO. At all following falling SCK edges data is shifted out through the internal shift registers to SDO.

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The communication frame is finished with the rising edge of CSN. If a valid communication took place (e.g. correct number of SCK cycles, access to a valid address), the requested operation according to the Operating Code will be performed (Write or Clear operation).

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SDI Frame

The devices Data-In Frame consist of 32-bit (OpCode (2 bits) + Address (6 bits) + Data Byte

3 + Data Byte 2 + Data Byte 1). The first two transmitted bits (MSB, MSB-1) contain the

Operation Code which represents the instruction which will be performed. The following 6 bits (MSB-2 to MSB-7) represent the address on which the operation will be performed. The subsequent bytes contain the payload.

Figure 52. SDI Frame

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Operating code

The operating code is used to distinguish between different access modes to the registers of the slave device.

OC1

OC0

Table 53. Operation codes

Description

Write Operation

Read Operation

Read & Clear Operation

Read Device Information

A Write Operation will lead to a modification of the addressed data by the payload if a write access is allowed (e.g. Control Register, valid data). Beside this a shift out of the content

(data present at Communication Start) of the registers is performed.

A Read Operation shifts out the data present in the addressed register at Communication

Start. The payload data will be ignored and internal data will not be modified. In addition a

Burst Read can be performed.

DS11567 Rev 5

L99DZ120

Note:

Serial Peripheral Interface (SPI)

A Read & Clear Operation will lead to a clear of addressed status bits. The bits to be cleared are defined first by address, second by payload bits set to ‘1’. Beside this a shift out of the content (data present at Communication Start) of the registers is performed.

Status registers which change status during communication could be cleared by the actual

Read & Clear Operation and are neither reported in actual communication nor in the following communications. To avoid a loss of any reported status it is recommended just clear status registers which are already reported in the previous communication (Selective

Bitwise Clear).

Advanced operation codes

To provide the separate write of all control registers and the bitwise clear of all status registers, two Advanced Operation Codes can be used to set all control registers to the default value and to clear all status registers. A ‘set all control registers to default’ command is performed when an OpCode ‘11’ at address b’111111 is performed.

Please consider that potential device specific write protected registers cannot be cleared with this command in therefore a device Power-on-Reset is needed.

A ‘clear all status registers’ command is performed when an OpCode ‘10’ at address b’111111 is performed.

Data-in payload

The Payload (Data Byte 1 to Data Byte 3) is the data transferred to the devices with every

SPI communication. The Payload always follows the OpCode and the Address bits. For

Write access the Payload represents the new data written to the addressed register. For

Read & Clear operations the Payload defines which bits of the adressed Status Register will be cleared. In case of a ‘1’ at the corresponding bit position the bit will be cleared.

For a Read Operation the Payload is not used. For functional safety reasons it is recommended to set unused Payload to ‘0’.

SDO frame

The data-out frame consists of 32-bit (GSB + Data Byte 1 to 3).

The first eight transmitted bits contain device related status information and are latched into the shift register at the time of the Communication Start. These 8-bit are transmitted at every

SPI transaction. The subsequent bytes contain the payload data and are latched into the shift register with the eighth positive SCK edge. This could lead to an inconsistency in data between the GSB and Payload due to different shift register load times. Anyhow, no unwanted Status Register clear should appear, as status information should just be cleared with a dedicated bit clear after.

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Global Status Byte (GSB)

The bits (Bit0 to Bit4) represent a logical OR combination of bits located in the Status

Registers. Therefore no direct Read & Clear can be performed on these bits inside the GSB.

Bit 31

GSBN

Bit 30

RSTB

Table 54. Global Status Byte

Bit 29 Bit 28 Bit 27 Bit 26

SPIE PLE FE DE

Bit 25

Bit 24

Global Status Bit Not (GSBN)

The GSBN is a logical NOR combination of Bit 24 to Bit 30. This bit can also be used as

Global Status Flag without starting a complete communication frame as it is present directly after pulling CSN low.

Reset Bit (RSTB)

The RSTB indicates a device reset. In case this bit is set, specific internal Control Registers are set to default and kept in that state until the bit is cleared. The RSTB bit is cleared after a Read & Clear of all the specific bits in the Status Registers which caused the reset event.

SPI Error (SPIE)

The SPIE is a logical OR combination of errors related to a wrong SPI communication.

Physical Layer Error (PLE)

The PLE is a logical OR combination of errors related to the LIN transceiver.

Functional Error (FE)

The FE is a logical OR combination of errors coming from functional blocks (e.g. high-side overcurrent).

Device Error (DE)

The DE is a logical OR combination of errors related to device specific blocks (e.g. VS overvoltage, overtemperature

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Global Warning (GW)

The GW is a logical OR combination of warning flags (e.g. thermal warning).

Fail Safe (FS)

The FS bit indicates that the device was forced into a safe state due to mistreatment or fundamental internal errors (e.g. Watchdog failure, Voltage regulator failure).

Data-Out Payload

The Payload (Data Bytes 1 to 3) is the data transferred from the slave device with every SPI communication to the master device. The Payload always follows the OpCode and the address bits of the actual shifted in data (In-frame-Response).

OC1

Table 55. Device application access

Operating Code

OC0

RAM Address

32H

31H

…

22H

3FH

3CH

…

1DH

…

02H

OC1

Table 56. Device information read access

Operating Code

OC0

Table 57. RAM address range

Description

Configuration Register

Status Register 12

…

Status Register 2

Status Register 1

…

Control Register 34

Control Register 29

…

Control Register 2

Access

R/C

R/W

R/C

R/W

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RAM Address

Table 57. RAM address range (continued)

Description

01H

00H

Control Register 1 reserved

Access

R/W

L99DZ120

ROM Address

0AH

…

06H

05H

12H

11H

10H

…

04H

03H

02H

01H

00H

16H

15H

14H

13H

3FH

3EH

…

20H

Table 58. ROM address range

Description

Access

Information registers

The Device Information Registers can be read by using OpCode ‘11’. After shifting out the

GSB the 8-bit wide payload will be transmitted. By reading Device Information Registers a communication width which is minimum 16-bit plus a multiple by 8 can be used. After shifting out the GSB followed by the 8-bit wide payload a series of ‘0’ is shifted out at the

SDO.

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ROM

Adress

13H

12H

11H

10H

…

0AH

3FH

3EH

…

20H

16H

15H

14H

…

06H

05H

04H

03H

02H

01H

00H

Description

Table 59. Information Registers Map

Access Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

→

C0H

7FH

C0H

41H

91H

28H

B0H major revision minor revision

L99DZ120: 01H

06H

4DH

41H

55H

01H

00H

Device Identification Registers

These registers represent a unique signature to identify the device and silicon version.

<Company Code>: 00H (STMicroelectronics)

<Device Family>: 01H (BCD Power Management)

<Device No. 1>: 55H

<Device No. 2>: 41H

<Device No. 3>: 4DH

<Device No. 4>: 06H

<Device No. 5>: for L99DZ120: 01H

SPI modes

By reading out the <SPI mode> register general information of SPI usage of the Device

Application Registers can be read.

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Serial Peripheral Interface (SPI) L99DZ120

Bit 7

Bit 6

DL2

Bit 5

Table 60. SPI Mode Register

Bit 4 Bit 3 Bit 2

DL1

DL0

Bit 1

<SPI mode>: B0H (Burst mode read available, 32-bit, no data consistency check)

SPI Burst Read

Bit 7

Table 61. Burst Read Bit

Description

BR not available

BR available

Bit 0

The SPI Burst Read bit indicates if a burst read operation is implemented. The intention of a

Burst Read is e.g. used to perform a device internal memory dump to the SPI Master.

The start of the Burst Read is like a normal Read Operation. The difference is, that after the

SPI Data Length the CSN is not pulled high and the SCK will be continuously clocked. When the normal SCK max count is reached (SPI Data Length) the consecutive addressed data will be latched into the shift register. This procedure is performed every time when the SCK payload length is reached.

In case the automatic incremented address is not used by the device, undefined data is shifted out. An automatic address overflow is implemented when address 3FH is reached.

The SPI Burst Read is limited by the CSN low timeout.

SPI Data Length

The SPI Data Length value indicates the length of the SCK count monitor which is running for all accesses to the Device Application Registers. In case a communication frame with an

SCK count is not equal to the reported one it will lead to a SPI Error and the data will be rejected.

Bit 6

DL2

Table 62. SPI Data Length

Bit 5 Bit 4

DL1

DL0

1 1

Description invalid

16-bit SPI

24-bit SPI

32-bit SPI

…

64-bit SPI

N/A

Data Consistency Check (Parity/CRC)

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Bit 1

Table 63. Data Consistency Check

Bit 0

Description not used

Parity used

CRC used

Invalid

Watchdog Definition

In case a watchdog is implemented the default settings can be read out via the Device

Information Registers .

Bit 7

WD1

Table 64. WD Type/Timing

Bit 6 Bit 5 Bit 4 Bit 3

WD0

Bit 2

Bit 1 Bit 0

<WD Type 1> 0 1

<WD Type 2> 1

WT5

WT4

WT3

WT2

WT1

WT0

Watchdog Timeout / Long Open Window WT[5:0] * 5ms

OW2 OW1 OW0

0 1 0

Open Window OW[2:0] *

5ms

CW2 CW1 CW0

0 0 1

Closed Window CW[2:0] *

5ms

<WD Type 1/2> 1 1 Invalid

<WD Type 1>: 28H (Long Open Window: 200ms)

<WD Type 2>: 91H (Open Window. 10ms, Closed Window: 5ms)

<WD Type 1> indicates the Long Open Window (timeout) which is opened at the start of the watchdog. The binary value of WT[5:0] times 5ms indicates the typical value of the Timeout

Time.

<WD Type 2> describes the default timing of the window watchdog.

The binary value of CW[2:0] times 5ms defines the typical Closed Window time and OW[2:0] times 5ms defines the typical Open Window time.

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The watchdog trigger bit location is defined by the <WD bit pos. X> registers.

Bit 7

WB1

Table 65. WD bit position

Bit 6 Bit 5 Bit 4 Bit 3

WB0

Bit 2

Bit 1 Bit 0

WBA5 WBA4 WBA3 WBA2 WBA1 WBA0

Defines the register addresses of the WD trigger bits

0 WBA5 WBA4 WBA3 WBA2 WBA1 WBA0

Defines the stop address of the address range (previous

<WD bit pos. X> is a WB = ‘01’). The consecutive <WD bit pos. X> has to be a WB = ‘11’

WBP 4 WBP3 WBP2 WBP1 WBP0

Defines the binary bit position of the WD trigger bit within the register

< WD bit pos 1>: 41H;watchdog trigger bit located at address 01H ( CR1 )

<WD bit pos 2>: C0H; watchdog trigger bit location is bit0

<WD bit pos 3>: 7FH;watchdog trigger bit located at address 3FH (Config Register)

<WD bit pos 4>: C0H; watchdog trigger bit location is bit0

DS11567 Rev 5

L99DZ120 Serial Peripheral Interface (SPI)

Device Application Registers (RAM)

The Device Application Registers are all registers accessible using OpCode ‘00’, ‘01’ and

‘10’. The functions of these registers are defined in the device specification.

To realize a protocol which covers certain failsafe requirements a basic set of failure detection mechanisms is implemented.

Clock monitor

During communication (CSN low to high phase) a clock monitor counts the valid SCK clock edges. If the SCK edges do not correlate with the SPI Data Length an SPIE is reported with the next command and the actual communication is rejected.

By accessing the Device Information Registers (OpCode = ‘11’) the Clock Monitor is set to a minimum of 16 SCK edges plus a multiple by 8 (e.g. 16, 25, 32, …). Providing no SCK edge during a CSN low to high phase is not recognized as an SPIE. For a SPI Burst Read also the SPI Data Length plus multiple numbers of Payloads SCK edges are assumed as a valid communication.

SCK Polarity (CPOL) check

To detect the wrong polarity access via SCK the internal Clock monitor is used. Providing first a negative edge on SCK during communication (CSN low to high phase) or a positive edge at last will lead to an SPI Error reported in the next communication and the actual data is rejected.

SCK Phase (CPHA) check

To verify, that the SCK Phase of the SPI master is set correctly a special Device Information

Register is implemented. By reading this register the data must be 55H. In case AAH is read the CPHA setting of the SPI master is wrong and a proper communication cannot be guaranteed.

CSN timeout

By pulling CSN low the SDO is set active and leaves its 3-state condition. To ensure communication between other SPI devices within the same bus even in case of CSN stuck at low a CSN timeout is implemented. By pulling CSN low an internal timer is started. After timer end is reached the actual communication is rejected and the SDO is set to 3-state condition.

SDI stuck at GND

As a communication with data all-‘0’ and OpCode ‘00’ on address b’000000 cannot be distinguished between a valid command and a SDI stuck at GND this communication is not allowed. Nevertheless, in case a stuck at GND is detected the communication will be rejected and the SPIE will be set with the next communication.

SDI stuck at HIGH

As a communication with data all-‘1’ and OpCode ‘11’ on address b’111111 cannot be distinguished between a valid command and a SDI stuck at HIGH this communication is not

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Serial Peripheral Interface (SPI) L99DZ120 allowed. In case a stuck at HIGH is detected the communication will be rejected and the

SPIE will be set with the next communication.

SDO stuck @

The SDO stuck at GND and stuck at HIGH have to be detected by the SPI master. As the definition of the GSB guarantees at least one toggle, a GSB with all-‘0’ or all –‘1’ reports a stuck at error.

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L99DZ120

6 Application

Application

Figure 55. Typical application diagram

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DS11567 Rev 5

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SPI Registers L99DZ120

7.1 Global Status Byte GSB

Bit name

Reset

Access

Table 66. Global Status Byte (GSB)

30 29 28 27

GSBN

RSTB

SPIE

PLE

Bit

Name

GSBN

RSTB

SPIE

(2)

Table 67. GSB signals description

Description

Global Status Bit Inverted

The GSBN is a logically NOR combination of GSB Bits 24 to Bit 30

(1)

This bit can also be used as Global Status Flag without starting a complete communication frame as it is present at SDO directly after pulling CSN low.

0: error detected (1 or several GSB bits from 24 to 30 are set)

1: no error detected (default after Power-on)

Specific failures may be masked in the Configuration Register 0x3F. A masked failure will still be reported in the GSB by the related failure flag, however it is not reflected in the GSBN (bit 31).

Reset

The RSTB indicates a device reset and it is set in case of the following events:

– VPOR (SR1 - 0x31)

– WDFAIL (SR1 - 0x31)

– V1UV (SR1 - 0x31)

– FORCED_SLEEP_TSD2/V1SC (SR1 - 0x31)

0: no reset signal has been generated (default)

1: Reset signal has been generated

RSTB is cleared by a Read & Clear command to all bits in Status Register 1 causing the Reset event.

SPI Error Bit

The SPIE indicates errors related to a wrong SPI communication.

– SPI_INV_CMD (SR2 - 0x32)

– SPI_SCK_CNT (SR2 - 0x32)

The bit is also set in case of an SPI CSN Time-out detection

0: no error (default)

1: error detected

SPIE is cleared by a valid SPI command.

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L99DZ120

Bit

SPI Registers

Name

PLE

(2)

Table 67. GSB signals description (continued)

Description

Physical Layer Error

The PLE is a logical OR combination of errors related to the LIN transceiver.

– LIN_PERM_DOM (SR2 - 0x32)

– LIN_TXD_DOM (SR2 - 0x32)

– LIN_PERM_REC (SR2 - 0x32)

0: no error (default)

1: error detected

PLE is cleared by a Read & Clear command to all related bits in Status

Registers 2 and 12 .

Functional Error Bit

The FE is a logical OR combination of errors coming from functional blocks.

– V2SC (SR2 - 0x32)

– DSMON_HSx (SR2 - 0x32)

– DSMON_LSx (SR2 - 0x32)

– OUTxHS_OC TH EX (SR3 - 0x33)

– OUTxLS_OC TH EX (SR3 - 0x33)

– OUTHS_OC TH EX (SR3 - 0x33)

– OUTx_OC (SR3 - 0x33)

– LSxFS_OC (SR3 - 0x33)

– OUTxHS_OL (SR5 - 0x35)

(3)

– OUTxLS_OL (SR5 - 0x35)

– OUTx_OL (SR5 - 0x35)

– OUTHS_OL (SR5 - 0x35)

0: no error (default)

1: error detected

FE is cleared by a Read & Clear command to all related bits in Status

Registers 2, 3, 4, 5

Device Error Bit

DE is a logical OR combination of global errors related to the device.

– VS_OV (SR2 - 0x32)

– VS_UV (SR2 - 0x32)

– VSREG_OV (SR2 - 0x32)

– VSREG_UV (SR2 - 0x32)

– CP_LOW (SR2 - 0x32)

– TSD1_CLx (SR6 - 0x36)

0: no error (default)

1: error detected

DE is cleared by a Read & Clear command to all related bits in Status

Registers 2 and 6

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SPI Registers L99DZ120

Bit Name

Table 67. GSB signals description (continued)

Description

(2)

Global Warning Bit

GW is a logical OR combination of warning flags. Warning bits do not lead to any device state change or switch off of functions.

– VSREG_EW (SR2 - 0x32)

– V1_FAIL (SR2 - 0x32)

– V2_FAIL (SR2 - 0x32)

– TW

(3)

(SR2 - 0x32)

– SPI_INV_CMD (SR2 - 0x32)

– SPI_SCK_CNT (SR2 - 0x32)

0: no error (default)

1: error detected

GW is cleared by a Read & Clear command to all related bits in Status

Register 2.

Fail Safe

The FS bit indicates the device was forced into a safe state due to the following failure conditions:

– WDFAIL (SR1 - 0x31)

– V1UV (SR1 - 0x31)

– TSD2 (SR1 - 0x31)

– FORCED_SLEEP_TSD/V1SC (SR1 - 0x31)

All Control Registers are set to default

Control Registers are blocked for WRITE access except the following bits:

– TRIG (CR1 - 0x01)

– V2_0 (CR1 - 0x01)

– V2_1 (CR1 - 0x01)

– Timer settings (bits 8…23) (CR2 - 0x02)

– OUTHS_x (bits 0…3) (CR5 - 0x05)

– OUT15_x (bits 0…3) (CR6 - 0x06)

– CR12 (0x0C) to CR17 (0x11); PWM frequency and duty cycles

0: Fail Safe inactive (default)

1: Fail Safe active

FS is cleared upon exit from Fail-Safe mode (refer to chapter ‘Fail-Safe mode’)

1. Individual failure flags may be masked in the Configuration Register (0x3F).

2. Bit may be masked in the Configuration Register (0x3F), i.e. the bit will not be included in the Global Status

Bit (GSBN).

3. Open-load status flags may be masked in the Configuration register (0x3F), i.e. the open-load flag will be included in the FE flag, but will not set the GSBN. TW failure status flags may be masked in the

Configuration register (0x3F), i.e. the TW flag will be included in the GW flag, but will not set the GSBN.

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0x02 CR2

0x03 CR3

0x04 CR4

0x05 CR5

0x06 CR6

0x07 CR7

L99DZ120

7.2 Control register overview

Table 68. Control register overview

Bit

SPI Registers

Addr. Reg. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0x00 Reserved

0x01 CR1 Reserved

Reserved

Reserved Reserved

Reserved

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SPI Registers L99DZ120

Table 68. Control register overview (continued)

Bit

Addr. Reg. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0x08 CR8 Reserved

0x09 CR9

0x0A CR10

0x0B CR11

0x0C CR12

0x0D CR13

0x0E CR14

0x0F CR15

Reserved

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Reserved

L99DZ120 SPI Registers

Table 68. Control register overview (continued)

Bit

Addr. Reg. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0x10 CR16

0x11 CR17

0x12 CR18

0x13 CR19

0x14 CR20

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SPI Registers L99DZ120

Table 68. Control register overview (continued)

Bit

Addr. Reg. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0x15 CR21

0x16 CR22

0x22 CR34

0x3F

Conf

Reg

Reserved

Note: All reserved bits (RES) are read-only (R) and will be read as ‘0’. Writing ‘1’ to a reserved bit is ignored and does not cause an SPI error.

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7.3 Status register overview

Table 69. Status register overview

Bit

Addr. Reg. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0x31 SR1 OR R

0x32 SR2 Reserved

0x33 SR3 Reserved

0x34 SR4 Reserved

0x35 SR5 Reserved

Reserved R

SO_OC R

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Table 69. Status register overview (continued)

Bit

Addr. Reg. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0x36 SR6 Reserved

_CL1 R

0x37 SR7

0x38 SR8

0x39 SR9

0x3A SR10

0x3B SR11

Reserved

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7.4.1 Control Register CR1 (0x01)

Table 70. Control Register CR1

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name Reserved

Reset

Access

0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0

R R/W R R/W R R/W

Bit

Name

Reserved

WU_EN

Reserved

WU_PU

Table 71. CR1 signals description

Description

—

Wake-up Input 1 (WU) enable

(1)

0: WU disabled

1: WU enabled (default)

—

Wake-up Input1 Pull-up/down configuration: configuration of internal current source

(1)

0: pull-down (default)

1: pull-up

Reserved —

WU_FILT_1

WU_FILT_0

Wake-up Input1 Filter configuration Bits: configuration of input filter

See Table 72: Wake-up input1 filter configuration

(1)

TIMER_NINT_WAKE_SEL

Select Timer for NINT / Wake: select timer for periodic interrupt in standby modes

0: Timer 2 (default)

1: Timer 1

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SPI Registers L99DZ120

Bit Name

Table 71. CR1 signals description (continued)

Description

13:7

TIMER_NINT_EN

Reserved

HEN

Timer NINT enable: enable timer interrupt in standby modes

0: timer interrupt disabled (default)

1: timer interrupt enabled

V1_standby mode: periodic NINT pulse generated by timer (NINT pulse at start of timer on-phase)

Vbat_standby mode: device wakes up after timer expiration and generates NReset

—

Enable H-bridge

0: H-bridge disabled (default)

1: H-bridge enabled

Refer to chapter H-bridge Control for details

V2_1

V2_0

PARITY

STBY_SEL

GO_STBY

TRIG

Voltage Regulator V2 Configuration

See Table 73: Voltage regulator V2 configuration

PARITY: Standby Command Parity Bit

STBY SEL: Select Standby mode

GO_STBY: Execute transition into Standby mode

The STBY_SEL and GO_STBY bits are protected by a parity check.

The bits STBY_SEL, GO_STBY and PARITY must represent an even number of '1', otherwise the command is ignored and the SPI_INV_CMD bit is set.

Table 74: Standby transition configuration

shows the valid settings.

All other settings are invalid; command will be ignored and SPI_INV_CMD will be set. The GO_STBY bit is not cleared automatically after wake-up.

Watchdog Trigger Bit

1. Setting is only valid if input is configured as wake-up input in Configuration Register (0x3F).

Table 72. Wake-up input1 filter configuration

WU _ FILT_1 WU _ FILT_0

0 0

Wake-up inputs monitored in static mode (filter time twu_stat) (default) t

Wake- up inputs monitored in cyclic mode with Timer2 (filter time:

WU_cyc

; blanking time 80% of timer ON time) t

Wake- up inputs monitored in cyclic mode with Timer1 (filter time:

WU_cyc

; blanking time 80% of timer ON time)

Invalid setting; command will be ignored and SPI INV CMD will be set

V2_1

Table 73. Voltage regulator V2 configuration

V2_0

V2 OFF in all modes (default)

V2 ON in Active mode; OFF in Standby modes

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V2_1

SPI Registers

Table 73. Voltage regulator V2 configuration (continued)

V2_0

V2 ON in Active and V1_standby mode; OFF in Vbat_standby mode

V2 ON in all modes

Table 74. Standby transition configuration

PARITY STBY_SEL GO_STBY

Go to V1 standby

Go to Vbat_standby

No transition to standby

7.4.2 Control Register CR2 (0x02)

Table 75. Control Register CR2

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name

Reset

Access

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0

R/W

Bit

Name

T1_RESTART

T1_DIR1

T1_ON_2

T1_ON_1

T1_ON_0

Table 76. CR2 signals description

Description

Timer 1 Restart: Restart of Timer 1

0: timer is running with period and on-time according to configuration (default)

1: restart of timer at CSN low to high transition; starting with ON phase

(1)

Bit is automatically reset with next SPI frame.

T1_DIR1: Timer 1 Direct Drive by DIR1

T1_ON_x: Timer 1 On-Time Bits

Configuration of Timer 1 on-time, for details see Table 77

and Figure 56

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SPI Registers L99DZ120

Bit

5:4

Name

Table 76. CR2 signals description (continued)

Description

T1_PER_2

T1_PER_1

T1_PER_0

T2_RESTART

Configuration of Timer 1 Period

000: T1 (default)

001: T2

010: T3

011: T4

100: T5

101: T6

110: T7

111: T8

Timer 2 Restart: restart of timer 2

0: timer is running with period and on-time according to configuration (default)

1: restart of timer at CSN low to high transition; starting with ON phase

(1)

Bit is automatically reset with next SPI frame.

T2_DIR1

T2_ON_2

T2_ON_1

T2_DIR1: Timer 2 Direct Drive by DIR1

T2_ON_x: Timer 2 On-Time Bits

Configuration of Timer 2 on-time, for details see Table 77

and Figure 56

T2_ON_0

T2_PER_2

T2_PER_1

T2_PER_0

Configuration of Timer 2 Period

000: T1 (default)

001: T2

010: T3

011: T4

100: T5

101: T6

110: T7

111: T8

LIN_REC_ONLY

LIN Transceiver Receive Only mode

0: LIN receive only mode disabled (default)

1: LIN receive only mode enabled

LIN_TXD_TOUT_EN

LIN TxD Timeout Enable

0: LIN TxD timeout detection disabled

1: LIN TxD timeout detection enabled (default)

Reserved —

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Bit Name

Table 76. CR2 signals description (continued)

Description

V1_RESET_1

V1_RESET_0

Voltage Regulator V1 Reset Threshold

00: Vrt4 (default)

01: Vrt3

10: Vrt2

11: Vrt1 thresholds are monitored in Active mode and V1_standby mode

WD_TIME_1

WD_TIME_0

Watchdog Trigger Time

00: TSW1 (default)

01: TSW2

10: TSW3

11: TSW4

Writing to WD_TIME_x is blocked unless WD CONFIG EN = 1.

The modified WD Trigger Time is valid immediately after the Write command (CSN transition low-high).

The watchdog timer is reset when the trigger time is modified (restart at CSN transition low-high).

1. Timer restart behavior: 

Write to CR2 when Tx_ON_x and Tx_PERx remain unchanged: 

Tx_RESTART = 1: timers restart at end of SPI frame, starting with ON time 

Tx_RESTART = 0: write operation to CR2 has no effect on timers 

Write to CR2 when Tx_ON_x and Tx_PERx are modified 

Tx_RESTART = 1: timers restart at end of SPI frame, starting with ON time and according to new setting (ON time and period) 

Tx_RESTART = 0: behavior is not defined; if a predictable behavior is needed, it is recommended to set Tx_RESTART = 1

Table 77. Configuration of Timer x on-time

Tx_DIR1 Tx_ON_2 Tx_ON_1 Tx_ON_0

1 (1)

(1)

1 (1)

0 ton1 (default) ton2 ton3 ton4 ton5

Invalid setting; command will be ignored and SPI

INV CMD will be set ton1 controlled by DIR1 input signal (logical AND) ton2 controlled by DIR1 input signal (logical AND) ton3 controlled by DIR1 input signal (logical AND) ton4 controlled by DIR1 input signal (logical AND) ton5 controlled by DIR1 input signal (logical AND)

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SPI Registers L99DZ120

Table 77. Configuration of Timer x on-time (continued)

Tx_DIR1 Tx_ON_2 Tx_ON_1 Tx_ON_0

(1)

1 (1)

(1)

Invalid setting; command will be ignored and SPI

INV CMD will be set

1. Tx_DIR1 = 1 is only valid for OUT7-OUT15 and OUT_HS control; the DIR1 signal has no influence for WU monitoring if WU is monitored by timer.

Figure 56. Timer_x controlled by DIR1

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7.4.3 Control Register CR3 (0x03)

Table 78. Control Register CR3

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name Reserved

Reset

Access

1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R/W

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Bit

17:10

Name

Table 79. CR3 signals description

Description

VSREG_LOCK_EN

VS_LOCK_EN

VSREG_OV_SD_EN

VSREG_UV_SD_EN

VS_OV_SD_EN

VS_UV_SD_EN

Reserved

SREG

lockout enable: Lockout of V

SREG

related outputs after V

SREG

overvoltage/ undervoltage shutdown

0: V

SREG

related Outputs are turned on automatically and status bits

(VSREG_UV, VSREG_OV) are cleared

1: V

SREG

related Outputs remain turned off until status bits (VSREG_UV,

VSREG_OV) are cleared (default)

Lockout is always disabled in standby modes in order to ensure supply of external contacts and detect wake-up conditions

lockout enable: Lockout of V

related outputs after V

over/undervoltage shutdown

0: V

related Outputs are turned on automatically and status bits (VS_UV,

VS_OV) are cleared

1: V

related Outputs remain turned off until status bits (VS_UV, VS_OV) are cleared (default)

Lockout is always disabled in standby modes in order to ensure supply of external contacts and detect wake-up conditions

SREG of V

overvoltage shutdown enable: shutdown of V

SREG

overvoltage

related outputs in case

0: no shutdown of V

SREG

related outputs in case of V

SREG

overvoltage

1: shutdown of V

SREG

related outputs in case of V

SREG

overvoltage (default)

SREG

undervoltage shutdown enable: shutdown of V

SREG

related outputs in case of V

SREG

undervoltage

0: no shutdown of V

SREG

related outputs in case of V

SREG

undervoltage

1: shutdown of V

SREG

related outputs in case of V

SREG

undervoltage (default)

In case of V1 undervoltage due to VSREG_UV, the device enters Fail-Safe mode and the outputs are turned off

overvoltage shutdown enable: shutdown of V

related outputs in case of V

S overvoltage

0: no shutdown of V

related outputs in case of V

overvoltage if charge pump output voltage is still sufficient (until CPLOW threshold is reached)

1: shutdown of V

related outputs in case of V

overvoltage (default)

undervoltage shutdown enable: shutdown of V undervoltage

related outputs in case of V

0: no shutdown V

related of outputs in case of V

undervoltage

1: shutdown of V

related outputs in case of V

undervoltage (default)

In case of V1 undervoltage due to VS_UV, the device enters Fail-Safe mode and the outputs are turned off

Reserved

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Bit

SPI Registers L99DZ120

Name

VSREG_EW_TH_9

VSREG_EW_TH_8

VSREG_EW_TH_7

VSREG_EW_TH_6

VSREG_EW_TH_5

VSREG_EW_TH_4

VSREG_EW_TH_3

VSREG_EW_TH_2

VSREG_EW_TH_1

VSREG_EW_TH_0

Table 79. CR3 signals description (continued)

Description

SREG

early warning threshold.

At V

SREG

< VSREG_EW_TH, an interrupt is generated at NINT and status bit

VSREG_EW in SR2 is set (in Active mode)

0000000000: 0 V (default) feature deactivated

...

1111111111: V

AINVS

7.4.4 Control Register CR4 (0x04)

Table 80. Control Register CR4

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name Reserved

Reset

Access

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R/W

Bit

23:22

Name

Reserved

19:10

OUT1_HS

OUT1_LS

Reserved

Table 81. CR4 signals description

Description

Reserved

OUT1 high-side Driver control

0: OUT1_HS is turned off (default)

1: OUT1_HS is turned on

An internal cross-current protection prevents, that both the low- and high-side drivers of the half-bridge OUT1 are switched on simultaneously.

OUT1 low-side Driver control

0: OUT1_LS is turned off (default)

1: OUT1_LS is turned on

An internal cross-current protection prevents, that both the low- and high-side drivers of the half-bridge OUT1 are switched on simultaneously.

Reserved

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Bit

7:6

3:2

SPI Registers

Name

OUT4_HS

OUT4_LS

Reserved

OUT5_HS

OUT5_LS

Reserved

OUT6_HS

OUT6_LS

Table 81. CR4 signals description (continued)

Description

OUT4 high-side Driver control

0: OUT4_HS is turned off (default)

1: OUT4_HS is turned on

An internal cross-current protection prevents, that both the low- and high-side drivers of the half-bridge OUT4 are switched on simultaneously.

OUT4 low-side Driver control

0: OUT4_LS is turned off (default)

1: OUT4_LS is turned on

An internal cross-current protection prevents, that both the low- and high-side drivers of the half-bridge OUT4 are switched on simultaneously.

Reserved

OUT5 high-side Driver control

0: OUT5_HS is turned off (default)

1: OUT5_HS is turned on

An internal cross-current protection prevents, that both the low- and high-side drivers of the half-bridge OUT5 are switched on simultaneously.

OUT5 low-side Driver control

0: OUT5_LS is turned off (default)

1: OUT5_LS is turned on

An internal cross-current protection prevents, that both the low- and high-side drivers of the half-bridge OUT5 are switched on simultaneously.

Reserved

OUT6 high-side Driver control

0: OUT6_HS is turned off (default)

1: OUT6_HS is turned on

An internal cross-current protection prevents, that both the low-side and high-side drivers of the half-bridge OUT6 are switched on simultaneously.

OUT6 low-side Driver control

0: OUT6_LS is turned off (default)

1: OUT6_LS is turned on

An internal cross-current protection prevents, that both the low-side and high-side drivers of the half-bridge OUT6 are switched on simultaneously.

7.4.5 Control Register CR5 (0x05)

Table 82. Control Register CR5

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name Reserved Reserved

Reset

Access

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R/W

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SPI Registers

Bit

15:12

7:4

Name

Table 83. CR5 signals description

Description

OUT7_3

OUT7_2

OUT7_1

OUT7_0

OUT8_3

OUT8_2

OUT8_1

OUT8_0

OUT7 Configuration Bits: high-side Driver OUT7 Configuration

For OUT7 bits configuration see Table 84: OUTx Configuration bits

OUT8 Configuration Bits: high-side Driver OUT8 Configuration

For OUT8 bits configuration see Table 84: OUTx Configuration bits

Reserved —

OUT10_3

OUT10_2

OUT10_1

OUT10_0

OUT10 Configuration Bits: high-side Driver OUT10 Configuration

For OUT10 bits configuration see

Reserved —

Table 84: OUTx Configuration bits

OUTHS_3

OUTHS_2 OUTHS Configuration Bits: high-side Driver OUTHS Configuration

For OUTHS bits configuration see Table 84: OUTx Configuration bits

OUTHS_1

OUTHS_0

L99DZ120

OUTx_3

OUTx_2

Table 84. OUTx Configuration bits

OUTx_1 OUTx_0 Description

Off (default)

Timer1

Timer2

PWM1

PWM2

PWM3

PWM4

PWM5

PWM6

PWM7

PWM8

PWM9

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OUTx_3

OUTx_2

Table 84. OUTx Configuration bits (continued)

OUTx_1 OUTx_0 Description

PWM10

DIR1

DIR2

7.4.6 Control Register CR6 (0x06)

Table 85. Control Register CR6

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name

Reset

Access

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R/W

Bit

Name

OUT9_3

OUT9_2

OUT9_1

OUT9_0

OUT11_3

OUT11_2

OUT11_1

OUT11_0

OUT12_3

OUT12_2

OUT12_1

OUT12_0

OUT13_3

OUT13_2

OUT13_1

OUT13_0

Table 86. CR6 signals description

Description

OUT9 Configuration Bits: high-side Driver OUT9 Configuration

For OUT9 bits configuration see Table 84: OUTx Configuration bits

OUT11 Configuration Bits: high-side Driver OUT11 Configuration

For OUT11 bits configuration see

Table 84: OUTx Configuration bits

OUT12 Configuration Bits: high-side Driver OUT12 Configuration

For OUT12 bits configuration see

Table 84: OUTx Configuration bits

OUT13 Configuration Bits: high-side Driver OUT13 Configuration

For OUT13 bits configuration see

Table 84: OUTx Configuration bits

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SPI Registers L99DZ120

Bit

Name

OUT14_3

OUT14_2

OUT14_1

OUT14_0

OUT15_3

OUT15_2

OUT15_1

OUT15_0

Table 86. CR6 signals description (continued)

Description

OUT14 Configuration Bits: high-side Driver OUT14 Configuration

For OUT14 bits configuration see

Table 84: OUTx Configuration bits

OUT15 Configuration Bits: high-side Driver OUT15 Configuration

For OUT15 bits configuration see

Table 84: OUTx Configuration bits

7.4.7 Control Register CR7 (0x07)

Table 87. Control Register CR7

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name Reserved

Reset

Access

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0

R/W

Bit

22:21

14:9

Name

OUT1_OCR

Table 88. CR7 signals description

Description

Overcurrent recovery for OUT1

0: overcurrent recovery is turned off (default)

1: overcurrent recovery is turned on

— Reserved

OUT4_OCR

OUT5_OCR

OUT6_OCR

OUT7_OCR

OUT8_OCR

Overcurrent recovery for OUTx

0: overcurrent recovery is turned off (default)

1: overcurrent recovery is turned on

OUTHS_OCR

Reserved

Overcurrent recovery for OUTHS

0: overcurrent recovery is turned off (default)

1: overcurrent recovery is turned on

—

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Bit

SPI Registers

Name

OCR_FREQ

OUT5_OC1

OUT5_OC0

CM_EN

Reserved

CM_SEL_3

CM_SEL_2

CM_SEL_1

CM_SEL_0

Table 88. CR7 signals description (continued)

Description

Overcurrent recovery frequency

0: freq0 (default)

1: freq1

Overcurrent Threshold for OUT5

00: IOC5_3 overcurrent threshold 3 (default)

01: IOC5_1 overcurrent threshold 1

10: IOC5_2 overcurrent threshold 2

11: IOC5_3 overcurrent threshold 3

Current monitor:

0: off (3-state)

1: on (default)

—

Current Monitor Select Bits.

A current image of the selected binary coded output is multiplexed to the CM output. If a corresponding output does not exist, the current monitor is deactivated.

0000: OUT1

0001: invalid configuration

0010: invalid configuration

0011: OUT4

0100: OUT5

0101: OUT6

0110: OUT7

0111: OUT8

1000: OUT9

1001: OUT10

1010: OUT11

1011: OUT12

1100: OUT13

1101: OUT14

1110: OUT15

1111: OUT_HS

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SPI Registers L99DZ120

7.4.8 Control Register CR8 (0x08)

Table 89. Control Register CR8

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name Resrved

Reset

Access

1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R/W

Bit

22:21

14:0

Name

Table 90. CR8 signals description

Description

OUT1_OCR_THX_EN

Enable Overcurrent Recovery with Thermal Expiration for OUTx.

0: Overcurrent Recovery with Thermal Expiration is off

1: Overcurrent Recovery with Thermal Expiration is on (default)

The output is turned off after Thermal Expiration.

Reserved —

OUT4_OCR_THX_EN

OUT5_OCR_THX_EN

OUT6_OCR_THX_EN

OUT7_OCR_THX_EN

OUT8_OCR_THX_EN

Enable Overcurrent Recovery with Thermal Expiration for OUTx.

0: Overcurrent Recovery with Thermal Expiration is off

1: Overcurrent Recovery with Thermal Expiration is on (default)

The output is turned off after Thermal Expiration.

OUTHS_OCR_THX_EN

Reserved

Enable Overcurrent Recovery with Thermal Expiration for OUTHS.

0: Overcurrent Recovery with Thermal Expiration is off

1: Overcurrent Recovery with Thermal Expiration is on (default)

The output is turned off after Thermal Expiration.

—

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7.4.9 Control Register CR9 (0x09)

Table 91. Control Register CR9

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name Reserved

Reset

Access

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R/W

Bit

21:16

Name

OUT7_RDSON

OUT8_RDSON

Table 92. CR9 signals description

Description

Select Rdson for OUT7

0: r on_low

(default)

1: r on_high

Select Rdson for OUT8

0: r on_low

(default)

1: r on_high

— Reserved

OUTHS_OL

OUT15_OL

OUT14_OL

OUT13_OL

OUT12_OL

OUT11_OL

OUT10_OL

OUT9_OL

OUTHS_OC

OUT15_OC

OUT14_OC

OUT13_OC

OUT12_OC

OUT11_OC

OUT10_OC

OUT9_OC

Open-load Threshold for OUTx

0: I

OLD1

; high-current mode (default)

1: I

OLD1

; low-current mode

Overcurrent Threshold for OUTx

0: I

; high-current mode (default)

1: I

; low-current mode

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SPI Registers L99DZ120

Table 93. Control Register CR10

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name Reserved

Reset

Access

1 1 1 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0

R/W

Bit

20:14

Name

Table 94. CR10 signals description

Description

DIAG_2

DIAG_1

DIAG_0

Reserved

Drain-source monitoring threshold for external H-bridge

000: V

SCd1_HB

001: V

SCd2_HB

010: V

SCd3_HB

011: V

SCd4_HB

100: V

SCd5_HB

101: V

SCd6_HB

110: V

SCd7_HB

111: V

SCd7_HB

(default)

—

SDS

Slow decay

Slow decay single

COPT_3

COPT_2

COPT_1

COPT_0

Cross current protection time

0000: not allowed

0001: tccp

0001

0010: tccp

0010

0011: tccp

0011

0100: tccp

0100

0101: tccp

0101

0110: tccp

0110

0111: tccp

0111

1000: tccp

1000

1001: tccp

1001

1010: tccp

1010

1011: tccp

1011

1100: tccp

1100

1101: tccp

1101

1110: tccp

1110

1111: tccp

1111

(default)

H_OLTH_HIGH H-bridge OL high threshold (5/6 * V

) select

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Bit

Name

OL_H1L2

OL_H2L1

SLEW_4

SLEW_3

SLEW_2

SLEW_1

SLEW_0

Table 94. CR10 signals description (continued)

Description

Test open-load condition between H1 and L2

Test open-load condition between H2 and L1

Binary coded slew rate of H-bridge (bit0 = LSB; bit4 = MSB)

00000: Control disabled (default)

11111: I

GHxmax

7.4.11 Control Register CR11 (0x0B)

Bit name

Reset

Access

Table 95. Control Register CR11

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0

R/W

Bit

23:0

Name

Reserved

Table 96. CR11 signals description

Description

—

Table 97. Control Register CR12

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name Reserved

Reset

Access

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R/W

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SPI Registers

Bit

Name

Table 98. CR12 signals description

Description

PMW1_FREQ_1 Frequency of PWM channel PWM1

00: f

PWMx

(00) (default)

PMW1_FREQ_0

01: f

PWMx

(01)

10: f

PWMx

(10)

11: f

PWMx

(11)

PMW2_FREQ_1 Frequency of PWM channel PWM2

00: f

PWMx

(00) (default)

01: f

PWMx

(01)

PMW2_FREQ_0 10: f

PWMx

(10)

11: f

PWMx

(11)

PMW3_FREQ_1 Frequency of PWM channel PWM3

00: f

PWMx

(00) (default)

PMW3_FREQ_0

01: f

PWMx

(01)

10: f

PWMx

(10)

11: f

PWMx

(11)

PMW4_FREQ_1 Frequency of PWM channel PWM4

00: f

PWMx

(00) (default)

01: f

PWMx

(01)

PMW4_FREQ_0 10: f

PWMx

(10)

11: f

PWMx

(11)

PMW5_FREQ_1 Frequency of PWM channel PWM5

00: f

PWMx

(00) (default)

PMW5_FREQ_0

01: f

PWMx

(01)

10: f

PWMx

(10)

11: f

PWMx

(11)

PMW6_FREQ_1 Frequency of PWM channel PWM6

00: f

PWMx

(00) (default)

01: f

PWMx

(01)

PMW6_FREQ_0 10: f

PWMx

(10)

11: f

PWMx

(11)

PMW7_FREQ_1 Frequency of PWM channel PWM7

00: f

PWMx

(00) (default)

PMW7_FREQ_0

01: f

PWMx

(01)

10: f

PWMx

(10)

11: f

PWMx

(11)

PMW8_FREQ_1 Frequency of PWM channel PWM8

00: f

PWMx

(00) (default)

01: f

PWMx

(01)

PMW8_FREQ_0 10: f

PWMx

(10)

11: f

PWMx

(11)

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Bit

3:0

Name

Table 98. CR12 signals description (continued)

Description

PMW9_FREQ_1 Frequency of PWM channel PWM9

00: f

PWMx

(00) (default)

PMW9_FREQ_0

01: f

PWMx

(01)

10: f

PWMx

(10)

11: f

PWMx

(11)

PMW10_FREQ_1 Frequency of PWM channel PWM10

00: f

PWMx

(00) (default)

01: f

PWMx

(01)

PMW10_FREQ_0 10: f

PWMx

(10)

11: f

PWMx

(11)

Reserved —

SPI Registers

Table 99. Control Register CR13 to CR17

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name

Reset

Access

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R/W

Bit

23:22

Where: x = 1 + (z * 2), z = 0 to 4 y = 2 + (z * 2), z = 0 to 4

Name

Reserved —

Table 100. CR13 to CR17 signals description

Description

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SPI Registers L99DZ120

Bit

11:10

Name

Table 100. CR13 to CR17 signals description (continued)

Description

PWMx_DC_9

PWMx_DC_8

PWMx_DC_7

PWMx_DC_6

PWMx_DC_5

PWMx_DC_4

PWMx_DC_3

PWMx_DC_2

PWMx_DC_1

PWMx_DC_0

Reserved

PWMy_DC_9

PWMy_DC_8

PWMy_DC_7

PWMy_DC_6

PWMy_DC_5

PWMy_DC_4

PWMy_DC_3

PWMy_DC_2

PWMy_DC_1

PWMy_DC_0

Binary coded on-dutycycle of PWM channel PWMx (bit12 = LSB; bit21 = MSB)

00 0000 0000: duty cycle 0% (default) xx xxxx xxxx: duty cycle 100%/1023 x register value

11 1111 1111. duty cycle 100%

—

Binary coded on-dutycycle of PWM channel PWMy (bit0 = LSB; bit9 = MSB)

00 0000 0000: duty cycle 0% (default) xx xxxx xxxx: duty cycle 100%/1023 x register value

11 1111 1111. Duty cycle 100%

Binary coded on-dutycycle of PWM channel PWMy

Table 101. Control Register CR18

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name

Reset

Access

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R/W

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L99DZ120 SPI Registers

Where: x = 7 + (z * 2), z = 0 to 4 y = 8 + (z * 2), z = 0 to 4

Name

Table 102. CR18 to CR22 signals description

Description

Reserved —

OUTx_AUTOCOMP_EN Setting this bit to ‘1’ enables the automatic V

compensation for OUTx

OUTx_VLED_9

OUTx_VLED_8

OUTx_VLED_7

OUTx_VLED_6

OUTx_VLED_5

OUTx_VLED_4

OUTx_VLED_3

Binary coded nominal LED voltage of OUTx (bit12 = LSB; bit21 = MSB)

00 0000 0000: V

LED

= 0 V (default) xx xxxx xxxx: V

LED

= V

AINVS

/1023 x register value

01 1101 0000: V

LED

= V

AINVS

LED

is clamped at 10 V (0x1D0h)

OUTx_VLED_2

OUTx_VLED_1

OUTx_VLED_0

Reserved —

OUTy_AUTOCOMP_EN Setting this bit to ‘1’ enables the automatic V

compensation for OUTy

OUTy_VLED_9

OUTy_VLED_8

OUTy_VLED_7

OUTy_VLED_6

OUTy_VLED_5

OUTy_VLED_4

OUTy_VLED_3

OUTy_VLED_2

OUTy_VLED_1

OUTy_VLED_0

Binary coded nominal LED voltage of OUTy (bit0 = LSB; bit9 = MSB)

00 0000 0000: V

LED

= 0 V (default) xx xxxx xxxx: V

LED

= V

AINVS

/1023 x register value

01 1101 0000: V

LED

= V

AINVS

LED

is clamped at 10 V (0x1D0h)

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SPI Registers L99DZ120

Table 103. Control Register CR34

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name

Reset

Access

Reserved

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

R/W

Bit

23:3

Name

Reserved

CP_OFF

ICMP

WD_EN

Table 104. CR34 signals description

Description

—

Charge pump control

0: Enabled; charge pump on in active mode (default)

1: Disabled; charge pump off in active mode setting CP_OFF = 1 is only possible when CP_OFF_EN = 1

V1 load current supervision

0: Enabled; Watchdog is disabled in V1 Standby when I v1

< I

CMP

(default)

1: Disabled; watchdog is disabled upon transition into V1_standby mode setting ICMP = 1 is only possible when ICMP_config_en = 1

Watchdog Enable

0: Watchdog disabled

1: Watchdog enabled (default)

7.4.16 Configuration Register (0x3F)

Table 105. Configuration Register

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name

Reset

Access

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

R/W

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Bit

SPI Registers

Name

WU_CONFIG

LIN_WU_CONFIG

LIN_HS_EN

TSD_CONFIG

Reserved

ICMP_CONFIG_EN

WD_CONFIG_EN

MASK_OL_HS1

MASK_OL_LS1

MASK_TW

Table 106. CR signals description

Description

Configuration of input pin WU

Input configured as wake-up input

0: WU configured as wake-up input

1: WU configured for input voltage measurement (default)

Configuration of LIN wake-up behaviour

0: wake up at recessive - dominant - recessive with t dom

> t dom_LIN

(default)

(according to LIN 2.2a and Hardware Requirements for Transceivers version

1.3)

1: wake up at recessive - dominant transition

Configuration of LIN transceiver bit rate

0: LIN transceiver in normal communication mode (20kbit/s) (default)

1: LIN transceiver in high speed mode for fast Flashing (115kbit/s)

Configuration of thermal shutdown behaviour

0: in case of TSD1 all power stages are switched off (default)

1: selective shut down of power stage cluster

—

H-bridge configuration

0: single motor mode (default)

1: reserved

ICMP configuration Enable

0: writing ICMP = 1 is blocked (writing ICMP=0 is possible); (default)

1: writing ICMP = 1 is possible with next SPI command bit is automatically reset to 0 after next SPI command

Watchdog configuration Enable

0: writing to WD Configuration (CR2 [0:1] is blocked (default)

1: writing to WD Configuration Bits is possible with next SPI command bit is automatically reset to 0 after next SPI command

Mask Open-load HS1

0: Open-load condition at HS1 is not masked (default)

1: Open-load condition at HS1 is masked i.e. it is reported as a Functional Error (GSB bit 3) but not as a Global Error

(GSB bit 7)

Mask Open-load LS1

0: Open-load condition at LS1 is not masked (default)

1: Open-load condition at LS1 is masked i.e. it is reported as a Functional Error (GSB bit 3) but not as a Global Error

(GSB bit 7)

Mask Thermal Warning

0: Thermal warning is not masked (default)

1: Thermal warning is masked i.e. it is reported as a Global Warning (GSB bit 1) but not as a Global Error

(GSB bit 7)

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SPI Registers

Bit

3:1

L99DZ120

Name

Reserved

MASK_OL

MASK_SPIE

MASK_PLE

MASK_GW

CP_OFF_EN

CP_DITH_DIS

FS_FORCED

Reserved

TRIG

Table 106. CR signals description (continued)

Description

CP_LOW_CONFIG

—

Mask open-load

0: Open-load condition at all outputs are not masked (default)

1: Open-load condition at all outputs are masked i.e. it is reported as a Functional Error (GSB bit 3) but not as a Global Error

(GSB bit 7)

Mask SPI error

0: SPI errors are not masked (default)

1: SPI errors are masked i.e. reported as am SPI Error (GSB bit 5) but not as a Global Error (GSB bit 7)

Mask physical layer error

0: Physical Layer Errors are not masked (default)

1: Physical Layer Errors are masked i.e. reported as a Physical Layer Error (GSB bit 4) but not as a Global Error

(GSB bit 7)

Mask global warning

0: Global Warning conditions are not masked (default)

1: Global Warning conditions are masked i.e. reported as a Global Warning (GSB bit 1) but not as a Global Error (GSB bit 7)

Charge pump control enable

0: writing CP_OFF = 1 is blocked (writing CP OFF = 0 is possible); (default)

1: writing CP_OFF = 1 is possible with next SPI command

Bit is automatically reset to 0 after next SPI command

Charge pump low configuration

0: CP_low (SR 2, bit 9) is latched and outputs are off until R&C; (default)

1: CP_low (SR 2, bit 9) is a ‘live’ bit; outputs are re-activated automatically upon recovery of the charge pump output voltage

Charge pump clock dithering

0: CP clock dithering is enabled; (default)

1: CP clock dithering is disabled

Force LSx_FSO ON

LSx_FSO low-side outputs are forced ON (to allow diagnosis of the fail-safe path)

0: LSx_FSO outputs are controlled by the Fail-safe logic (default)

1: LSx_FSO outputs are forced ON and the device enters Fail-Safe mode; no

NReset is generated

—

Watchdog Trigger bit

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7.5.1 Status Register SR1 (0x31)

Table 107. Status Register SR1 (0x31)

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name

Access R/C R

Bit

R/C R R/C

Name

Reserved

WU_STATE

Reserved

WU_WAKE

Reserved

WAKE_LIN

WAKE_TIMER

DEBUG_ACTIVE

Table 108. SR1 signals description

Description

—

State of WU input

0: input level is low

1: input level is high

The bit shows the momentary status of WU and cannot be cleared (“Live bit”)

Note: The status is only valid if WU is configured as wake-up input in

Configuration Register (0x3F). Otherwise this bit remains at his previous logic state.

—

Wake-up by WU: shows wake up source

1: wake-up

Bits are latched until a “Read and clear” command

—

Wake-up by LIN: shows wake up source

1: wake-up

Bits are latched until a “Read and clear” command

Wake-up by Timer: shows wake up source

1: wake-up

Bits are latched until a “Read and clear” command

Debug Mode Active: indicates Device is in Debug mode

1: Debug mode

The bit shows the momentary status and cannot be cleared (“Live bit”)

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160

SPI Registers

Bit

L99DZ120

Name

Table 108. SR1 signals description (continued)

Description

V1UV

V1_RESTART_2

V1_RESTART_1

V1_RESTART_0

WDFAIL_CNT_3

Indicates undervoltage condition at voltage regulator V1 (V1 < V

RTx

)

1: undervoltage

Bit is latched until a “Read and clear” command

Indicates the number of TSD2 events which caused a restart of voltage regulator V1

Bits cannot be cleared; counter will be cleared automatically if no additional

TSD2 event occurs within 1 minute.

WDFAIL_CNT_2

WDFAIL_CNT_1

Indicates number of subsequent watchdog failures.

Bits cannot be cleared; will be cleared with a valid watchdog trigger

WDFAIL CNT_0

DEVICE_STATE_1 State from which the device woke up

00: Active Mode after Read&Clear command or after Flash Mode state

DEVICE_STATE_0

01: Active mode after wake-up from V1_standby mode (before Read&Clear command)

10: Active Mode after Power-on or after wake-up from Vbat_standby Mode

(before Read&Clear command)

11: Flash mode (LIN Flash mode)

Bit is latched until a “Read and clear” command

After a “read and clear access”, the device state will be updated

TSD2

TSD1

FORCED_SLEEP_

TSD2/V1SC

Thermal Shutdown 2 was reached

Bit is latched until a "Read and clear" command

Thermal Shutdown 1 was reached (Logical Or combination of all TSD1_CLx; see status register SR6).

This bit cannot be cleared directly. It is reset if the corresponding TSD1_CLx bits in SR6 are cleared.

Device entered Forced Vbat_standby mode due to:

– Thermal shutdown or

– Short circuit on V1 during startup

Bit is latched until a "Read and clear" command

FORCED_SLEEP_WD

Device entered Forced Vbat_standby mode due to multiple watchdog failures

Bit is latched until a "Read and clear" command

WDFAIL

VPOR

Watchdog failure

Bit is latched until a "Read and clear" command

Power-on Reset threshold (VPOR) reached

Bit is latched until a "Read and clear" command

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7.5.2

SPI Registers

Status Register SR2 (0x32)

Table 109. Status Register SR2 (0x32)

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name Reserved

Access R/C R R/C

Bit

20:16

Name

LIN_PERM_DOM

LIN_TXD_DOM

LIN_PERM_REC

Table 110. SR2 signals description

Description

LIN bus signal is dominant for t > t dom(bus)

Bit is latched until a “Read and clear” command

TxDL pin is dominant for t > t dom(TXDL)

The LIN transmitter is disabled until the bit is cleared

Bit is latched until a “Read and clear” command

LIN bus signal does not follow TxDL within t

LIN

The LIN transmitter is disabled until the bit is cleared

Bit is latched until a “Read and clear” command

— Reserved

DSMON_HS2

DSMON_HS1

DSMON_LS2

DSMON_LS1

Drain-Source Monitoring

‘1’ indicates a short-circuit or open-load condition was detected

Bit is latched until a “Read and clear” command

SPI_INV_CMD

SPI_SCK_CNT

CP_LOW

Invalid SPI command

‘1’ indicates one of the following conditions was detected:

– access to undefined address

– Write operation to Status Register

– DI stuck at '0' or '1'

– CSN timeout

– Parity failure

– invalid or undefined setting

The SPI frame is ignored

Bit is latched until a “Read and clear” command

SPI clock counter

‘1’ indicates an SPI frame with wrong number of CLK cycles was detected

Bit is latched until a valid SPI frame

Charge pump voltage low

‘1’ indicates that the charge pump voltage is too low

Bit is latched until a “Read and clear” command

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SPI Registers

Bit

L99DZ120

Name

V2SC

V2FAIL

V1FAIL

VSREG_EW

VSREG_OV

VSREG_UV

VS_OV

VS_UV

Table 110. SR2 signals description (continued)

Description

Thermal warning

‘1’ indicates the temperature has reached the thermal warning threshold (logical

OR combination of bits TW_CLx in SR6)

Bit is latched until a “Read and clear” command

V2 short circuit detection

‘1’ indicates a short circuit to GND condition of V2 at turn-on of the regulator

(V2 < V2_fail for t > t v2_short

)

Bit is latched until a “Read and clear” command

V2 failure detection

‘1’ indicates a V2 fail event occurred since last readout

(V2 < V2_fail for t > t v2_fail

)

Bit is latched until a “Read and clear” command

V1 failure detection

‘1’ indicates a V1 fail event occurred since last readout

(V1 < V1_fail for t > t v1_fail

)

Bit is latched until a “Read and clear” command

SREG

early warning

‘1’ indicates the voltage at V

SREG

(configured in CR3)

has reached the early warning threshold

In Active mode, an interrupt pulse is generated at NINT

Bit is latched until a “Read and clear” command.

Bit needs a "Read and clear" command after wake-up from standby modes

SREG

overvoltage

‘1’ indicates the voltage at V

SREG

has reached the overvoltage threshold

Bit is latched until a “Read and clear” command

SREG

undervoltage

‘1’ indicates the voltage at V

SREG

has reached the undervoltage threshold

Bit is latched until a “Read and clear” command

overvoltage

‘1’ indicates the voltage at V

has reached the overvoltage threshold

Bit is latched until a “Read and clear” command

undervoltage

‘1’ indicates the voltage at V

has reached the undervoltage threshold

Bit is latched until a “Read and clear” command

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7.5.3

SPI Registers

Status Register SR3 (0x33)

Table 111. Status Register SR3 (0x33)

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name Reserved

Access R/C

Bit

21:18

Name

Table 112. SR3 signals description

Description

OUT1_HS_OC_TH_EX Overcurrent shutdown

‘1’ indicates the output was shut down due to overcurrent condition.

If Overcurrent Recovery is disabled (CR7: OUTx_OCR = 0):

Bit is set upon overcurrent condition and output is turned off.

If Overcurrent Recovery is enabled (CR7: OUTx_OCR = 1):

OUT1_LS_OC_TH_EX In case of overcurrent condition this bit is not set. The output goes into

Overcurrent Recovery mode and OUTx_OCR_alert in SR4 is set to '1'

In case of Thermal Expiration enabled (CR8: OUTx_OCR_THx_en = 1):

Bit is set after thermal expiration and output is turned off

Bit is latched until a “Read and clear” command

Reserved —

OUT4_HS_OC_TH_EX Overcurrent shutdown

OUT4_LS_OC_TH_EX ‘1’ indicates the output was shut down due to overcurrent condition.

OUT5_HS_OC_TH_EX

If Overcurrent Recovery is disabled (CR7: OUTx_OCR = 0):

Bit is set upon overcurrent condition and output is turned off.

OUT5_LS_OC_TH_EX

If Overcurrent Recovery is enabled (CR7: OUTx_OCR = 1):

OUT6_HS_OC_TH_EX In case of overcurrent condition this bit is not set. The output goes into

Overcurrent Recovery mode and OUTx_OCR_alert in SR4 is set to '1'

OUT6_LS_OC_TH_EX

OUT7_OC_TH_EX

OUT8_OC_TH_EX

In case of Thermal Expiration enabled (CR8: OUTx_OCR_THx_en = 1):

Bit is set after thermal expiration and output is turned off

Bit is latched until a “Read and clear” command

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SPI Registers

Bit

L99DZ120

Name

Table 112. SR3 signals description (continued)

Description

OUT9_OC

OUT10_OC

OUT11_OC

OUT12_OC

OUT13_OC

OUT14_OC

OUT15_OC

Overcurrent shutdown

‘1’ indicates the output was shut down due to overcurrent condition.

Bit is latched until a “Read and clear” command

OUTHS_OC_TH_EX

LS2FSO_OC

LS1FSO_OC

Overcurrent shutdown

‘1’ indicates the output was shut down due to overcurrent condition.

If Overcurrent Recovery is disabled (CR7: OUTx_OCR = 0):

Bit is set upon overcurrent condition and output is turned off.

If Overcurrent Recovery is enabled (CR7: OUTx_OCR = 1):

In case of overcurrent condition this bit is not set. The output goes into

Overcurrent Recovery mode and OUTx_OCR_alert in SR4 is set to '1'

In case of Thermal Expiration enabled (CR8: OUTx_OCR_THx_en = 1):

Bit is set after thermal expiration and output is turned off

Bit is latched until a “Read and clear” command

Overcurrent shutdown

‘1’ indicates the output was shut down due to overcurrent condition.

Bit is latched until a “Read and clear” command

7.5.4 Status Register SR4 (0x34)

Table 113. Status Register SR4 (0x34)

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved Bit name

Access R

Reserved

R/C R R/C

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L99DZ120 SPI Registers

Bit

21:18

9:3

1:0

Name

Table 114. SR4 signals description

Description

OUT1_HS_OCR_ALERT Autorecovery Alert

OUT1_LS_OCR_ALERT

‘1’ indicates that the output reached the overcurrent threshold and is in autorecovery mode

Bit is not latched and cannot be cleared.

Reserved

OUT4_HS_OCR_ALERT

—

OUT4_LS_OCR_ALERT

OUT5_HS_OCR_ALERT

OUT5_LS_OCR_ALERT

OUT6_HS_OCR_ALERT

Autorecovery Alert

‘1’ indicates that the output reached the overcurrent threshold and is in autorecovery mode

Bit is not latched and cannot be cleared.

OUT6_LS_OCR_ALERT

OUT7_OCR_ALERT

OUT8_OCR_ALERT

Reserved

OUTHS_OCR_ALERT

Reserved

—

Autorecovery Alert

‘1’ indicates that the output reached the overcurrent threshold and is in autorecovery mode

Bit is not latched and cannot be cleared.

—

7.5.5 Status Register SR5 (0x35)

Table 115. Status Register SR5 (0x35)

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name Reserved

Access

Bit

21:18

Name

OUT1_HS_OL

OUT1_LS_OL

Reserved

R/C

Table 116. SR5 signals description

Description

Open-load

‘1’ indicates an open-load condition was detected at the output

Bit is latched until a “Read and clear” command

—

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Bit

1:0

SPI Registers

Name

OUT4_HS_OL

OUT4_LS_OL

OUT5_HS_OL

OUT5_LS_OL

OUT6_HS_OL

OUT6_LS_OL

OUT7_OL

OUT8_OL

OUT9_OL

OUT10_OL

OUT11_OL

OUT12_OL

OUT13_OL

OUT14_OL

OUT15_OL

OUTHS_OL

Reserved

Table 116. SR5 signals description (continued)

Description

Open-load

‘1’ indicates an open-load condition was detected at the output

Bit is latched until a “Read and clear” command

—

L99DZ120

7.5.6 Status Register SR6 (0x36)

Table 117. Status Register SR6 (0x36)

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name Reserved

Access R R/C

Bit

Table 118. SR6 signals description

Name

WD_TIMER_STATE_1 Watchdog timer status

00: 0 - 33%

WD_TIMER_STATE_0 01: 33 - 66%

11: 66 - 100%

Description

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Bit

7:6

21:14

L99DZ120 SPI Registers

Name

Reserved

TW_CL6

TW_CL5

TW_CL4

TW_CL3

TW_CL2

TW_CL1

Reserved

TSD1_CL6

TSD1_CL5

TSD1_CL4

TSD1_CL3

TSD1_CL2

TSD1_CL1

Table 118. SR6 signals description (continued)

Description

—

Thermal warning for Cluster x

‘1’ indicates Cluster x has reached the thermal warning threshold

Bit is latched until a “Read and clear” command

—

Thermal shutdown of Cluster x

‘1’ indicates Cluster x has reached the thermal shutdown threshold (TSD1) and the output cluster was shut down

Bit is latched until a “Read and clear” command

Table 119. Status Register SR7 (0x37) to SR9 (0x39)

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name

Access

Bit

23:22

R/C R R/C

Where: x = 2 + (z * 2), z = 0 to 2 y = 1 + (z * 2), z = 0 to 2

Name

Reserved

Table 120. SR7 to SR9 signals description

Description

—

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Bit

11:10

SPI Registers L99DZ120

Name

Table 120. SR7 to SR9 signals description (continued)

Description

TEMP_CLx_9

TEMP_CLx_8

TEMP_CLx_7

TEMP_CLx_6

TEMP_CLx_5

TEMP_CLx_4

TEMP_CLx_3

TEMP_CLx_2

TEMP_CLx_1

TEMP_CLx_0

Reserved

TEMP_CLy_9

TEMP_CLy_8

TEMP_CLy_7

TEMP_CLy_6

TEMP_CLy_5

TEMP_CLy_4

TEMP_CLy_3

TEMP_CLy_2

TEMP_CLy_1

TEMP_CLy_0

Temperature Cluster x: Binary coded voltage of temperature diode for cluster x

(bit12 = LSB; bit21 = MSB) (see

Section 4.31: Thermal clusters )

Bits cannot be cleared.

—

Temperature Cluster y: binary coded voltage of temperature diode for cluster y

(bit0 = LSB; bit9 = MSB) (see

Section 4.31: Thermal clusters )

Bits cannot be cleared.

7.5.8 Status Register SR10 (0x3A)

Table 121. Status Register SR10 (0x3A)

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name

Access R/C R

Bit

23:22

Name

Reserved —

Table 122. SR10 signals description

Description

Reserved

R/C

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DS11567 Rev 5

L99DZ120 SPI Registers

Bit

11:0

Name

Table 122. SR10 signals description (continued)

Description

VSREG_9

VSREG_8

VSREG_7

VSREG_6

VSREG_5

VSREG_4

VSREG_3

VSREG_2

VSREG_1

VSREG_0

Reserved —

Binary coded voltage at V

SREG

pin (bit12 = LSB; bit21 = MSB)

00 0000 0000: 0V xx xxxx xxxx: V

AINVS

/1023 x register value

11 1111 1111: V

AINVS

Bits cannot be cleared.

7.5.9 Status Register SR11 (0x3B)

Table 123. Status Register SR11 (0x3B)

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit name

Access R/C R R/C R

Bit

23:22

11:10

Name

Table 124. SR11 signals description

Description

Reserved —

VS_9

VS_8

VS_7

VS_6

VS_5

VS_4

VS_3

VS_2

Binary coded voltage at V

00 0000 0000: 0V

pin (bit12 = LSB; bit21 = MSB) xx xxxx xxxx: V

AINVS

/1023 x register value

11 1111 1111: V

AINVS

Bits cannot be cleared.

VS_1

VS_0

Reserved —

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Bit

SPI Registers

Name

VWU_9

VWU_8

VWU_7

VWU_6

VWU_5

VWU_4

VWU_3

VWU_2

VWU_1

VWU_0

Table 124. SR11 signals description (continued)

Description

Binary coded voltage at WU pin (bit0 = LSB; bit9 = MSB)

00 0000 0000: 0V xx xxxx xxxx: V

AINVS

/1023 x register value

11 1111 1111: V

AINVS

Bits cannot be cleared.

L99DZ120

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L99DZ120 Package information

8.1

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com

ECOPACK ® is an ST trademark.

LQFP-64 package information

Figure 57. LQFP-64 package dimension

Symbol

Θ 1

Θ 2

Θ 3

("1($'5

Table 125. LQFP-64 mechanical data

Millimeters

Min.

0º

11º

Typ. Max.

3.5°

9°

12°

6°

12°

13°

DS11567 Rev 5

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Package information L99DZ120

Table 125. LQFP-64 mechanical data (continued)

Millimeters

Symbol

Min.

Typ. Max.

A 1.60

A2 1.35 1.40 1.45 b b1 0.17

0.20

0.27

0.23

c1 0.09

0.127

0.16

6.85

D3 e

E2 aaa bbb ccc ddd

5.7

0.50 BSC

12.00 BSC

10.00 BSC

3.3

0.45

0.60

1.00

0.08

0.20

Tolerance of form and position

0.20

0.08

4.79

0.75

0.20

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Figure 58. LQFP-64 footprint

Package information

("1($'5

8.2 LQFP-64 marking information

Figure 59. LQFP-64 marking information

.BSLJOHBSFB

4QFDJBMGVODUJPOEJHJUT

&4&OHJOFFSJOHTBNQMF

CMBOL$PNNFSDJBMTBNQMF

-2'15017*&8

OPUJOTDBMF

("%(."(

Parts marked as ES are not yet qualified and therefore not approved for use in production.

ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted to run a qualification activity prior to any decision to use these engineering samples.

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Revision history L99DZ120

Date

27-Apr-2016

11-May-2016

12-Sep-2016

22-Nov-2016

11-Mar-2019

Table 126. Document revision history

Revision Changes

Initial release.

Updated Section 3.3.1: LQFP64 thermal data

Updated Section 4.14: Auto-recovery alert and thermal expiration

Updated Section 4.22: Programmable soft-start function to drive loads with higher inrush current

Updated Figure 43

Updated Table 114

Updated Table 29

Added AEC-Q100 qualified in Features .

Updated Table 4: ESD protection

Added Section 3.4.12: Over Current Recovery settings

Updated Section 4.22: Programmable soft-start function to drive loads with higher inrush current

Added

Table 18: Half bridges (OUT1, OUT4, OUT5 and

OUT6) OCR timing parameters and Table 19: High-side

(OUT7, OUT8 and OUT_HS) OCR timing parameters

Updated Table 20: Current monitoring

Updated Table 110: SR2 signals description

Updated Table 124: SR11 signals description

Moved “Device summary” table in cover page.

Added the "Sustainable Technology" logo to the datasheet in cover page.

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L99DZ120

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on

ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

DS11567 Rev 5 161/161

161

Features

Automotive door actuator driver with embedded LIN

Applications

Contents

List of tables

List of figures

1 Description

2

Block diagram and pin descriptions

3.1

Absolute maximum ratings

L99DZ120 thermal profiles

,*+[U DFFXUDF\

'DWDLQSXW

,*+[I DFFXUDF\

'DWDLQSXW

, V

SREG

4.4

Wake-up from Standby modes

4.6

Configurable window watchdog

4.8 Reset output (NReset)

4.9

LIN Bus Interface

Dominant TxDL time out

Permanent recessive

Permanent dominant

Pattern Wake-up (default)

Status change wake-up - Recessive-to-dominant

Status change wake-up - Dominant-to-recessive

4.10 Serial Peripheral Interface (ST SPI Standard)

V

overvoltage

V

undervoltage

V

overvoltage

V

undervoltage

4.14 Auto-recovery alert and thermal expiration

4.20 PWM mode of the power outputs

4.22 Programmable soft-start function to drive loads with higher inrush current

4.26 Short circuit detection / drain source monitoring

4.32 V

S

compensation (duty cycle adjustment) module

4.33 Analog digital converter

5 Serial Peripheral Interface (SPI)

&

63,0DVWHU

/'=

SDI Frame

Operating code

Advanced operation codes

Data-in payload

SDO frame

Global Status Byte (GSB)

Data-Out Payload

Information registers

Device Application Registers (RAM)

Clock monitor

SCK Polarity (CPOL) check

SCK Phase (CPHA) check

CSN timeout

SDI stuck at GND

SDI stuck at HIGH

SDO stuck @

6 Application

7.1 Global Status Byte GSB

7.2 Control register overview

7.3 Status register overview

8.1

LQFP-64 package information

8.2 LQFP-64 marking information

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AEK-POW-SPSB081 User Manual - Automotive Power Management IC Evaluation Board

STMicroelectronics L99MM70XP Datasheet

&