TFBGA216 package. STMicroelectronics STM32F479ZI, STM32F479VI, STM32F479BI, STM32F479II, STM32F479VG, STM32F479NG, STM32F479ZG, STM32F479AG, STM32F479NI, STM32F479AI

STM32F479xx Description

A

1

PE4

Figure 4. TFBGA216 port-to-terminal assignment differences

2

PE3

3 4 5

PE2 PG14 PE1

6

PE0

7

PB8

8

PB5

9

PB4

10

PB3

11 12 13 14 15

PD7 PC12 PA15 PA14 PA13

B

PE5 PE6 PG13 PB9 PB7 PB6 PG15 PG11 PJ13 PJ12 PD6 PD0 PC11 PC10 PA12

C VBAT PI8 PI4 PK7 PK6 PK5 PG12 PG10 PJ14 PD5 PD3 PD1 PI3 PI2 PA11

D PC13 PF0 PI5 PI7 PI10 PI6 PK4 PK3 PG9 PJ15 PD4 PD2 PH15 PI1 PA10

E

PC14 PF1 PI12 PI9

PDR

ON

BOOT0 VDD VDD VDD VDD VCAP2 PH13 PH14 PI0 PA9

F PC15 VSS PI11 VDD VDD VSS VSS VSS VSS VSS VDD PC9 PA8

G PH0 PF2 PI13 PI15 VDD VSS

H PH1 PF3 PI14

PH4

VDD VSS

J NRST PF4 PH5 PH3 VDD VSS

VSS

VSS

VSS VDD

PC8 PC7

PG8 PC6

PG7 PG6

K PF7 PF6 PF5 PH2 VDD VSS VSS VSS VSS VSS VDD PD15

PB13

PD10

L

PF10 PF9 PF8 PC3

BYPASS

-REG

VSS VDD VDD VDD VDD VCAP1 PD14 PB12 PD9 PD8

M

VSSA PC0 PC1 PC2 PB2 PF12 PG1 PF15 PJ4 PD12 PD13 PG3 PG2 PJ5 PH12

N

VREFPA1 PA0 PA4 PC4 PF13 PG0 PJ3 PE8 PD11 PG5 PG4 PH7 PH9 PH11

P VREF+ PA2 PA6 PA5 PC5 PF14 PJ2 PF11 PE9 PE11 PE14 PB10 PH6 PH8 PH10

R VDDA PA3 PA7 PB1 PB0 PJ0 PJ1 PE7 PE10 PE12 PE15 PE13 PB11 PB14 PB15

STM32F42xx/3xx

STM32F40xx/41xx

VDD PK1 PL2

VDD PJ11 PK0

VDD PJ8 PJ10

VDD PJ7 PJ9

VDD PJ6 PD15

STM32F469xx

STM32F479xx

VDD

DSI

HOST_

D1P

DSI

HOST_

D1N

VDDD

USB

VDD

DSI

VDD

VSS

DSI

VDD12

DSI

DSI

HOST_

CKP

DSI

HOST_

CKN

DSI

HOST_

D0P

DSI

HOST_

D0N

VDD

VCAP

DSI

PD15

1. The highlighted pins are substituted with dedicated DSI IO pins on STM32F469xx/479xx devices.

MSv39404V1

DS11118 Rev 7 19/220

47

Description STM32F479xx

Figure 5. STM32F479xx block diagram

JTRST, JTDI,

JTCK/SWCLK

JTDO/SWD, JTDO

TRACECK

TRACED(3:0)

CCM data RAM 64 KB

JTAG & SW

ETM

MPUFPU

NVIC

ARM

Cortex M4

180 MHz

D-BUS

I-BUS

S-BUS

EXT MEM CTRL (FMC)

SRAM, PSRAM, NOR Flash

NAND Flash, SDRAM

QuadSPI

CLK, NE[3:0], A[23:0], D[31:0],

NOE, NWEN, NBL[3:0],

SDCLKE[1:0], SDNE[1:0],

NRAS, NCAS, NADV,

NWAIT, INTR

CLK,

BK1_NCS, BK2_NCS,

D[7:0]

Flash 1MB

Flash 1MB

3DES,

AES256

D+, D-

VDDUSB = 3.0 to 3.6 V

ULPI : CLK, D(7:0),

DIR, STP, NXT

SCL/SDA, INT, ID, VBUS

USB

OTG HS

DMA/

FIFO

GP-DMA2

GP-DMA1

8 Streams

FIFO

8 Streams

FIFO

SRAM1 160KB

SRAM2 32KB

SRAM3 128KB

HASH

RNG

CAMERA

ITF

USB

OTG FS

HSYNC, VSYNC

PIXCK, D(13:0)

D+, D-,

VDDUSB = 3.0 to 3.6 V,

SCL, SDA, INT, ID, VBUS

LCD-TFT FIFO

AHB2 180 MHz

AHB1 180 MHz

DMA-2D FIFO

PA[15:0]

PB[15:0]

PC[15:0]

PD[15:0]

PE[15:0]

PF[15:0]

PG[15:0]

RESET&

@VDDA

RC HS

RC LS

PLL1,2,3

POR

Reset

Int

SUPPLY

SUPERVISION

POR/PDR/

BOR

PVD

@VDDA @VDD

XTAL OSC

4-26MHz

IWDG

Standbyinterface

@VBAT

VDDA, VSSA,

NRST

OSCIN

OSCOUT

VBAT = 1.8 to 3.6 V

PH[15:0]

PI[15:0]

PJ[15:0]

CRC

XTAL 32kHz

RTC

AWU

Backup Register

4KB BKPRAM

TIM2

TIM3

TIM4

TIM5

TIM12

TIM13

OSC32_IN

OSC32_OUT

RTC_TAMP1

RTC_TAMP2

RTC_OUT

RTC_REFIN

RTC_TS

4 Channels, ETR as AF

PK[7:0]

DSIHOST_D0 P/N

DSIHOST_D1 P/N

DSIHOST_CK P/N

VDD12DSI, VDDSI, VSSDSI

VCAPDSI

DSIHOST_TE

168 AF

D[7:0]

CMD, CK as AF

4 compl. chan. (TIM1_CH1[1:4]N),

4 chan. (TIM8_CH1[1:4]ETR),

BKIN as AF

4 compl. chan. (TIM1_CH1[1:4]N),

4 chan. (TIM8_CH1[1:4]ETR),

BKIN as AF

DSI Host

SDIO / MMC

16b

16b

DMA2

AHB/APB2 AHB/APB1

DMA1

32b

16b

16b

32b

16b

16b

4 Channels, ETR as AF

4 Channels, ETR as AF

4 Channels

2 Channels as AF

1 Channels as AF

2 channels as AF

1 channel as AF

1 channel as AF

RX, TX, SCK,

CTS, RTS as AF

RX, TX, SCK,

CTS, RTS as AF

MOSI, MISO, SCK,

NSS as AF

MOSI, MISO, SCK,

NSS as AF

USART 2MBps

16b

16b smcard irDA smcard irDA

USART 2MBps

16b

WWDG

16b

TIM14 16b

USART2 smcard irDA

USART3 smcard irDA

UART4

UART5

UART7

UART8

SPI2/I2S

1 CH as AF

RX, TX, SCK,

CTS, RTS as AF

RX, TX, SCK

CTS, RTS as AF

RX, TX as AF

RX, TX as AF

RX, TX as AF

RX, TX as AF

MOSI, MISO, SCK

NSS/WS, MCK as AF TIMER6

MOSI, MISO, SCK,

NSS as AF

MOSI, MISO, SCK,

NSS as AF

SD, SCK, FS

MCLK as AF

TIMER7

16b

SPI3/I2S

I2C1/SMBUS

MOSI, MISO, SCK

NSS/WS, MCK as AF

SCL, SDA, SMBA as AF

@VDDA

SCL, SDA, SMBA as AF

@VDDA

DAC1

DAC2

I2C2/SMBUS

I2C3/SMBUS

SCL, SDA, SMBA as AF

V

DDREF_ADC

8 analog inputs common to the 3 ADCs

8 analog inputs common to the ADC1 & 2

ADC1

ADC2

ADC 3

ITF bxCAN1 bxCAN2

TX, RX

TX, RX

8 analog inputs to ADC3

DAC1 as AF DAC2 as AF

MS38297V1

1. The timers connected to APB2 are clocked from TIMxCLK up to 180 MHz, while the timers connected to

APB1 are clocked from TIMxCLK either up to 90 MHz or 180 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register.

20/220 DS11118 Rev 7