Power supply supervisor. STMicroelectronics STM32F479ZI, STM32F479VI, STM32F479BI, STM32F479II, STM32F479VG, STM32F479NG, STM32F479ZG, STM32F479AG, STM32F479NI, STM32F479AI
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![Power supply supervisor. STMicroelectronics STM32F479ZI, STM32F479VI, STM32F479BI, STM32F479II, STM32F479VG, STM32F479NG, STM32F479ZG, STM32F479AG, STM32F479NI, STM32F479AI | Manualzz Power supply supervisor. STMicroelectronics STM32F479ZI, STM32F479VI, STM32F479BI, STM32F479II, STM32F479VG, STM32F479NG, STM32F479ZG, STM32F479AG, STM32F479NI, STM32F479AI | Manualzz](http://s3.manualzz.com/store/data/064361677_1-61be67e92612d464df0f93f64d4af9f2-360x466.png)
Functional overview STM32F479xx
– VCAPDSI pin must be connected externally to VDD12DSI but the external capacitor is no more needed.
– VSSDSI pin must be grounded.
30/220
On packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On other packages the power supply supervisor is always enabled.
The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is reached, the option byte loading process starts, either to confirm or modify default BOR thresholds, or to disable BOR permanently. Three BOR thresholds are available through option bytes. The device remains in reset mode when V
DD
V
POR/PDR
or V
BOR
is below a specified threshold,
, without the need for an external reset circuit.
The device also features an embedded programmable voltage detector (PVD) that monitors the V
DD
/V
DDA
power supply and compares it to the V
PVD generated when V
DD
/V
DDA higher than the V
PVD
drops below the V
PVD
threshold. An interrupt can be
threshold and/or when V
DD
/V
DDA message and/or put the MCU into a safe state. The PVD is enabled by software.
is
threshold. The interrupt service routine can then generate a warning
This feature is available only on packages featuring the PDR_ON pin. The internal power-on reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin.
An external power supply supervisor should monitor V
DD the device in reset mode as long as V
DD connected to VSS, as shown in
and NRST and should maintain
is below a specified threshold. PDR_ON must be
Figure 8. Power supply supervisor interconnection with internal reset OFF
VDD
STM32F479xx
VBAT
PDR_ON
Application reset signal (optional)
VSS
PDR not active : 1.7 V < VDD < 3.6 V
MSv36589V1
DS11118 Rev 7
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Table of contents
- 12 Description
- 15 Compatibility throughout the family
- 16 LQFP176 package
- 17 LQFP208 package
- 18 UFBGA176 package
- 19 TFBGA216 package
- 21 Functional overview
- 21 -M4 with FPU and embedded Flash and SRAM
- 21 Adaptive real-time memory accelerator (ART Acceleratorâ„¢)
- 21 Memory protection unit
- 22 Embedded Flash memory
- 22 CRC (cyclic redundancy check) calculation unit
- 22 Embedded SRAM
- 22 Multi-AHB bus matrix
- 23 DMA controller (DMA)
- 24 Flexible memory controller (FMC)
- 25 Quad-SPI memory interface (QUADSPI)
- 25 LCD-TFT controller
- 25 DSI Host (DSIHOST)
- 27 Chrom-ART Acceleratorâ„¢ (DMA2D)
- 27 Nested vectored interrupt controller (NVIC)
- 27 External interrupt/event controller (EXTI)
- 28 Clocks and startup
- 28 Boot modes
- 28 Power supply schemes
- 30 Power supply supervisor
- 30 Internal reset ON
- 30 Internal reset OFF
- 31 Voltage regulator
- 32 Regulator ON
- 33 Regulator OFF
- 35 Regulator ON/OFF and internal reset ON/OFF availability
- 35 Real-time clock (RTC), backup SRAM and backup registers
- 36 Low-power modes
- 37 operation
- 37 Timers and watchdogs
- 38 Advanced-control timers (TIM1, TIM8)
- 39 General-purpose timers (TIMx)
- 39 Basic timers TIM6 and TIM
- 39 Independent watchdog
- 39 Window watchdog
- 40 SysTick timer
- 40 Universal synchronous/asynchronous receiver transmitters (USART)
- 41 Serial peripheral interface (SPI)
- 42 Serial Audio interface (SAI1)
- 42 Audio PLL (PLLI2S)
- 42 Audio and LCD PLL(PLLSAI)
- 42 Secure digital input/output interface (SDIO)
- 43 Ethernet MAC interface with dedicated DMA and IEEE 1588 support
- 43 Controller area network (bxCAN)
- 44 Universal serial bus on-the-go full-speed (OTG_FS)
- 44 Universal serial bus on-the-go high-speed (OTG_HS)
- 45 Digital camera interface (DCMI)
- 45 Cryptographic accelerator
- 45 Random number generator (RNG)
- 45 General-purpose input/outputs (GPIOs)
- 46 Analog-to-digital converters (ADCs)
- 46 Temperature sensor
- 46 Digital-to-analog converter (DAC)
- 47 Serial wire JTAG debug port (SWJ-DP)
- 47 Embedded Trace Macrocell
- 48 Pinouts and pin description
- 84 Memory mapping
- 89 Electrical characteristics
- 89 Parameter conditions
- 89 Minimum and maximum values
- 89 Typical values
- 89 Typical curves
- 89 Loading capacitor
- 89 Pin input voltage
- 90 Power supply scheme
- 91 Current consumption measurement
- 91 Absolute maximum ratings
- 93 Operating conditions
- 93 General operating conditions
- 95 VCAP1/VCAP2 external capacitor
- 96 Operating conditions at power-up / power-down (regulator ON)
- 96 Operating conditions at power-up / power-down (regulator OFF)
- 96 Reset and power control block characteristics
- 98 Over-drive switching characteristics
- 98 Supply current characteristics
- 114 Wakeup time from low-power modes
- 115 External clock source characteristics
- 119 Internal clock source characteristics
- 120 PLL characteristics
- 123 PLL spread spectrum clock generation (SSCG) characteristics
- 124 MIPI D-PHY characteristics
- 127 MIPI D-PHY PLL characteristics
- 128 MIPI D-PHY regulator characteristics
- 129 Memory characteristics
- 131 EMC characteristics
- 132 Absolute maximum ratings (electrical sensitivity)
- 133 I/O current injection characteristics
- 134 I/O port characteristics
- 140 NRST pin characteristics
- 141 TIM timer characteristics
- 141 Communications interfaces
- 156 12-bit ADC characteristics
- 162 Temperature sensor characteristics
- 162 monitoring characteristics
- 162 Reference voltage
- 163 DAC electrical characteristics
- 165 FMC characteristics
- 185 Quad-SPI interface characteristics
- 186 Camera interface (DCMI) timing specifications
- 187 LCD-TFT controller (LTDC) characteristics
- 189 SD/SDIO MMC card host interface (SDIO) characteristics
- 191 RTC characteristics
- 192 Package information
- 192 LQFP100 package information
- 195 LQFP144 package information
- 198 WLCSP168 package information
- 200 UFBGA169 package information
- 203 LQFP176 package information
- 207 UFBGA(176+25) package information
- 208 LQFP208 package information
- 212 TFBGA216 package information
- 215 Thermal characteristics
- 216 Part numbering
- 217 Appendix A Recommendations when using internal reset OFF
- 217 Operating conditions
- 218 Revision history