Power supply supervisor. STMicroelectronics STM32F479ZI, STM32F479VI, STM32F479BI, STM32F479II, STM32F479VG, STM32F479NG, STM32F479ZG, STM32F479AG, STM32F479NI, STM32F479AI

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Power supply supervisor. STMicroelectronics STM32F479ZI, STM32F479VI, STM32F479BI, STM32F479II, STM32F479VG, STM32F479NG, STM32F479ZG, STM32F479AG, STM32F479NI, STM32F479AI | Manualzz

Functional overview STM32F479xx

– VCAPDSI pin must be connected externally to VDD12DSI but the external capacitor is no more needed.

– VSSDSI pin must be grounded.

30/220

On packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On other packages the power supply supervisor is always enabled.

The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is reached, the option byte loading process starts, either to confirm or modify default BOR thresholds, or to disable BOR permanently. Three BOR thresholds are available through option bytes. The device remains in reset mode when V

DD

V

POR/PDR

or V

BOR

is below a specified threshold,

, without the need for an external reset circuit.

The device also features an embedded programmable voltage detector (PVD) that monitors the V

DD

/V

DDA

power supply and compares it to the V

PVD generated when V

DD

/V

DDA higher than the V

PVD

drops below the V

PVD

threshold. An interrupt can be

threshold and/or when V

DD

/V

DDA message and/or put the MCU into a safe state. The PVD is enabled by software.

is

threshold. The interrupt service routine can then generate a warning

This feature is available only on packages featuring the PDR_ON pin. The internal power-on reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin.

An external power supply supervisor should monitor V

DD the device in reset mode as long as V

DD connected to VSS, as shown in

Figure 8 .

and NRST and should maintain

is below a specified threshold. PDR_ON must be

Figure 8. Power supply supervisor interconnection with internal reset OFF

VDD

STM32F479xx

VBAT

PDR_ON

Application reset signal (optional)

VSS

PDR not active : 1.7 V < VDD < 3.6 V

MSv36589V1

DS11118 Rev 7

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