DMA controller (DMA). STMicroelectronics STM32F479ZI, STM32F479VI, STM32F479BI, STM32F479II, STM32F479VG, STM32F479NG, STM32F479ZG, STM32F479AG, STM32F479NI, STM32F479AI

STM32F479xx

64-Kbyte

CCM data RAM

ARM

Cortex-M4

Functional overview

Figure 6. STM32F479xx Multi-AHB matrix

GP

DMA1

GP

DMA2

MAC

Ethernet

USB OTG

HS

LCD-TFT

Chrom ART

Accelerator(DMA2D)

Bus matrix-S

ICODE

DCODE

Flash memory

SRAM1

160 Kbyte

SRAM2

32 Kbyte

SRAM3

128 Kbyte

AHB2 peripherals

AHB1 peripherals

FMC external

MemCtl

QuadSPI

APB1

APB2

MS33862V1

The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth

(AHB/APB).

The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code.

Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. Configuration is made by software and transfer sizes between source and destination are independent.

DS11118 Rev 7 23/220

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