Quad-SPI memory interface (QUADSPI). STMicroelectronics STM32F479ZI, STM32F479VI, STM32F479BI, STM32F479II, STM32F479VG, STM32F479NG, STM32F479ZG, STM32F479AG, STM32F479NI, STM32F479AI
Add to My manuals220 Pages
advertisement
![Quad-SPI memory interface (QUADSPI). STMicroelectronics STM32F479ZI, STM32F479VI, STM32F479BI, STM32F479II, STM32F479VG, STM32F479NG, STM32F479ZG, STM32F479AG, STM32F479NI, STM32F479AI | Manualzz Quad-SPI memory interface (QUADSPI). STMicroelectronics STM32F479ZI, STM32F479VI, STM32F479BI, STM32F479II, STM32F479VG, STM32F479NG, STM32F479ZG, STM32F479AG, STM32F479NI, STM32F479AI | Manualzz](http://s3.manualzz.com/store/data/064361677_1-61be67e92612d464df0f93f64d4af9f2-360x466.png)
STM32F479xx Functional overview
All STM32F479xx devices embed a Quad-SPI memory interface, which is a specialized communication interface targeting Single, Dual, Quad or Dual-flash SPI memories. It can work in direct mode through registers, external flash status register polling mode and memory mapped mode. Up to 256 Mbytes external Flash memory are mapped, supporting
8, 16 and 32-bit access. Code execution is supported.
The opcode and the frame format are fully programmable. Communication can be either in
Single Data Rate or Dual Data Rate.
The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue) and delivers all signals to interface directly to a broad range of LCD and TFT panels up to
XGA (1024x768) resolution with the following features:
2 displays layers with dedicated FIFO (64x32-bit)
Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer
Up to 8 Input color formats selectable per layer
Flexible blending between two layers using alpha value (per pixel or constant)
Flexible programmable parameters for each layer
Color keying (transparency color)
Up to 4 programmable interrupt events.
2.12 DSI Host (DSIHOST)
The DSI Host is a dedicated peripheral for interfacing with MIPI
DSI compliant displays. It includes a dedicated video interface internally connected to the LTDC and a generic APB interface that can be used to transmit information to the display.
These interfaces are as follows:
LTDC interface:
– Used to transmit information in Video Mode, in which the transfers from the host processor to the peripheral take the form of a real-time pixel stream (DPI).
– Through a customized for mode, this interface can be used to transmit information in full bandwidth in the Adapted Command Mode (DBI).
APB slave interface:
– Allows the transmission of generic information in Command mode, and follows a proprietary register interface.
– Can operate concurrently with either LTDC interface in either Video Mode or
Adapted Command Mode.
Video mode pattern generator:
– Allows the transmission of horizontal/vertical color bar and D-PHY BER testing pattern without any kind of stimuli.
DS11118 Rev 7 25/220
47
Functional overview STM32F479xx
The DSI Host main features:
Compliant with MIPI
Alliance standards
Interface with MIPI
D-PHY
Supports all commands defined in the MIPI
Alliance specification for DCS:
– Transmission of all Command mode packets through the APB interface
– Transmission of commands in low-power and high-speed during Video Mode
Supports up to two D-PHY data lanes
Bidirectional communication and escape mode support through data lane 0
Supports non-continuous clock in D-PHY clock lane for additional power saving
Supports Ultra Low-Power mode with PLL disabled
ECC and Checksum capabilities
Support for End of Transmission Packet (EoTp)
Fault recovery schemes
3D transmission support
Configurable selection of system interfaces:
– AMBA APB for control and optional support for Generic and DCS commands
– Video Mode interface through LTDC
– Adapted Command Mode interface through LTDC
Independently programmable Virtual Channel ID in
– Video Mode
– Adapted Command Mode
– APB Slave
Video Mode interfaces features
LTDC interface color coding mappings into 24-bit interface:
– 16-bit RGB, configurations 1, 2, and 3
– 18-bit RGB, configurations 1 and 2
– 24-bit RGB
Programmable polarity of all LTDC interface signals
Maximum resolution is limited by available DSI physical link bandwidth:
– Number of lanes: 2
– Maximum speed per lane: 500 Mbps
Adapted interface features
Support for sending large amounts of data through the memory_write_start (WMS) and memory_write_continue (WMC) DCS commands
LTDC interface color coding mappings into 24-bit interface:
– 16-bit RGB, configurations 1, 2, and 3
– 18-bit RGB, configurations 1 and 2
– 24-bit RGB
26/220 DS11118 Rev 7
advertisement
Related manuals
advertisement
Table of contents
- 12 Description
- 15 Compatibility throughout the family
- 16 LQFP176 package
- 17 LQFP208 package
- 18 UFBGA176 package
- 19 TFBGA216 package
- 21 Functional overview
- 21 -M4 with FPU and embedded Flash and SRAM
- 21 Adaptive real-time memory accelerator (ART Accelerator™)
- 21 Memory protection unit
- 22 Embedded Flash memory
- 22 CRC (cyclic redundancy check) calculation unit
- 22 Embedded SRAM
- 22 Multi-AHB bus matrix
- 23 DMA controller (DMA)
- 24 Flexible memory controller (FMC)
- 25 Quad-SPI memory interface (QUADSPI)
- 25 LCD-TFT controller
- 25 DSI Host (DSIHOST)
- 27 Chrom-ART Accelerator™ (DMA2D)
- 27 Nested vectored interrupt controller (NVIC)
- 27 External interrupt/event controller (EXTI)
- 28 Clocks and startup
- 28 Boot modes
- 28 Power supply schemes
- 30 Power supply supervisor
- 30 Internal reset ON
- 30 Internal reset OFF
- 31 Voltage regulator
- 32 Regulator ON
- 33 Regulator OFF
- 35 Regulator ON/OFF and internal reset ON/OFF availability
- 35 Real-time clock (RTC), backup SRAM and backup registers
- 36 Low-power modes
- 37 operation
- 37 Timers and watchdogs
- 38 Advanced-control timers (TIM1, TIM8)
- 39 General-purpose timers (TIMx)
- 39 Basic timers TIM6 and TIM
- 39 Independent watchdog
- 39 Window watchdog
- 40 SysTick timer
- 40 Universal synchronous/asynchronous receiver transmitters (USART)
- 41 Serial peripheral interface (SPI)
- 42 Serial Audio interface (SAI1)
- 42 Audio PLL (PLLI2S)
- 42 Audio and LCD PLL(PLLSAI)
- 42 Secure digital input/output interface (SDIO)
- 43 Ethernet MAC interface with dedicated DMA and IEEE 1588 support
- 43 Controller area network (bxCAN)
- 44 Universal serial bus on-the-go full-speed (OTG_FS)
- 44 Universal serial bus on-the-go high-speed (OTG_HS)
- 45 Digital camera interface (DCMI)
- 45 Cryptographic accelerator
- 45 Random number generator (RNG)
- 45 General-purpose input/outputs (GPIOs)
- 46 Analog-to-digital converters (ADCs)
- 46 Temperature sensor
- 46 Digital-to-analog converter (DAC)
- 47 Serial wire JTAG debug port (SWJ-DP)
- 47 Embedded Trace Macrocell
- 48 Pinouts and pin description
- 84 Memory mapping
- 89 Electrical characteristics
- 89 Parameter conditions
- 89 Minimum and maximum values
- 89 Typical values
- 89 Typical curves
- 89 Loading capacitor
- 89 Pin input voltage
- 90 Power supply scheme
- 91 Current consumption measurement
- 91 Absolute maximum ratings
- 93 Operating conditions
- 93 General operating conditions
- 95 VCAP1/VCAP2 external capacitor
- 96 Operating conditions at power-up / power-down (regulator ON)
- 96 Operating conditions at power-up / power-down (regulator OFF)
- 96 Reset and power control block characteristics
- 98 Over-drive switching characteristics
- 98 Supply current characteristics
- 114 Wakeup time from low-power modes
- 115 External clock source characteristics
- 119 Internal clock source characteristics
- 120 PLL characteristics
- 123 PLL spread spectrum clock generation (SSCG) characteristics
- 124 MIPI D-PHY characteristics
- 127 MIPI D-PHY PLL characteristics
- 128 MIPI D-PHY regulator characteristics
- 129 Memory characteristics
- 131 EMC characteristics
- 132 Absolute maximum ratings (electrical sensitivity)
- 133 I/O current injection characteristics
- 134 I/O port characteristics
- 140 NRST pin characteristics
- 141 TIM timer characteristics
- 141 Communications interfaces
- 156 12-bit ADC characteristics
- 162 Temperature sensor characteristics
- 162 monitoring characteristics
- 162 Reference voltage
- 163 DAC electrical characteristics
- 165 FMC characteristics
- 185 Quad-SPI interface characteristics
- 186 Camera interface (DCMI) timing specifications
- 187 LCD-TFT controller (LTDC) characteristics
- 189 SD/SDIO MMC card host interface (SDIO) characteristics
- 191 RTC characteristics
- 192 Package information
- 192 LQFP100 package information
- 195 LQFP144 package information
- 198 WLCSP168 package information
- 200 UFBGA169 package information
- 203 LQFP176 package information
- 207 UFBGA(176+25) package information
- 208 LQFP208 package information
- 212 TFBGA216 package information
- 215 Thermal characteristics
- 216 Part numbering
- 217 Appendix A Recommendations when using internal reset OFF
- 217 Operating conditions
- 218 Revision history