Working with Hardware Tools
Hardware Diagnostics Window
Hardware Diagnostics Window
The Hardware Diagnostics window lists global options for the hardware diagnostic tools.
These preferences apply to every open project file.
Figure 22.7
shows the Hardware Diagnostics window.
Table 22.7
explains items in the window.
To open the Hardware Diagnostics window, click Tools > Hardware Diagnostics.
The Hardware Diagnostics window has these panels:
•
Configuration
•
Memory Read / Write
•
Scope Loop
•
Memory Tests
Figure 22.7 Hardware Diagnostics window
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Hardware Diagnostics Window
Table 22.7 Hardware Diagnostics Window Items
Item
Hardware
Diagnostics pane
Load Settings
Save Settings
OK button
Cancel button
Explanation
Shows a list of panel names. Click a panel name to display that panel in the Hardware Diagnostics window.
Click to restore previously saved settings for the current panel.
Click to save settings for the current panel to a file.
Click to save changes to all panels and close the window.
Click to discard changes to all panels and close the window.
Configuration
The Configuration panel configures general flash programmer settings. Figure 22.8
shows the Configuration panel. Table 22.8
explains items in the panel.
Figure 22.8 Configuration Panel
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Table 22.8 Configuration Panel Items
Item
Default Project
Default Target
Use Custom
Settings checkbox.
Explanation
Shows the current default project in the IDE.
Shows the default build target in the IDE. Clear the Use Custom
Settings checkbox to have the IDE use the connection settings from the build target for diagnosing the hardware.
Check to specify the connection information that you want to use for diagnosing the hardware. In this case, the IDE can connect to the hardware without using settings from a project.
Clear to use the connection information stored in the default project for connecting to the hardware. You cannot clear the checkbox if you do not have an active default project or default target.
Connection information includes information that you specify in the
Target Processor list box, the Connection list box, and the Use
Target Initialization text box.
Use to specify the hardware processor.
Target
Processor text/list box
Connection list box
Use Target
Initialization checkbox and text box
Use to specify the method that the IDE uses to connect to the hardware.
Check to specify an initialization file for the hardware connection.
Enter the initialization file path in the text box, or click the Browse button to locate the initialization file path.
Clear if you do not want to use an initialization file for the hardware connection.
Memory Read / Write
The Memory Read / Write panel configures diagnostic tests for performing memory reads and writes over the remote connection interface.
Figure 22.9
shows the Memory
Read / Write panel.
Table 22.9
explains items in the panel.
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Figure 22.9 Memory Read / Write Panel
Working with Hardware Tools
Hardware Diagnostics Window
Table 22.9 Memory Read / Write Panel Items
Item
Read
Write
Byte
Word
Long Word
Target Address
Explanation
Select to have the hardware diagnostic tools perform read tests.
Select to have the hardware diagnostic tools perform write tests.
Select to have the hardware diagnostic tools perform bytesize operations.
Select to have the hardware diagnostic tools perform word-size operations.
Select to have the hardware diagnostic tools perform long-word-size operations.
Specify the address of an area in RAM that the hardware diagnostic tools should analyze. The tools must be able to access this starting address through the remote connection (after the hardware initializes).
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Hardware Diagnostics Window
Table 22.9 Memory Read / Write Panel Items ( continued)
Item
Value to Write
Status
Access Target button
Explanation
Specify the value that the hardware diagnostic tools write during testing.
Select the Write option to enable this text box.
Shows hardware diagnostic progress information. Click the Details button to show more progress information.
Click to have the hardware diagnostic tools perform specified tests.
The Status shows test results.
Scope Loop
The Scope Loop panel configures diagnostic tests for performing repeated memory reads and writes over the remote connection interface. The tests repeat until you stop them. By performing repeated read and write operations, you can use a scope analyzer or logic analyzer to debug the hardware device.
Figure 22.10
shows the Scope Loop panel.
Table 22.10
explains items in the panel.
After the first 1000 operations, the Status shows the estimated time between operations.
NOTE
For all values of Speed, the time between operations depends heavily on the processing speed of the host computer.
For Read operations, the Scope Loop test has an additional feature. During the first read operation, the hardware diagnostic tools store the value read from the hardware. For all successive read operations, the hardware diagnostic tools compare the read value to the stored value from the first read operation. If the Scope Loop test determines that the value read from the hardware is not stable, the diagnostic tools report the number of times that the read value differs from the first read value.
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Figure 22.10 Scope Loop Panel
Working with Hardware Tools
Hardware Diagnostics Window
Table 22.10 Scope Loop Panel Items
Item
Read
Write
Byte
Word
Long Word
Target
Address
Value to Write
Explanation
Select to have the hardware diagnostic tools perform read tests.
Select to perform write tests.
Select to have the hardware diagnostic tools perform bytesize operations.
Select to perform word-size operations.
Select to perform long-word-size operations.
Specify the address of an area in RAM that the hardware diagnostic tools should analyze. The tools must be able to access this starting address through the remote connection (after the hardware initializes).
Specify the value that the hardware diagnostic tools write during testing.
Select the Write option to enable this text box.
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Hardware Diagnostics Window
Table 22.10 Scope Loop Panel Items ( continued)
Item
Speed slider
Status
Begin Scope
Loop button
Explanation
Move to adjust the speed at which the hardware diagnostic tools repeat successive read and write operations. Lower speeds increase the delay between successive operations. Higher speeds decrease the delay between successive operations.
Shows hardware diagnostic progress information. Click the Details button to show more thorough progress information.
Click to have the hardware diagnostic tools perform your specified tests. The Status shows test results.
Memory Tests
The Memory Tests panel lets you perform three different tests on the hardware:
•
Walking Ones
•
Address
•
Bus Noise
Figure 22.11
shows the Memory Tests panel. Table 22.11
explains items in the panel.
You can specify any combination of tests and number of passes to perform. For each pass, the hardware diagnostic tools perform the tests in turn, until all passes are complete. The tools tally memory test failures and display them in a log window after all passes are complete. Errors resulting from memory test failures do not stop the testing process, however, fatal errors immediately stop the testing process.
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Figure 22.11 Memory Tests Panel
Working with Hardware Tools
Hardware Diagnostics Window
Table 22.11 Memory Tests Panel Items
Item
Walking 1’s
Address
Bus Noise
Start:
End:
Byte
Explanation
Check to have the hardware diagnostic tools perform the
Walking
Ones test.
Clear to have the diagnostic tools skip the Walking Ones test.
Check to have the hardware diagnostic tools perform the Address
test.
Clear to have the diagnostic tools skip the Address
test.
Check to have the hardware diagnostic tools perform the
Bus Noise
test.
Clear to have the diagnostic tools skip the Bus Noise test.
Enter the starting address of the range that you want to test.
Enter the ending address of the range that you want to test.
Select to have the hardware diagnostic tools perform bytesize operations.
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Hardware Diagnostics Window
Table 22.11 Memory Tests Panel Items ( continued)
Item
Word
Long Word
Passes
Show Log
Use Target
CPU
Target
Scratch
Memory Start
Target
Scratch
Memory End
Status
Begin Test
Explanation
Select to have the hardware diagnostic tools perform word-size operations.
Select to have the hardware diagnostic tools perform long-word-size operations.
Enter the number of times that you want to repeat the specified tests.
Click to display a text file that logs memory test actions.
Check to have the hardware diagnostic tools download the test code to the hardware device. Enter in the Target Scratch Memory Start and Target Scratch Memory End text boxes the memory range that you want to use on the hardware device. The CPU on the hardware device executes the test code in this memory range.
Clear to have the hardware diagnostic tools execute the test code through the remote connection interface.
Execution performance improves greatly if you execute the test code on the hardware CPU, but requires that the hardware has enough stability and robustness to execute the test code.
Specify the starting address of an area in RAM that the hardware diagnostic tools can use as a scratch area. The tools must be able to access this starting address through the remote connection (after the hardware initializes).
Specify the ending address of an area in RAM that the hardware diagnostic tools can use as a scratch area. The tools must be able to access this address through the remote connection (after the hardware initializes).
Shows memory test progress information. Click the Details button to show more thorough progress information.
Click to have the hardware diagnostic tools perform the memory tests that you specified. The Status reflects memory test progress.
Walking Ones
This test detects these memory faults:
• Address Line—The board or chip address lines are shorting or stuck at 0 or 1. Either condition could result in errors when the hardware reads and writes to the memory
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Hardware Diagnostics Window location. Because this error occurs on an address line, the data may end up in the wrong location on a write operation, or the hardware may access the wrong data on a read operation.
• Data Line—The board or chip data lines are shorting or stuck at 0 or 1. Either condition could result in corrupted values as the hardware transfers data to or from memory.
• Retention—The contents of a memory location change over time. The effect is that the memory fails to retain its contents over time.
The Walking Ones test includes four subtests:
• Walking Ones—This subtest first initializes memory to all zeros. Then the subtest writes, reads, and verifies bits, with each bit successively set from the least significant bit (LSB) to the most significant bit (MSB). The subtest configures bits such that by the time it sets the MSB, all bits set to a value of 1. This pattern repeats for each location within the memory range that you specify. For example, the values for a byte-based Walking Ones subtest occur in this order:
0x01, 0x03, 0x07, 0x0F, 0x1F, 0x3F, 0x7F, 0xFF
• Ones Retention—This subtest immediately follows the Walking Ones subtest. The
Walking Ones subtest should leave each memory location with all bits set to 1. The Ones Retention subtest verifies that each location has all bits set to 1.
• Walking Zeros—This subtest first initializes memory to all ones. Then the subtest writes, reads, and verifies bits, with each bit successively set from the LSB to the
MSB. The subtest configures bits such that by the time it sets the MSB, all bits are set to a value of 0. This pattern repeats for each location within the memory range that you specify. For example, the values for a byte-based Walking Zeros subtest occur in this order:
0xFE, 0xFC, 0xF8, 0xF0, 0xE0, 0xC0, 0x80, 0x00
• Zeros Retention—This subtest immediately follows the Walking Zeros subtest. The
Walking Zeros subtest should leave each memory location with all bits set to 0. The
Zeros Retention subtest verifies that each location has all bits set to 0.
Address
This test detects memory aliasing. Memory aliasing exists when a physical memory block repeats one or more times in a logical memory space. Without knowing about this condition, you might conclude that there is much more physical memory than what actually exists.
The address test uses a simplistic technique to detect memory aliasing. The test writes sequentially increasing data values (starting at one and increasing by one) to each successive memory location. The maximum data value is a prime number and its specific value depends on the addressing mode so as to not overflow the memory location.
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The test uses a prime number of elements to avoid coinciding with binary math boundaries:
• For byte mode, the maximum prime number is 2
8
-5 or 251.
• For word mode, the maximum prime number is 2
16
-15 or 65521.
• For long word mode, the maximum prime number is 2
32
-5 or 4294967291.
If the test reaches the maximum value, the value rolls over to 1 and starts incrementing again. This sequential pattern repeats throughout the memory under test. Then the test reads back the resulting memory and verifies it against the written patterns. Any deviation from the written order could indicate a memory aliasing condition.
Bus Noise
This test stresses the memory system by causing many bits to flip from one memory access to the next (both addresses and data values). Bus noise occurs when many bits change consecutively from one memory access to another. This condition can occur on both address and data lines.
Address lines
To force bit flips in address lines, the test uses three approaches:
• Sequential—This approach works sequentially through all of the memory under test, from lowest address to highest address. This sequential approach results in an average number of bit flips from one access to the next.
• Full Range Converging—This approach works from the fringes of the memory range toward the middle of the memory range. Memory access proceeds in this pattern, where + number and - number refer to the next item location (the specific increment or decrement depends on byte, word, or long word address mode):
– the lowest address
– the highest address
– (the lowest address) + 1
– (the highest address) - 1
– (the lowest address) + 2
– (the highest address) - 2
• Maximum Invert Convergence—This approach uses calculated end point addresses to maximize the number of bits flipping from one access to the next. This approach involves identifying address end points such that the values have the maximum inverted bits relative to one another. Specifically, the test identifies the lowest address with all 0x5 values in the least significant nibbles and the highest address with all 0xA values in the least significant nibbles. After the test identifies these end
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