STMicroelectronics VN5050AJ-E Datasheet

VN5050AJ-E

Single channel high side driver with analog current sense for automotive applications

Features

Max supply voltage

Operating voltage range

Max On-State resistance

Current limitation (typ)

Off state supply current

V

CC

V

CC

R

ON

I

LIMH

I

S

41 V

4.5 to 36V

50 m

Ω

16.5 A

2 µA

■

■

■

General features

– Inrush current active management by power limitation

– Very low stand-by current

– 3.0V CMOS compatible input

– Optimized electromagnetic emission

– Very low electromagnetic susceptibility

– In compliance with the 2002/95/EC

European directive

Diagnostic functions

– Proportional load current sense

– High current sense precision for wide range currents

– Current sense disable

– Thermal shutdown indication

– Very low current sense leakage

Protection

– Undervoltage shut-down

– Overvoltage clamp

– Load current limitation

– Self limiting of fast thermal transients

– Protection against loss of ground and loss of V

CC

– Thermal shut down

Table 1.

Device summary

Package

PowerSSO-12

PowerSSO-12

– Reverse battery protection ( see

Application schematic

)

– Electrostatic discharge protection

Application

■

■

All types of resistive, inductive and capacitive loads

Suitable as LED driver

Description

The VN5050AJ-E is a monolithic device made using STMicroelectronics VIPower technology. It is intended for driving resistive or inductive loads with one side connected to ground. Active V

CC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table).

This device integrates an analog current sense which delivers a current proportional to the load current (according to a known ratio) when

CS_DIS is driven low or left open.

When CS_DIS is driven high, the CURRENT

SENSE pin is in a high impedance condition.

Output current limitation protects the device in overload condition. In case of long overload duration, the device limits the dissipated power to safe level up to thermal shut-down intervention.

Thermal shut-down with automatic restart allows the device to recover normal operation as soon as fault condition disappears.

Order codes

Tube

VN5050AJ-E

Tape and Reel

VN5050AJTR-E

September 2013 Rev 7 1/31

www.st.com

31

1

2

Contents

Contents

3

4

5

6

VN5050AJ-E

Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2

Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.4

Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.1

GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 21

3.1.1

Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 21

3.1.2

Solution 2: diode (D

GND

) in the ground line . . . . . . . . . . . . . . . . . . . . . . 22

3.2

Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.3

MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.4

Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 23

Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1

PowerSSO-12™ thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.1

ECOPACK

®

packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.2

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.3

Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2/31

VN5050AJ-E

List of tables

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Suggested connections for unused and N.C. pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 5.

Table 6.

Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 7.

Table 8.

Switching (V

CC

=13V, T j

=25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Protection and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 9.

Table 10.

Current sense (8V<V

CC

<16V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 11.

Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 12.

Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 13.

Thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 14.

PowerSSO-12™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 15.

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3/31

List of figures

List of figures

VN5050AJ-E

Figure 1.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2.

Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3.

Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4.

Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 5.

Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 6.

Delay response time between rising edge of ouput current and rising edge of current sense

(CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 7.

Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 8.

I

OUT

/I

SENSE

Vs. I

OUT

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 9.

Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 10.

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 11.

Off state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 12.

High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 13.

Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 14.

Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 15.

Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 16.

Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 17.

On state resistance vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 18.

On state resistance vs. VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 19.

Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 20.

Turn-On voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 21.

ILIMH Vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 22.

Turn-Off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 23.

CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 24.

CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 25.

CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 26.

Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 27.

Maximum turn Off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 28.

PowerSSO-12™ PC Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 29.

Rthj-amb Vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . 24

Figure 30.

PowerSSO-12™ thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . 25

Figure 31.

Thermal fitting model of a single channel HSD in PowerSSO-12™ . . . . . . . . . . . . . . . . . 25

Figure 32.

PowerSSO-12™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 33.

PowerSSO-12™ tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 34.

PowerSSO-12™ tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4/31

VN5050AJ-E

1

Block diagram and pin description

Block diagram and pin description

Figure 1.

Block diagram

V

CC

GND

INPUT

V

CC

CLAMP

LOGIC

UNDERVOLTAGE

PwCLAMP

DRIVER

I

LIM

V

DSLIM

Pwr

LIM

OVERTEMP.

I

OUT

K

CS_DIS

OUTPUT

CURRENT

SENSE

Table 2.

Name

Pin function

Function

V

CC

OUTPUT

Battery connection.

GND

INPUT

Power output.

Ground connection. Must be reverse battery protected by an external diode/resistor network.

Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state.

CURRENT SENSE Analog current sense pin, delivers a current proportional to the load current.

CS_DIS Active high CMOS compatible pin, to disable the current sense pin.

5/31

Block diagram and pin description

Figure 2.

Configuration diagram (top view)

N.C.

GND

INPUT

CURRENT SENSE

CS_DIS

N.C.

1

2

3

4

5

6

12

11

10

9

8

7

TAB = V cc

N.C.

OUTPUT

OUTPUT

OUTPUT

OUTPUT

N.C.

VN5050AJ-E

Note: The above pin configuration reflects the changes notified with PCN-APG-BOD/07/2886. The new pinout is backaward compatible with existing PCB layouts where pins #1 and #6 are connected to Vcc and/or pins #7 and 12 are connected to OUTPUT. For new PCB designs, these pins should be left unconnected.

Table 3.

Suggested connections for unused and N.C. pins

Connection / Pin Current Sense N.C.

Output Input

Floating

To ground

N.R.

Through 1k

Ω

resistor

X

X

X

N.R.

(1)

CS_DIS

X X

Through 10k

Ω resistor

Through

10k

Ω

resistor

1.

Not recommended.

6/31

VN5050AJ-E Electrical specifications

Figure 3.

Current and voltage conventions

V

CSD

V

IN

I

CSD

I

IN

I

S

V

CC

V

F

I

OUT

CS_DIS

OUTPUT

INPUT

CURRENT SENSE

GND

I

GND

I

SENSE

V

SENSE

V

OUT

V

CC

Note: V

F

= V

OUT

- V

CC

during reverse battery condition.

Stressing the device above the rating listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to the conditions in table below for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality document.

Table 4.

Symbol

V

CC

-V

CC

- I

GND

Absolute maximum ratings

Parameter

DC supply voltage

Reverse DC supply voltage

DC reverse ground pin current

I

OUT

DC output current

- I

OUT

I

IN

I

CSD

-I

CSENSE

Reverse DC output current

DC input current

DC current sense disable input current

DC reverse CS pin current

V

CSENSE

Current sense maximum voltage

E

MAX

Maximum switching energy (single pulse)

(L= 3mH; R

L

=0

Ω

; V bat

=13.5V; T jstart

=150ºC; I

OUT

= I limL

(Typ.) )

Value

41

0.3

200

Internally limited

30

-1 to 10

-1 to 10

200

V

CC

-41

+V

CC

104

Unit

V

V mA

A

A mA mA mA

V

V mJ

7/31

Electrical specifications VN5050AJ-E

Table 4.

Symbol

V

ESD

V

ESD

T j

T stg

Absolute maximum ratings (continued)

Parameter

Electrostatic discharge (Human Body Model: R=1.5k

Ω;

C=100pF)

- INPUT

- CURRENT SENSE

- CS_DIS

- OUTPUT

- V

CC

Charge device model (CDM-AEC-Q100-011)

Junction operating temperature

Storage temperature

Value Unit

4000

2000

4000

5000

5000

750

-40 to 150

-55 to 150

V

V

V

V

V

V

°C

°C

8/31

Table 5.

Symbol

Thermal data

Parameter

R thj-case

R thj-amb

Thermal resistance junction-case (MAX)

Thermal resistance junction-ambient (MAX)

Max value Unit

2.7

°C/W

See

Figure 29.

°C/W

VN5050AJ-E Electrical specifications

Values specified in this section are for 8V < VCC < 36V; -40°C < Tj < 150°C, unless otherwise specified.

Table 6.

Symbol

Power section

Parameter Test conditions Min. Typ. Max.

Unit

V

CC

Operating supply voltage

V

USD

Undervoltage shutdown

V

USDhyst

Undervoltage shutdown hysteresis

V

I

R clamp

I

L(off)

V

ON

S

F

On state resistance

Clamp voltage

Supply current

I

OUT

= 2A; T j

=25°C

I

OUT

= 2A; T j

=150°C

I

OUT

= 2A; V

CC

=5V; T j

=25°C

I

S

= 20mA

Off State; V

CC

=13V; T j

=25°C;

V

IN

=V

OUT

=V

SENSE

=V

CSD

=0V

On State; V

CC

=13V; V

IN

=5V; I

OUT

=0A

Off state output current

V

IN

=V

OUT

=0V; V

CC

=13V; T j

=25°C

V

IN

=V

OUT

=0V; V

CC

=13V; T j

=125°C

Output - V

CC

diode voltage

-I

OUT

= 2A; T j

= 150°C

4.5

13

41

0

0

3.5

0.5

46

2

(1)

1.5

36

4.5

5

(1)

3

0.01

3

5

0.7

50

100

65

52

1.

PowerMOS leakage included.

Table 7.

Symbol

Switching (V

CC

=13V, T

Parameter j

=25°C)

Test conditions

t d(on) t d(off)

Turn-on delay time

Turn-off delay time

R

L

= 6.5

Ω

(see

Figure 7.

)

R

L

= 6.5

Ω

(see

Figure 7.

)

(dV

OUT

/dt) on

Turn-on voltage slope R

L

= 6.5

Ω

(dV

OUT

/dt) off

Turn-off voltage slope R

L

= 6.5

Ω

Min.

Typ.

20

40

See

Figure 20

See

Figure 22

V

V

V m

Ω m

Ω m

Ω

V

µA mA

µA

V

Max. Unit

µs

µs

V

/

µs

V

/

µs

W

ON

W

OFF

Switching energy losses during tw on

Switching energy losses during tw off

R

L

= 6.5

Ω

(see

Figure 7.

)

R

L

= 6.5

Ω

(see

Figure 7.

)

0.20

0.3

mJ mJ

9/31

Electrical specifications VN5050AJ-E

Table 8.

Symbol

Logic input

Parameter Test conditions

V

IL

I

IL

V

IH

I

IH

V

I(hyst)

Input low level voltage

Low level input current

Input high level voltage

High level input current

Input hysteresis voltage

V

V

IN

IN

= 0.9V

= 2.1V

V

ICL

Input clamp voltage

I

IN

= 1mA

I

IN

= -1mA

V

CSDL

I

CSDL

V

CSDH

CS_DIS low level voltage

Low level CS_DIS current V

CS_DIS high level voltage

CSD

= 0.9V

I

CSDH

High level CS_DIS current V

CSD

= 2.1V

V

CSD(hyst)

CS_DIS hysteresis voltage

V

CSCL

CS_DIS clamp voltage

I

CSD

= 1mA

I

CSD

= -1mA

Table 9.

Symbol

Protection and diagnostics

Parameter

(1)

Test conditions

Min.

Typ.

Max.

Unit

0.9

1

2.1

0.25

5.5

1

2.1

0.25

5.5

-0.7

-0.7

10

7

0.9

10

7

V

µA

V

µA

V

V

V

V

µA

V

µA

V

V

V

Min.

Typ.

Max.

Unit

I

I limH limL

T

TSD

Shutdown temperature

Reset temperature T

R

T

T

RS

HYST

V

DEMAG

Thermal reset of

STATUS

Thermal hysteresis

(T

TSD

-T

R

)

Turn-off output voltage clamp

I

OUT

= 2A; V

IN

= 0; L= 6mH

V

ON

DC Short circuit current

V

CC

= 13V

5V<V

CC

<36V

Short circuit current during thermal cycling

V

CC

=13V T

R

<T j

<T

TSD

Output voltage drop limitation

I

OUT

= 0.1A;

T j

= -40°C...+150°C

(see

Figure 5.

)

T

V

12

150

RS

CC

+ 1 T

135

-41 V

16.5

175

RS

7

7

CC

+ 5

-46 V

25

23

23

200

CC

1.

To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device operates under abnormal conditions this software must limit the duration and number of activation cycles.

A

A

A

°C

°C

°C

°C

-52 V mV

10/31

VN5050AJ-E Electrical specifications

Table 10.

Current sense (8V<V

CC

<16V)

Symbol Parameter Test conditions Min. Typ. Max. Unit

K

K

0

1 dK

1

/K

1

(1)

K dK

2

/K

2

(1)

K

3 dK

3

/K

3

(1)

I

SENSE0

I

2

OL

I

OUT

/I

SENSE

I

OUT

= 0.05A; V

SENSE

=0.5V; V

CSD

=0V;

T j

= -40°C...150°C

I

I

OUT

/I

SENSE

Current sense ratio drift

I

OUT

=1A; V

SENSE

=0.5V; V

CSD

=0V;

T j

= -40°C...150°C

I

OUT

= 1A; V

SENSE

= 0.5V; V

CSD

= 0V;

T j

= 25°C...150°C

I

OUT

=1A; V

SENSE

= 0.5V;

V

CSD

=0V;

T

J

=-40 °C to 150 °C

OUT

/I

SENSE

I

OUT

= 2A; V

SENSE

= 4V; V

CSD

= 0V;

T j

= -40°C...150°C

I

OUT

= 2A; V

SENSE

= 4V; V

CSD

= 0V;

T j

= 25°C...150°C

Current sense ratio drift

I

OUT

= 2 A; V

SENSE

= 4 V;

V

CSD

= 0V;

T

J

= -40 °C to 150 °C

I

OUT

/I

SENSE

Current sense ratio drift

Analog sense leakage current

I

OUT

= 4A; V

SENSE

= 4V; V

CSD

= 0V;

T j

= -40°C...150°C

I

OUT

= 4A; V

SENSE

= 4V; V

CSD

= 0V;

T j

= 25°C...150°C

I

OUT

= 4 A; V

SENSE

= 4 V;

V

CSD

=0V;

T

J

=-40 °C to 150 °C

I

OUT

= 0A; V

SENSE

=0V;

V

CSD

= 5V; V

IN

=0V; T j

= -40°C...150°C

V

CSD

= 0V; V

IN

=5V; T j

= -40°C...150°C

I

OUT

= 2A; V

SENSE

= 0V;

V

CSD

= 5V; V

IN

=5V; T j

= -40°C...150°C

Openload ON state current detection threshold

V

IN

= 5V, I

SENSE

= 5 µA

V

SENSEH

I

V

SENSE

SENSEH

Max analog sense output voltage

Analog sense output voltage in overtemperature condition

Analog sense output current in overtemperature condition

I

OUT

V

V

CC

CC

=2A; V

=13V; R

=13V, V

CSD

=0V 5

SENSE

SENSE

=10K

=5V

Ω

1100 2440 3480

1600

1630

-10

1770

1800

-6

1860

1870

-3

0

0

0

4

2030

2030

2000

2000

1970

1970

9

8

2580

2430

+10

2310

2200

+6

2140

2120

+3

1

2

1

20

%

%

%

µA

µA

µA mA

V

V mA

11/31

Electrical specifications

Table 10.

Current sense (8V<V

CC

<16V) (continued)

Symbol Parameter Test conditions

t t

DSENSE1H

Delay response time from falling edge of CS_DIS pin

V

SENSE

<4V, 0.5A<Iout<4A

I

SENSE

=90% of I

SENSEmax

(see

Figure 4.

)

t

DSENSE1L

Delay response time from rising edge of CS_DIS pin

V

SENSE

<4V, 0.5A<Iout<4A

I

SENSE

=10% of I

SENSEmax

(see

Figure 4.

)

DSENSE2H

Delay response time from rising edge of INPUT pin

V

SENSE

<4V, 0.5A<Iout<4A

I

SENSE

=90% of I

SENSE max

(see

Figure 4.

)

Δ t

DSENSE2H

Delay response time between rising edge of output current and rising edge of current sense

V

SENSE

< 4V,

I

SENSE

= 90% of I

SENSEMAX,

I

OUT

= 90% of I

OUTMAX

I

OUTMAX

=2A (see

Figure 6

) t

DSENSE2L

Delay response time from falling edge of INPUT pin

V

SENSE

<4V, 0.5A<Iout<4A

I

SENSE

=10% of I

SENSE max

(see

Figure 4.

)

1.

Parameter guaranteed by design; it is not tested.

Figure 4.

Current sense delay characteristics

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT t

DSENSE2H t

DSENSE1L

VN5050AJ-E

Min. Typ. Max. Unit

50 100 µs

5 20 µs

80 250 µs

65 s

µ

100 250 µs t

DSENSE1H t

DSENSE2L

Figure 5.

Output voltage drop limitation

V cc

-V out

T j

=150 o

C

T j

=25 o

C

T j

=-40 o

C

V on

I out

12/31

V on

/R on(T)

VN5050AJ-E Electrical specifications

Figure 6.

Delay response time between rising edge of ouput current and rising edge of current sense (CS enabled)

V

IN

Δ t

DSENSE2H t

I

OUT

90% I

OUTMAX

I

OUTMAX t

I

SENSE I

SENSEMAX

90% I

SENSEMAX t

Figure 7.

Switching characteristics

V

OUT t

Won

80% dV

OUT

/dt

(on) t r

10%

INPUT t d(on) t d(off) t

Woff

90% t f dV

OUT

/dt

(off) t t

13/31

Electrical specifications

Figure 8.

I

OUT

/I

SENSE

Vs. I

OUT

(see

Table 10.

for details)

I out

/ I sense

2800

2600

2400

max Tj = -40 °C to 150 °C

2200

max Tj = 25 °C to 150 °C

2000

1800

min Tj = 25 °C to 150 °C

1600

min Tj = -40 °C to 150 °C

1400

1200

1 1,5 2

typical value

2,5 3

I

OUT

(A)

3,5 4 4,5

VN5050AJ-E

5

Note:

Figure 9.

Maximum current sense ratio drift vs load current dk/k(%)

15

10

5

0

-5

-10

-15

1 2

I

OUT

(A)

Parameter guaranteed by design; it is not tested.

3 4

14/31

VN5050AJ-E Electrical specifications

Table 11.

Truth table

Conditions

Normal operation

Overtemperature

Undervoltage

Short circuit to GND

(R sc

≤

10 m

Ω

)

Short circuit to V

CC

Input

L

H

L

H

H

L

H

L

H

L

H

Output

L

H

L

L

L

L

L

L

L

H

H

Sense (V

CSD

=0V)

(1)

0

Nominal

0

V

SENSEH

0

0

0

0 if T j

< T

TSD

V

SENSEH

if T j

> T

TSD

0

< Nominal

Negative output voltage clamp

L L 0

1.

If the V

CSD

is high, the SENSE output is at a high impedance, its potential depends on leakage currents and external circuit.

15/31

Electrical specifications VN5050AJ-E

Table 12.

Electrical transient requirements

Test levels ISO 7637-2:

2004(E)

Test pulse

1

2a

3a

3b

4

5b

(2)

III

-75V

+37V

-100V

+75V

-6V

+65V

IV

-100V

+50V

-150V

+100V

-7V

+87V

Number of pulses or test times

5000 pulses

5000 pulses

1h

1h

1 pulse

1 pulse

Burst cycle/pulse repetition time

0.5 s

0.2 s

90 ms

90 ms

5 s

5 s

100 ms

100 ms

Delays and

Impedance

2 ms, 10

Ω

50

μ s, 2

Ω

0.1

μ s, 50

Ω

0.1

μ s, 50

Ω

100 ms, 0.01

Ω

400 ms, 2

Ω

ISO 7637-2:

2004(E)

Test pulse

1

2a

III

C

C

Test level results

(1)

IV

3a

3b

C

C

4

5b

(2)

C C

C C

1.

The above test levels must be considered referred to V

CC

= 13.5V except for pulse 5b.

2.

Valid in case of external load dump clamp: 40V maximum referred to ground.

C

C

C

C

Class

C

E

Contents

All functions of the device are performed as designed after exposure to disturbance.

One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.

16/31

VN5050AJ-E

Figure 10.

Waveforms

Electrical specifications

NORMAL OPERATION

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT

V

CC

INPUT

CS_DIS

LOAD CURRENT

SENSE CURRENT

V

USD

UNDERVOLTAGE

V

USDhyst

SHORT TO V

CC

INPUT

CS_DIS

LOAD VOLTAGE

LOAD CURRENT

SENSE CURRENT

<Nominal

<Nominal

OVERLOAD OPERATION

T j

INPUT

CS_DIS

LOAD CURRENT

T

R

T

TSD

T

RS

SENSE CURRENT current limitation power limitation thermal cycling

SHORTED LOAD

I

I

LIMH

LIML

V

SENSEH

NORMAL LOAD

17/31

Electrical specifications

Figure 11.

Off state output current Figure 12.

High level input current

VN5050AJ-E

TBD

Figure 13.

Input clamp voltage Figure 14.

Input low level

Figure 15.

Input high level Figure 16.

Input hysteresis voltage

18/31

VN5050AJ-E

Figure 17.

On state resistance vs. T case

Electrical specifications

Figure 18.

On state resistance vs. V

CC

Figure 19.

Undervoltage shutdown Figure 20.

Turn-On voltage slope

Figure 21.

I

LIMH

Vs. T case

TBD

Figure 22.

Turn-Off voltage slope

19/31

Electrical specifications

Figure 23.

CS_DIS high level voltage Figure 24.

CS_DIS clamp voltage

VN5050AJ-E

Figure 25.

CS_DIS low level voltage

20/31

VN5050AJ-E Application information

Figure 26.

Application schematic

+5V

μ

C

V

CC

R prot

CS_DIS

C ext

R prot

R prot

R

SENSE

INPUT

CURRENT SENSE

GND

V

GND

R

GND

D

GND

OUTPUT

.

D ld

3.1

3.1.1

GND protection network against reverse battery

This section provides two solutions for implementing a ground protection network against reverse battery.

Solution 1: resistor in the ground line (R

GND

only)

This can be used with any type of load.

The following show how to dimension the R

GND resistor:

1.

R

GND

≤

600mV / (I

S(on)max

)

2. R

GND

≥ (−

V

CC

) / (-I

GND

) where -I

GND

is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet.

Power dissipation in R

GND

(when V

CC

<0 during reverse battery situations) is:

P

D

= (-V

CC

)

2

/ R

GND

This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where I

S(on)max

becomes the sum of the maximum on-state currents of the different devices.

Please note that, if the microprocessor ground is not shared by the device ground, then the

R

GND will produce a shift (I

S(on)max

* R

GND

) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same R

GND

.

21/31

Application information

3.1.2

VN5050AJ-E

If the calculated power dissipation requires the use of a large resistor, or several devices have to share the same resistor, then ST suggests using solution 2 below.

Solution 2: diode (D

GND

) in the ground line

Note that a resistor (R

GND

=1k

Ω

) should be inserted in parallel to D an inductive load.

GND

if the device drives

This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift ( j 600mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network.

3.2 Load dump protection

D ld

is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the

V

CC

maximum DC rating. The same applies if the device is subject to transients on the V

CC line that are greater than those shown in the ISO T/R 7637/1 table.

3.3 MCU I/O protection

If a ground protection network is used and negative transients are present on the V

CC

line, the control pins will be pulled negative. ST suggests to insert a resistor (R prot

) in line to prevent the

µ

C I/O pins from latching up.

The value of these resistors is a compromise between the leakage current of

µ

C and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of

µ

C

I/Os:

-V

CCpeak

/I latchup

≤

R prot

≤

(V

OH

μ

C

-V

IH

-V

GND

) / I

IHmax

Equation 1:

For the following conditions:

V

CCpeak

= - 100V

I latchup

≥

20mA

V

OH

μ

C

≥

4.5V

5k

Ω ≤

R prot

≤

180k

Ω

.

Recommended values are:

R prot

=10k

Ω

, C

EXT

=10nF

22/31

VN5050AJ-E

3.4

Application information

Maximum demagnetization energy (V

CC

= 13.5V)

Figure 27.

Maximum turn Off current versus inductance

100

C

C

A

A

B

B

10

1

0,1 1

A: T jstart

= 150°C single pulse

B: T jstart

= 100°C repetitive pulse

C: T jstart

= 125°C repetitive pulse

L (mH)

V

IN

, I

L

Demagnetization

10

Demagnetization

100

Demagnetization

Note:

t

Values are generated with R

L

=0

Ω.

In case of repetitive pulses, T jstart

(at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B.

23/31

Package and PCB thermal data

4 Package and PCB thermal data

Figure 28. PowerSSO-12™ PC Board

VN5050AJ-E

Note: Layout condition of R th

and Z th

measurements (PCB: Double layer, Thermal Vias, FR4 area= 77mm x 86mm,PCB thickness=1.6mm, Cu thickness=70 µm (front and back side),

Copper areas: from minimum pad lay-out to 8cm

2

).

Figure 29. R thj-amb

Vs. PCB copper area in open box free air condition

RTHj_amb( ° C/ W)

65

60

55

50

45

40

35

0 2 4 6

PCB Cu heat sink area ( cm^ 2)

8 10

24/31

VN5050AJ-E Package and PCB thermal data

Figure 30. PowerSSO-12™ thermal impedance junction ambient single pulse

ZTH ( ° C/ W)

100

Footprint

2 cm

2

8 cm

2

10

1

0,1

0,001 0,01 0,1 1

Time ( s)

10 100 1000

Equation 2: pulse calculation formula

Z

TH

δ

= R

TH where

δ

= t

P

/T

⋅ δ

+ Z

THtp

(

1 –

δ )

Figure 31. Thermal fitting model of a single channel HSD in PowerSSO-12™

(a)

a.

The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered.

25/31

Package and PCB thermal data

Table 13.

Thermal parameter

Area/island (cm

2

)

R1 (°C/W)

R2 (°C/W)

R3 (°C/W)

R4 (°C/W)

R5 (°C/W)

R6 (°C/W)

C1 (W.s/°C)

C2 (W.s/°C)

C3 (W.s/°C)

C4 (W.s/°C)

C5 (W.s/°C)

C6 (W.s/°C)

Footprint

0.001

0.0025

0.0166

0.2

0.27

3

0.7

2.8

3

8

22

26

2

VN5050AJ-E

8

8

15

20

7

10

15

0.1

0.8

6

0.1

1

9

26/31

VN5050AJ-E Package information

5.1 ECOPACK

®

packages

In order to meet environmental requirements, ST offers these devices in ECOPACK

® packages. These packages have a Lead-free second-level interconnect. The category of

Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97.

The maximum ratings related to soldering conditions are also marked on the inner box label.

ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

Figure 32. PowerSSO-12™ package dimensions

27/31

Package information

Table 14.

PowerSSO-12™ mechanical data

Symbol

h

L k e

H

X

Y ddd

B

C

D

E

A

A1

A2

5.800

0.250

0.400

0°

2.200

2.900

Min.

1.250

0.000

1.100

0.230

0.190

4.800

3.800

Millimeters

Typ.

0.800

VN5050AJ-E

6.200

0.500

1.270

8°

2.800

3.500

0.100

Max.

1.620

0.100

1.650

0.410

0.250

5.000

4.000

28/31

VN5050AJ-E Package information

Figure 33. PowerSSO-12™ tube shipment (no suffix)

B

A

C

Base Q.ty

Bulk Q.ty

Tube length (± 0.5)

A

B

C (± 0.1)

All dimensions are in mm.

100

2000

532

1.85

6.75

0.6

Figure 34. PowerSSO-12™ tape and reel shipment (suffix “TR”)

REEL DIMENSIONS

Base Q.ty

Bulk Q.ty

A (max)

B (min)

C (± 0.2)

F

G (+ 2 / -0)

N (min)

T (max)

2500

2500

330

1.5

13

20.2

12.4

60

18.4

TAPE DIMENSIONS

According to Electronic Industries Association

(EIA) Standard 481 rev. A, Feb. 1986

Tape width

Tape Hole Spacing

Component Spacing

Hole Diameter

Hole Diameter

Hole Position

Compartment Depth

Hole Spacing

W

P0 (± 0.1)

P

D (± 0.05)

D1 (min)

F (± 0.1)

K (max)

P1 (± 0.1)

1.5

5.5

4.5

2

12

4

8

1.5

All dimensions are in mm.

End

Top cover tape

No components

500mm min

Components No components

Empty components pockets saled with cover tape.

500mm min

User direction of feed

Start

29/31

Revision history VN5050AJ-E

Table 15.

Document revision history

Date Revision

24-Jan-2006

Jul-2006

06-Feb-2007

13-Sep-2007

7-Dec-2007

12-Feb-2008

23-Sep-2013

1

2

3

4

5

6

7

Changes

Initial release.

Minor updates.

Document reformatted.

Table 14: PowerSSO-12™ mechanical data

, X and Y values (slug

dimensions) updated.

Table 10: Current sense (8V<V

CC

<16V)

t

DSENSE2H

entry updated.

Figure 27: Maximum turn Off current versus inductance

and

Table 13: Thermal parameter

updated.

Document reformatted and restructured.

Contents and lists of tables and figures added.

Figure 2: Configuration diagram (top view)

updated: pins 1-6-7-12

left unconnected (N.C).

Table 4: Absolute maximum ratings

: updated E

MAX entries.

Table 10

: added dk1/k1, dk2/k2, dk3/k3,

Δ t

DSENSE2H

.

Added

Figure 6: Delay response time between rising edge of ouput current and rising edge of current sense (CS enabled)

.

Updated

Figure 8: I

OUT

/I

SENSE

Vs. I

OUT

(see Table 10. for details)

.

Added

Figure 9: Maximum current sense ratio drift vs load current

.

Table 12: Electrical transient requirements

: updated test level values

III and IV for test pulse 5b and notes.

Corrected

Figure 30: PowerSSO-12™ thermal impedance junction ambient single pulse

.

Figure 2: Configuration diagram (top view)

: added note.

Updated

Table 10: Current sense (8V<V

CC

<16V)

:

– changed t

DSENSE2H max value from 300 µs to 250µs.

– added I

OL parameter.

Updated

Section 4.1: PowerSSO-12™ thermal data

:

– changed

Figure 29: Rthj-amb Vs. PCB copper area in open box free air condition

.

– changed

Figure 30: PowerSSO-12™ thermal impedance junction ambient single pulse

.

– updated

Table 13: Thermal parameter

:

R1 value changed from 0.6 to 0.7 °C/W.

R3 value changed from 6.5 to 3 °C/W

R4 values changed from 10 /10 /9 to 8 /8 /7 °C/W.

C3 value changed from 0.022 to 0.0166 W.s/°C

Corrected typing error in

Table 10: Current sense (8V<V

CC

<16V)

:

changed I

OL test condition from V

IN

= 0V to V

IN

= 5V.

Updated Disclaimer.

30/31

VN5050AJ-E

Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice.

All ST products are sold pursuant to ST’s terms and conditions of sale.

Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.

UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED

WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED

WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS

OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

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SUPPORTING, ACTIVE IMPLANTED DEVICES OR SYSTEMS WITH PRODUCT FUNCTIONAL SAFETY REQUIREMENTS; (B)

AERONAUTIC APPLICATIONS; (C) AUTOMOTIVE APPLICATIONS OR ENVIRONMENTS, AND/OR (D) AEROSPACE APPLICATIONS

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EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR “AUTOMOTIVE, AUTOMOTIVE SAFETY OR MEDICAL” INDUSTRY

DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS. PRODUCTS FORMALLY ESCC, QML OR JAN QUALIFIED ARE

DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY.

Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST.

ST and the ST logo are trademarks or registered trademarks of ST in various countries.

Information in this document supersedes and replaces all information previously supplied.

The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.

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31/31