STMicroelectronics VN5016AJ-E Datasheet
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VN5016AJ-E
Single channel high side driver with analog current sense for automotive applications
Features
Max supply voltage
Operating voltage range
V
CC
V
CC
Max On-State resistance (per ch.) R
ON
Current limitation (typ) I
LIMH
Off state supply current I
S
41V
4.5 to 36V
16 m
65A
2 µA
■
■
■
Main features
– Inrush current active management by power limitation
– Very low stand-by current
– 3.0V CMOS compatible input
– Optimized electromagnetic emission
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/EC european directive
Diagnostic functions
– Proportional load current sense
– High current sense precision for wide range currents
– Current sense disable
– Thermal shutdown indication
– Very low current sense leakage
Protection
– Undervoltage shut-down
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss of V
CC
– Thermal shut down
– Reverse battery protection
– Electrostatic discharge protection
Table 1. Device summary
Package
PowerSSO-12
Application
■ All types of resistive, inductive and capacitive loads
Description
The VN5016AJ-E is a monolithic device made using STMicroelectronics VIPower M0-5 technology. It is intended for driving resistive or inductive loads with one side connected to ground. Active V
CC
pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). This device integrates an analog current sense which delivers a current proportional to the load current
(according to a known ratio) when CS_DIS is driven low or left open.
When CS_DIS is driven high, the CURRENT
SENSE pin is in a high impedance condition.
Output current limitation protects the device in overload condition. In case of long overload duration, the device limits the dissipated power to safe level up to thermal shut-down intervention.
Thermal shut-down with automatic restart allows the device to recover normal operation as soon as fault condition disappears.
Tube
VN5016AJ-E
PowerSSO-12
Order codes
Tape & Reel
VN5016AJTR-E
September 2013 Rev 8 1/32
www.st.com
32
1
2
Contents
Contents
3
4
5
6
VN5016AJ-E
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 22
3.1.1
3.1.2
Solution 1 : resistor in the ground line (RGND only) . . . . . . . . . . . . . . . 22
Solution 2 : diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . 23
3.2
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3
MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4
Maximum demagnetization energy (V
CC
= 13.5V) . . . . . . . . . . . . . . . . . . 24
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1
PowerSSO-12™ thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.1
ECOPACK
®
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.2
PowerSSO-12™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3
PowerSSO-12™ packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2/32
VN5016AJ-E
List of tables
List of tables
Table 2.
Table 3.
Table 4.
Table 5.
Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Suggested connections for unused and N.C. pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6.
Table 7.
Table 9.
Table 8.
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Switching (V
CC
=13V, T j
=25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 10.
Current sense (8V<V
CC
<16V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 11.
Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 12.
Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 13.
Thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 14.
PowerSSO-12™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 15.
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3/32
List of figures
List of figures
VN5016AJ-E
Figure 1.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2.
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3.
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4.
Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5.
Delay response time between rising edge of ouput current and rising edge of current sense
(CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 6.
IOUT/ISENSE Vs. IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7.
Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8.
Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9.
Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10.
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11.
Off state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12.
High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13.
Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 14.
Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 15.
Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 16.
Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 17.
On state resistance vs. T case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 18.
On state resistance vs. V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 19.
Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 20.
Turn - On voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 21.
I
LIMH
vs. T case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 22.
Turn - Off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 23.
CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 24.
CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 25.
CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 26.
Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 27.
Maximum turn Off current versus load inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 28.
PowerSSO-12™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 29.
Rthj-amb vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 25
Figure 30.
PowerSSO-12™ thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . 26
Figure 31.
Thermal fitting model of a single channel HSD in PowerSSO-12™ . . . . . . . . . . . . . . . . . 26
Figure 32.
PowerSSO-12™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 33.
PowerSSO-12™ tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 34.
PowerSSO-12™ tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4/32
VN5016AJ-E
1
Block diagram and pin description
Block diagram and pin description
Figure 1.
Block diagram
V
CC
GND
INPUT
V
CC
CLAMP
LOGIC
UNDERVOLTAGE
PwCLAMP
DRIVER
Pwr
LIM
OVERTEMP.
I
OUT
I
LIM
V
DSLIM
K
CS_DIS
OUTPUT
CURRENT
SENSE
Table 2.
Name
V
CC
OUTPUT
GND
INPUT
Pin function
Function
Battery connection.
Power output.
Ground connection. Must be reverse battery protected by an external diode/resistor network.
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state.
CURRENT
SENSE
CS_DIS
Analog current sense pin, delivers a current proportional to the load current.
Active high CMOS compatible pin, to disable the current sense pin.
5/32
Block diagram and pin description
Figure 2.
Configuration diagram (top view)
V
CC
GND
INPUT
CURRENT SENSE
CS_DIS
V
CC
1
2
3
4
5
6
12
11
10
9
8
7
TAB = V cc
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
VN5016AJ-E
Table 3.
Suggested connections for unused and N.C. pins
Connection / Pin Current Sense N.C.
Output Input
Floating
To ground
N.R.
(1)
Through 1K
resistor
X
X
X
N.R.
(1)
X
Through 10K
resistor
(1) Not recommended.
CS_DIS
X
Through 10K
resistor
6/32
VN5016AJ-E Electrical specifications
Figure 3.
Current and voltage conventions
V
CSD
V
IN
I
CSD
I
IN
V
CC
I
S
V
F
I
OUT
CS_DIS
OUTPUT
INPUT
CURRENT SENSE
GND
I
SENSE
V
SENSE
I
GND
V
OUT
V
CC
Note:
2.1
V
Fn
= V
OUTn
- V
CC
during reverse battery condition.
Absolute maximum ratings
Stressing the device above the ratings listed in the “Absolute maximum ratings” tables may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to the conditions in this section for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Table 4.
Symbol
Absolute maximum ratings
Parameter
V
CC
-V
CC
-I
GND
I
OUT
-I
OUT
I
IN
I
CSD
-I
CSENSE
DC supply voltage
Reverse DC supply voltage
DC reverse ground pin current
DC output current
Reverse DC output current
DC input current
DC current sense disable input current
DC reverse CS pin current
V
CSENSE
Current sense maximum voltage
E
MAX
Maximum switching energy
(L=0.75mH; R
L
=0
; V bat
=13.5V; T jstart
=150ºC;
I
OUT
= I limL
(Typ.) )
Value
41
0.3
200
Internally limited
30
-1 to 10
-1 to 10
200
V
CC
-41
+V
CC
304 mJ
Unit
V
V mA
A
A mA mA mA
V
V
7/32
Electrical specifications
Table 4.
Symbol
V
ESD
V
ESD
T j
T stg
Absolute maximum ratings (continued)
Parameter
Electrostatic discharge (Human Body Model: R=1.5K
C=100pF)
- INPUT
- CURRENT SENSE
- CS_DIS
- OUTPUT
- V
CC
Charge device model (CDM-AEC-Q100-011)
Junction operating temperature
Storage temperature
VN5016AJ-E
Value
4000
2000
4000
5000
5000
750
-40 to 150
-55 to 150
Unit
V
°C
°C
V
V
V
V
V
Table 5.
Symbol
Thermal data
Parameter
R thj-case
R thj-amb
Thermal resistance junction-case
Thermal resistance junction-ambient
Max value
0.5
Unit
°C/W
°C/W
8/32
VN5016AJ-E Electrical specifications
8V<V
CC
<36V; -40°C<T j
<150°C, unless otherwise specified.
.
Table 6.
Power section
Symbol Parameter Test conditions
V
V
CC
USD
V
USDhyst
Operating supply voltage
Undervoltage shutdown
Undervoltage Shut-down hysteresis
R
ON
V clamp
On state resistance
Clamp voltage
I
OUT
= 5A; T j
= 25°C
I
OUT
= 5A; T j
= 150°C
I
OUT
= 5A; V
CC
= 5V; T j
= 25°C
I
S
= 20mA
Off State; V
CC
=13V; T j
=25°C;
V
IN
=V
OUT
=V
SENSE
=V
CSD
=0V
I
S
Supply current
I
L(off)
Off state output current
On State; V
CC
=13V; V
IN
=5V;
I
OUT
=0A
V
IN
=V
OUT
=0V; V
CC
=13V;
T j
=25°C
V
IN
=V
OUT
=0V; V
CC
=13V;
T j
=125°C
V
F
Output - V
CC
diode voltage
(1) PowerMOS leakage included.
I
OUT
= 6A; T j
= 150°C
Min.
Typ.
Max.
Unit
4.5
13 36
3.5
4.5
V
V
0.5
41 46
16
32
20
52
V m
m
m
V
2
(1)
5
(1)
µA
1.5
3 mA
0 0.01
3
0 5
µA
0.7
V
Table 7.
Symbol
Switching (V
CC
=13V, T j
=25°C)
Parameter Test conditions
t d(on) t d(off)
Turn-On delay time
Turn-Off delay time
(dV
OUT
/dt) on
Turn-On voltage slope
(dV
OUT
/dt) off
Turn-Off voltage slope
W
ON
Switching energy losses during t won
R
L
= 2.6
(see
)
R
L
= 2.6
R
L
= 2.6
R
L
= 2.6
R
L
= 2.6
W
OFF
Switching energy losses during t woff
R
L
= 2.6
Min.
Typ.
Max.
Unit
See
See
35
50
µs
µs
V
µs
V
µs
1.1
mJ
0.8
mJ
9/32
Electrical specifications VN5016AJ-E
Table 8.
Symbol
V
IL
I
IL
V
IH
I
IH
V
I(hyst)
V
ICL
Logic input
Parameter
Input low level voltage
Low level input current
Input high level voltage
High level input current
Input hysteresis voltage
Input clamp voltage
Test conditions
V
IN
=0.9V
V
IN
=2.1V
I
IN
=1mA
I
IN
=-1mA
Min.
Typ.
Max.
Unit
0.9
1
2.1
0.25
5.5
-0.7
10
7
0.9
µA
V
V
V
V
V
µA
V
V
V
I
I
CSDL
CSDL
CSDH
CSDH
CS_DIS low level voltage
Low level CS_DIS current
CS_DIS high level voltage
High level CS_DIS current
V
CSD(hyst)
CS_DIS hysteresis voltage
V
CSD
=0.9V
V
CSD
=2.1V
1
2.1
0.25
10
µA
V
µA
V
V
CSCL
CS_DIS clamp voltage
I
CSD
=1mA
I
CSD
=-1mA
5.5
-0.7
7 V
V
Table 9.
Symbol
Protections and diagnostics
(1)
Parameter Test conditions Min.
Typ.
Max.
Unit
I limH
DC short circuit current
V
CC
=13V
5V<V
CC
<36V
46 65 91
91
A
A
V
T
I
T
T limL
TSD
T
R
RS
HYST
DEMAG
Short circuit current during thermal cycling
Shutdown temperature
Reset temperature
Thermal reset of
STATUS
Thermal hysteresis
(T
TSD
-T
R
)
Turn-Off output voltage clamp
V
CC
I
OUT
=13V T
R
=2A; V
IN
<T j
<T
TSD
150
T
RS
135
=0; L=6mH V
CC
24
175
+1 T
RS
7
-41 V
CC
+5
-46 V
200
CC
-52
A
°C
°C
°C
°C
V
V
ON
Output voltage drop limitation
I
OUT
=0.3A;
T j
= -40°C...+150°C
25
(1) To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles.
mV
10/32
VN5016AJ-E
Table 10.
Current sense (8V<V
CC
<16V)
Symbol Parameter Test conditions
K
0
K
1 dK
1
/K
1
(1)
Current sense ratio drift
K
2 dK
2
/K
2
(1)
Current sense ratio drift
K
3 dK
3
/K
3
(1)
Current sense ratio drift
I
SENSE0
I
OUT
/I
SENSE
I
OUT
/I
SENSE
I
OUT
/I
SENSE
I
OUT
/I
SENSE
Analog sense leakage current
I
OUT
=0.25A;
V
SENSE
=0.5V;V
CSD
=0V;
T j
= -40°C...150°C
I
OUT
=4A; V
SENSE
=0.5V;
V
CSD
=0V;
T j
= -40°C...150°C
I
OUT
=4A; V
SENSE
=0.5V;
V
CSD
=0V;
T j
= 25°C...150°C
I
OUT
=4A; V
SENSE
= 0.5V;
V
CSD
=0V;
T
J
=-40 °C to 150 °C
I
OUT
=10A; V
SENSE
=4V;
V
CSD
=0V;
T j
=-40°C...150°C
I
OUT
=10A; V
SENSE
=4V;
V
CSD
=0V;
T j
=25°C...150°C
I
OUT
=10A; V
SENSE
= 4V;
V
CSD
=0V;
T
J
=-40 °C to 150 °C
I
OUT
=25A; V
SENSE
=4V;
V
CSD
=0V;
T j
= -40°C...150°C
I
OUT
=25A; V
SENSE
=4V;
V
CSD
=0V;
T j
= 25°C...150°C
I
OUT
=25A; V
SENSE
= 4V;
V
CSD
=0V;
T
J
=-40 °C to 150 °C
I
OUT
=0A; V
SENSE
=0V;
V
CSD
=5V; V
IN
=0V;
T j
=-40°C...150°C
V
CSD
=0V; V
IN
=5V;
T j
=-40°C...150°C
I
OUT
=2A; V
SENSE
=0V;
V
CSD
=5V; V
IN
=5V;
T j
=-40°C...150°C
I
OL
Openload ON state current detection threshold
V
IN
= 5V, I
SENSE
= 5 µA
Electrical specifications
Min.
Typ.
Max.
Unit
2760 5010 7240
3510 4560 5690
3770 4560 5350
-8 +8 %
4180 4570 5060
4250 4570 4890
-4 +4 %
4360 4500 4700
4380 4500 4620
-3 +3 %
0
10
0
0
1
2
µA
µA
1 µA
45 mA
11/32
Electrical specifications VN5016AJ-E
Table 10.
Current sense (8V<V
CC
<16V) (continued)
Symbol Parameter Test conditions Min.
Typ.
Max.
Unit
V
I
V
SENSE
SENSEH
SENSEH
Max analog sense output voltage
Analog sense output voltage in overtemperature condition
Analog sense output current in overtemperature condition
I
OUT
V
V
CC
CC
=15A; V
=13V; R
=13V; V
CSD
=0V; 5
SENSE
SENSE
=3.9K
=5V
t t t
DSENSE1H
DSENSE1L
DSENSE2H
Delay response time from falling edge of
CS_DIS pin
Delay response time from rising edge of
CS_DIS pin
Delay response time from rising edge of
INPUT pin
V
SENSE
<4V, 1.5A<Iout<25A
I
SENSE
= 90% of I
SENSE max
(see
)
V
SENSE
<4V, 1.5A<Iout<25A
I
SENSE
= 10% of I
SENSE max
(see
)
V
SENSE
<4V, 1.5A<Iout<25A
I
SENSE
= 90% of I
SENSE max
(see
)
t
DSENSE2H
Delay response time between rising edge of output current and rising edge of current sense t
DSENSE2L
Delay response time from falling edge of
INPUT pin
V
SENSE
< 4V,
I
SENSE
= 90% of I
SENSEMAX,
I
OUT
= 90% of I
OUTMAX
I
OUTMAX
V
SENSE
<4V, 1.5A<Iout<25A
I
SENSE
=10% of I
SENSE max
(see
)
(1) Parameter guaranteed by design; it is not tested.
9
8
50
5
270
100
100
20
400
280
250
V
V mA
µs
µs
µs
µs
µs
12/32
VN5016AJ-E
Figure 4.
Current sense delay characteristics
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT t
DSENSE2H t
DSENSE1L
Electrical specifications
t
DSENSE1H t
DSENSE2L
Figure 5.
Delay response time between rising edge of ouput current and rising edge of current sense (CS enabled)
V
IN
t
DSENSE2H t
I
OUT
90% I
OUTMAX
I
OUTMAX t
I
SENSE I
SENSEMAX
90% I
SENSEMAX t
13/32
Electrical specifications
Figure 6.
I
OUT
/I
SENSE
Vs. I
OUT
for details)
I out
/ I sense
6000
max Tj = -40 °C to 150 °C
5500
5000
max Tj = 25 °C to 150 °C
4500
min Tj = 25 °C to 150 °C
4000
3500
min Tj = -40 °C to 150 °C
3000
4 8
typical value
12
I
OUT
(A)
16 20 24
VN5016AJ-E
Note:
Figure 7.
Maximum current sense ratio drift vs load current dk/k(%)
15
10
5
0
-5
-10
-15
4 7 10 13 16
I
OUT
(A)
Parameter guaranteed by design; it is not tested.
19 22 25
14/32
VN5016AJ-E
Figure 8.
Switching characteristics
V
OUT t
Won
80% dV
OUT
/dt
(on) t r
10%
INPUT t d(on) t d(off) t
Woff
90% t f
Electrical specifications
dV
OUT
/dt
(off) t t
Figure 9.
Output voltage drop limitation
V cc
-V out
T j
=150 o
C
T j
=25 o
C
T j
=-40 o
C
V on
V on
/R on(T)
I out
15/32
Electrical specifications VN5016AJ-E
Table 11.
Truth table
Conditions
Normal operation
Overtemperature
Undervoltage
Short circuit to GND
(R sc
10 m)
Short circuit to V
CC
Input
L
H
L
L
H
L
H
H
L
H
L
H
Output
H
H
L
L
L
L
L
L
L
L
L
H
Sense (V
CSD
=0V)
(1)
0
Nominal
0
V
SENSEH
0
0
0
0 if T j
< T
TSD
V
SENSEH
if T j
> T
TSD
0
< Nominal
0 Negative output voltage clamp
(1) If the V
CSD
is high, the SENSE output is at a high impedance, its potential depends on leakage currents and external circuit.
16/32
VN5016AJ-E Electrical specifications
Table 12.
Electrical transient requirements
ISO 7637-2:
2004(E)
Test pulse
1
2a
3a
3b
4
5b
(2)
Test levels
(1)
III
-75V
+37V
-100V
+75V
-6V
+65V
IV
-100V
+50V
-150V
+100V
-7V
+87V
Number of pulses or test times
5000 pulses
5000 pulses
1h
1h
1 pulse
1 pulse
Burst cycle/pulse repetition time
0.5 s
0.2 s
90 ms
90 ms
5 s
5 s
100 ms
100 ms
Delays and
Impedance
2 ms, 10
50 µs, 2
0.1 µs, 50
0.1 µs, 50
100 ms, 0.01
400 ms, 2
ISO 7637-2:
2004(E)
Test pulse
1
2a
3a
III
C
C
C
Test level results
(1)
IV
3b C C
4
5b
(2)
C C
C
(1) The above test levels must be considered referred to V
CC
= 13.5V except for pulse 5b.
(2) Valid in case of external load dump clamp: 40V maximum referred to ground.
C
C
C
C
Class
C
E
Contents
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
17/32
Electrical specifications
Figure 10. Waveforms
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
NORMAL OPERATION
V
CC
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
V
USD
UNDERVOLTAGE
V
USDhyst
SHORT TO V
CC
INPUT
CS_DIS
LOAD VOLTAGE
LOAD CURRENT
SENSE CURRENT
<Nominal
<Nominal
VN5016AJ-E
OVERLOAD OPERATION
T j
INPUT
CS_DIS
LOAD CURRENT
T
R
T
TSD
T
RS
SENSE CURRENT current limitation power limitation thermal cycling
SHORTED LOAD
I
I
LIMH
LIML
V
SENSEH
NORMAL LOAD
18/32
VN5016AJ-E Electrical specifications
Figure 11. Off state output current
1.25
1
0.75
Iloff (uA)
2
1.75
1.5
Off State
Vcc=13V
Vin=Vout=0V
0.5
0.25
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Figure 13. Input clamp voltage
6.25
6
5.75
Vicl (V)
7
6.75
6.5
Iin=1mA
5.5
5.25
5
-50 -25 0 25 50 75
Tc (°C)
Figure 15. Input high level
100 125 150 175
Vih (V)
4
3.5
3
2.5
2
1.5
1
0.5
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Figure 12. High level input current
Iih (uA)
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
Vin=2.1V
0
-50 -25 0 25 50 75
Tc (°C)
Figure 14. Input low level
100 125 150 175
2.5
2
1.5
Vil (V)
4
3.5
3
1
0.5
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Figure 16. Input hysteresis voltage
0.8
0.7
0.6
0.5
0.4
Vhyst (V)
1
0.9
0.3
0.2
0.1
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
19/32
Electrical specifications
Figure 17. On state resistance vs. T case
25
20
15
10
5
0
-50
40
35
30
Ron (mOhm)
50
45
Iout=5A
Vcc=13V
-25 0 25 50 75
Tc (°C)
100 125 150 175
Figure 19. Undervoltage shutdown
10
8
6
4
2
Vusd (V)
16
14
12
0
-50 -25 0 25 50 75
Tc (°C)
Figure 21. I
LIMH
vs. T case
100 125 150 175
Ilimh (A)
80
65
60
55
75
70
50
45
40
-50 -25
Vcc=13V
0 25 50 75
Tc (°C)
100 125 150 175
VN5016AJ-E
Figure 18. On state resistance vs. V
CC
Ron (mOhm)
40
35
30
25
Tc= 150°C
Tc= 125°C
20
15
Tc= 25°C
10
5
Tc= -40°Cv
0
0 5 10 15 20
Vcc (V)
25 30
Figure 20. Turn - On voltage slope
35 40 dVout/dt(on) (V/ms)
1000
900
800
700
Vcc=13V
RI=2.6Ohm
600
500
400
300
200
100
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Figure 22. Turn - Off voltage slope
(dVout/dt)off (V/ms)
1000
900
800
Vcc=13V
Rl=2.6Ohm
700
600
500
400
300
200
100
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
20/32
VN5016AJ-E
Figure 23. CS_DIS high level voltage
Vcsdh (V)
4
3.5
3
2.5
2
1.5
1
0.5
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Figure 25. CS_DIS low level voltage
Vcsdl (V)
4
3.5
3
2.5
2
1.5
1
0.5
0
-50 -25 0 25 50 75
Tc (°C)
100 125 150 175
Electrical specifications
Figure 24. CS_DIS clamp voltage
Vcsdcl (V)
8
7.5
7
6.5
6
5.5
5
4.5
4
-50 -25
Icsd=1mA
0 25 50 75
Tc (°C)
100 125 150 175
21/32
Application Information VN5016AJ-E
Figure 26. Application schematic
+5V
µC
V
CC
R prot
CS_DIS
R
R prot prot
C ext
R
SENSE
INPUT
CURRENT SENSE
GND
V
GND
R
GND
D
GND
OUTPUT
D ld
3.1
3.1.1
GND protection network against reverse battery
Solution 1 : resistor in the ground line (R
GND
only)
This can be used with any type of load.
The following is an indication on how to dimension the R
GND resistor.
1.
R
GND
600mV / (I
S(on)max
).
2. R
GND
V
CC
) / (-I
GND
) where -I
GND
is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet.
Power Dissipation in R
GND
(when V
CC
<0: during reverse battery situations) is:
P
D
= (-V
CC
)
2
/R
GND
This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where I
S(on)max
becomes the sum of the maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the
R
GND will produce a shift (I
S(on)max
* R
GND
) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same R
GND
.
22/32
VN5016AJ-E
3.1.2
Application Information
If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize Solution 2 (see below).
Solution 2 : diode (D
GND
) in the ground line
A resistor (R
GND
=1k
should be inserted in parallel to D inductive load.
GND
if the device drives an
This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift (
600mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network.
3.3
D ld
is necessary (
Voltage Transient Suppressor) if the load dump peak voltage exceeds the
V
CC
max DC rating. The same applies if the device is subject to transients on the V
CC
line that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
MCU I/Os protection
If a ground protection network is used and negative transient are present on the V
CC
line, the control pins will be pulled negative. ST suggests to insert a resistor (R prot
) in line to prevent the
µ
C I/Os pins to latch-up.
The value of these resistors is a compromise between the leakage current of
µ
C and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
µ
C
I/Os.
-V
CCpeak
/I latchup
R prot
(V
OHµC
-V
IH
-V
GND
) / I
IHmax
Calculation example:
For V
CCpeak
= - 100V and I latchup
20mA; V
OHµC
4.5V
5k
R prot
180k.
Recommended values: R prot
=10k
C
EXT
=10nF
.
23/32
Application Information
3.4 Maximum demagnetization energy (V
CC
= 13.5V)
Figure 27.
Maximum turn Off current versus load inductance
100
VN5016AJ-E
B
A
C
10
1
0,1 1 L (mH) 10 100
A: T jstart
= 150°C single pulse
B: T jstart
= 100°C repetitive pulse
C: T jstart
= 125°C repetitive pulse
V
IN
, I
L
Demagnetization
Demagnetization
Demagnetization
Note:
t
Values are generated with R
L
=0
In case of repetitive pulses, T jstart
(at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C.
24/32
VN5016AJ-E
4 Package and PCB thermal data
Package and PCB thermal data
Figure 28. PowerSSO-12
™ PC board
Note: Layout condition of R th
and Z th
measurements (PCB: Double layer, Thermal Vias, FR4 area= 77mm x 86mm,PCB thickness=1.6mm, Cu thickness=70µm (front and back side),
Copper areas: from minimum pad lay-out to 8cm
2
).
Figure 29. R thj-amb
vs. PCB copper area in open box free air condition
RTHj_amb(°C/ W)
65
60
55
50
45
40
35
30
0 2 4 6
PCB Cu heatsink area (cm^ 2)
8 10
25/32
Package and PCB thermal data VN5016AJ-E
Figure 30. PowerSSO-12
™ thermal impedance junction ambient single pulse
100
2 cm
2
Footprint
8 cm
2
10
1
0,1
0,0001 0,001 0,01 0,1
Time (s)
1 10 100 1000
Equation 1: pulse calculation formula
Z
TH
=
R
TH where
= t
P
/T
THtp
1
–
Figure 31.
Thermal fitting model of a single channel HSD in PowerSSO-12
™
(a)
26/32
(a )The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
VN5016AJ-E
Table 13.
Thermal parameter
Area/island (cm
2
)
R1 (°C/W)
R2 (°C/W)
R3 (°C/W)
R4 (°C/W)
R5 (°C/W)
R6 (°C/W)
C1 (W.s/°C)
C2 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
Footprint
0.0001
0.002
0.05
0.2
0.27
3
0.1
0.2
4
8
22
26
Package and PCB thermal data
2
0.1
0.8
6
8
15
20
8
0.1
1
9
7
10
15
27/32
Package information VN5016AJ-E
5.1 ECOPACK
®
packages
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
5.2
PowerSSO-12™ package information
Figure 32.
PowerSSO-12™ package dimensions
28/32
VN5016AJ-E
Table 14.
PowerSSO-12™ mechanical data
Symbol
k
X
Y ddd e
H h
L
B
C
D
E
A
A1
A2
5.800
0.250
0.400
0°
1.900
3.600
Min.
1.250
0.000
1.100
0.230
0.190
4.800
3.800
Millimeters
Typ.
0.800
Package information
6.200
0.500
1.270
8°
2.500
4.200
0.100
Max.
1.620
0.100
1.650
0.410
0.250
5.000
4.000
29/32
Package information
5.3
PowerSSO-12™ packing information
Figure 33. PowerSSO-12
™ tube shipment (no suffix)
B
A
C
VN5016AJ-E
Base Q.ty
Bulk Q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
All dimensions are in mm.
100
2000
532
1.85
6.75
0.6
Figure 34. PowerSSO-12
™ tape and reel shipment (suffix “TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
2500
2500
330
1.5
13
20.2
12.4
60
18.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
W
P0 (± 0.1)
P
D (± 0.05)
D1 (min)
F (± 0.1)
K (max)
P1 (± 0.1)
1.5
5.5
4.5
2
12
4
8
1.5
All dimensions are in mm.
End
Top cover tape
No components
500mm min
Components No components
Empty components pockets saled with cover tape.
500mm min
User direction of feed
Start
30/32
VN5016AJ-E Revision history
Table 15.
Document revision history
Date Revision
30-Oct-2004
15-Jan-2005
11-May-2006
02-Feb-2007
02-Jul-2007
09-Jan-2007
12-Feb-2008
25-Sep-2013
1
2
3
4
5
6
7
8
Changes
Initial release.
Minor text changes.
Document changed from Advance Data to maturity.
Changes minor formatting.
Figure 27: Maximum turn Off current versus load inductance
Added new disclaimer.
: updated E
MAX
entries.
: added dk1/k1, dk2/k2, dk3/k3,
t
DSENSE2H
.
: updated test level values III and IV for test pulse 5b and
notes.
Section 3.4: Maximum demagnetization energy (V
.
Figure 31: Thermal fitting model of a single channel HSD in
:
– Changed dK
3
/K
3 values from ± 2 to ± 3 %.
– Added I
OL parameter.
– Changed
t
DSENSE2H max value from 120 to 280 µs.
Figure 7: Maximum current sense ratio drift vs load current
with new dK/K values.
Section 4.1: PowerSSO-12™ thermal data
– Changed
Figure 29: Rthj-amb vs. PCB copper area in open box free air condition
– Changed
Figure 30: PowerSSO-12™ thermal impedance junction ambient single pulse
.
– Updated
R3 value changed from 7 to 4 °C/W.
R4 values changed from 10 /10 /10 to 8 /8 /7 °C/W.
changed I
OL test condition from V
IN
= 0V to V
IN
= 5V.
Updated disclaimer.
31/32
VN5016AJ-E
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