STMicroelectronics ST200-TOOLSET Reference Manual
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広告
ST200 VLIW
Series
ST220 Core and
Instruction Set
Architecture
Manual
Last updated 12 September 2007
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ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Contents
Preface xi
1 Introduction
1.1
VLIW overview
1.2
ST220 overview
1.3
Document overview
2 Cluster 19
2.1
Integer units
2.2
Multiply units
2.3
Load/store unit (LSU)
20
21
21
13
14
14
16
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3 Architectural state 25
3.1
Program counter (PC)
3.2
Register file
3.3
Program status word (PSW)
25
25
26
Supported method for changing the PSW 27
3.4
Branch register file
3.5
Control registers
28
28
4 Execution pipeline and latencies
4.1
Execution pipeline
4.2
Operation latencies
4.3
Additional notes
29
29
30
30
5 Traps: exceptions and interrupts 31
5.1
Trap mechanism
5.2
Exception handling
31
32
5.3
Saved execution state 32
5.4
Interrupts 34
5.5
Debug interrupt handling
5.6
Exception types and priorities
Illegal instruction definition
5.7
Speculative load considerations
34
34
36
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6 Memory access protection units 39
6.1
Description 39
6.2
Operation 40
Example use of overlapping regions
6.3
Protection unit registers
Speculative load returns zero field
Operation when protection unit is disabled
42
7 Memory subsystem 47
7.1
Memory subsystem
7.2
I-side memory subsystem
7.3
D-side memory subsystem
7.4
Core memory controller (CMC) 54
48
48
50
v
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7.5
Additional notes
Forcing writes to external memory
Coherency between I-side and D-side
Changing memory to uncacheable
Cached data in uncached region
8 Streaming data interface (SDI) 57
8.1
Overview 57
8.2
Functional description 58
8.3
Communication channel
59
8.4
Registers 59
8.5
Exceptions, interrupts, reset and restart 62
9 Control registers 65
9.1
Access operations 65
9.2
Exceptions 65
9.3
Control register addresses 66
54
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10 Timers 71
10.1
Operation 72
10.2
Timer interrupts
10.3
Programming the timer
74
74
11 Peripheral addresses
11.1
Peripheral addresses
Interrupt controller & timer registers
12 Interrupt controller 79
12.1
Architecture 79
12.2
Operation 80
12.3
Interrupt registers
80
Interrupt mask register (INTMASK)
Interrupt test register (INTTEST)
12.4
Programming 83
75
75
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13 Debugging support 85
13.1
Overview 85
13.2
Core 86
13.3
Debug support unit
88
13.4
Debug ROM
13.5
Host debug interface
91
95
14 Performance monitoring 99
14.1
Events 99
14.2
Access to registers 100
14.3
Control register (PM_CR)
14.4
Event counters (PM_CNTi)
101
102
14.5
Clock counter (PM_PCLK)
14.6
Recording events
102
102
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15 Execution model 105
15.1
Introduction 105
15.2
Bundle fetch, decode, and execute 106
15.3
Functions 108
16 Specification notation 109
16.1
Overview 109
16.2
Variables and types 110
16.3
Expressions 112
16.4
Statements 118
16.5
Architectural state 122
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16.6
Memory and control registers
17 Instruction set 135
17.1
Introduction 135
17.2
Bundle encoding 135
17.3
Operation specifications
17.4
Example operations
137
139
17.5
Macros 141
17.6
Operations 141
124
A Instruction encoding
A.1
Reserved bits
A.2
Fields
A.3
Formats
A.4
Opcodes
Index
313
313
313
314
316
325
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Preface
This document is part of the ST200 documentation suite detailed below. Comments on this or other manuals in the ST200 documentation suite should be made by contacting your local STMicroelectronics Limited sales office or distributor.
ST200 document identification and control
Each book in the ST200 documentation suite carries a unique ADCS identifier in the form:
ADCS nnnnnnnx
Where, nnnnnnn is the document number and x is the revision.
Whenever making comments on a ST200 document the complete identification
ADCS nnnnnnnx should be quoted.
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ST200 documentation suite
The ST200 documentation suite comprises the following volumes:
ST220 Core and Instruction Set Architecture Manual (ADCS 7395369)
This manual describes the architecture and instruction set of the ST220 implementation.
ST200 User Manual (ADCS 8063762)
This manual describes the ST200 Micro Toolset and provides an introduction to
OS21. It covers the various cross tools and libraries that are provided in the toolset, the target platform libraries. Information is also given on how to build the open source packages that provide the compiler tools, base run-time libraries and debug tools and how to set up an ST Micro Connect.
ST200 Compiler Manual (ADCS 7508723)
This manual describes the software provided as part of the ST200 tools. It supports the development of ST200 applications for embedded systems. Applications can be developed in either a stand-alone environment, or under the OS21 real-time operating system.
ST200 Runtime Architecture Manual (ADCS 7521848)
This manual describes the common software conventions for the ST200 processor runtime architecture.
OS21 User Manual (ADCS 7358306)
This manual describes the royalty free, light weight, OS21 multitasking operating system.
OS21 for ST200 User Manual (ADCS 7410372)
This manual describes the use of OS21 on ST200 platforms. It describes how specific ST200 facilities are exploited by the OS21 API. It also describes the OS21 board support packages for ST200 platforms.
ST200 ELF Specification (ADCS 7932400)
This document describes the use of the ELF file format for the ST200 processor.
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Introduction
The 32-bit ST220 is a member of the ST200 family of cores.
This family of embedded processors use a scalable technology that allows variation in instruction issue width, the number and capabilities of functional units and register files, and the instruction set.
The ST200 family includes the following features:
•
Parallel execution units, including multiple integer ALUs and multipliers.
•
Architectural support for data prefetch.
•
Predicated execution through select operations.
•
Efficient branch architecture with multiple condition registers.
•
Encoding of immediate operands up to 32 bits.
•
Support for register file and functional unit clustering.
•
Support for user/supervisor modes and memory protection.
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ST220 Core and Instruction Set Architecture Manual
14 VLIW overview
VLIW (very long instruction word) processors use a technique where instruction level parallelism is explicitly exposed to the compiler which must schedule operations to account for the operation latency.
RISC-like operations (syllables) are grouped into bundles (wide words). The operations in a bundle are issued simultaneously. In the ST200 family operations also complete simultaneously. While the delay between issue and completion is the same for all operations, some results are available for bypassing to subsequent
A hardware implementation of a VLIW is significantly simpler than a corresponding multiple issue superscaler CPU. This is due principally to the simplification of the operation grouping and scheduling hardware, all this complexity is moved to the instruction scheduling system (compiler and assembler) in the software toolchain.
The ST220 is a single cluster member of the ST200 family (see
Clustering is a technique in which functional units and registers are tightly coupled in groups called, clusters . Multiple clusters can be instantiated in a processor with a single program counter controlling execution. To date no ST200 varient contains more than one cluster. No further discussion is made in this document of multiple clusters.
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ST220 overview
ST220 Core
IPU
Interrupt
Peripherals
Timers
Interrupt
Controller
Taplink
Debug
Support Unit
Exception Controller DPU
STBus
ICache
I-Side Memory
Subsystem
Cluster
Data
Cache
Write
Buffer
Prefetch
Buffer
D-Side Memory
Subsystem
CMC
Control
Registers
4 x SDI
SDI Ports
Figure 1: ST220 processor diagram
STBus
15
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16 Document overview
This manual describes the architecture and instruction set of the ST220 implementation. This section gives an outline of the following document.
The processor is made up of a number of functional units described in Chapter 2:
Cluster which operate on data stored in the register files (
Chapter 3: Architectural state
). These functional units are pipelined and subject to explicit observable
latencies ( Chapter 4: Execution pipeline and latencies
).
The handling of exceptions and interrupts are detailed in
Chapter 5: Traps: exceptions and interrupts .
units for instruction and data accesses ( Chapter 6: Memory access protection units ).
The ST220 has 4 SDI ports (
Chapter 8: Streaming data interface (SDI)
) which allow it to communicate rapidly with other devices and avoid cache pollution when processing large amounts of data.
Control of the devices is performed using the memory mapped control registers defined within the relevant chapters. The address of the control registers and PSW
are detailed in Chapter 9: Control registers
.
The peripheral register addresses on the ST220 are detailed in
Peripheral addresses on page 75
.
A number of peripheral devices are also provided, including timers ( Chapter 10:
), interrupt control ( Chapter 12: Interrupt controller
) and debug support
( Chapter 13: Debugging support
).
The execution model is described in
Chapter 15: Execution model on page 105 . The
execution of bundles is described in
Section 15.2: Bundle fetch, decode, and execute on page 106
, including the behavior of the machine when exceptions or interrupts are encountered.
describes the details of each operation, including the semantics. The instruction set includes details of the instruction set encoding, syntax and semantics. The encoding of bundles is defined in
Section 17.2: Bundle encoding on page 135 .
The behavior of operations is specified using the notational language defined in
through
. The descriptions clearly identify where
architectural state is updated and the latency of the operands.
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Document overview
A simple model of memory and control registers defined in Section 16.6.2
and
is used when specifying the load and store operations.
17
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Cluster
The ST220 cluster consists of the functional units and the two register files; the branch registers and general purpose registers (for register files, refer to
Architectural state on page 25 ). The cluster is the core of the processor but does not
include the instruction fetch mechanism, caches or control registers.
This chapter describes the functional units of the ST220 cluster including 4 integer
units, 2 multiply units, a load store unit and a branch unit (refer to Figure 2
).
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20 Integer units
Mul Mul
I-Side
Memory
Subsystem
128 bit wide
Word
Instruction
Buffer
Register
File
(64 registers
8 read
4 write)
Load
Store
Unit
(LSU)
D-Side
Memory
Subsystem
Control
Registers
I-Side
Memory
Subsystem
PC and Branch
Unit
Branch
Register File
IU IU IU IU
Exception
Control
Debug
Support Unit
Figure 2: ST220 cluster
The ST220 has four identical integer units. Each integer unit is capable of executing one operation per cycle. The results of the integer units can be used as operands of the next bundle. This is equivalent to a pipeline depth of one cycle.
Each operation can take up to three operands in the form of two 32-bit values and a single conditional bit. The IU then executes the appropriate operation and produces up to two results in the form of a 32-bit value and a 1-bit conditional value. The
integer operations supported are detailed in the Chapter 17: Instruction set on page 135 .
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Multiply units 21
The ST220 has two identical multiply units. Each multiply unit is pipelined with a depth of three cycles, executing an operation every cycle.
Each multiply units takes two 32-bit operands and produces a single 32-bit result.
The multiply operations supported are detailed in the
Chapter 17: Instruction set on page 135 .
2.3 Load/store unit (LSU)
The ST220 has a single load store unit. The load store unit is pipelined with a depth of three cycles, executing an operation every cycle.
The load store can take up to three 32-bit operands and may produce a single 32-bit result depending on the operation. The load store operations supported are detailed
in the Chapter 17: Instruction set on page 135 .
Memory access protection is implemented by the DPU (data protection unit), this is part of the memory sub-system. The DPU also controls the cache behavior of data accesses,
Chapter 6: Memory access protection units on page 39
.
Uncached accesses or accesses which miss the data cache cause the load store unit to stall the pipeline to ensure correct operation.
2.3.1 Memory access
The ST220 addresses the external memory system via a single address space.
Peripheral devices and control registers are also mapped into the address space.
All cacheable memory transactions are made via the data cache. The data cache then decides if it needs to go to external memory to satisfy the request.
Note: Cacheable memory transactions that miss are written to the write buffer not the data cache.
Uncached accesses are performed directly on the memory system (refer to
Section 7.3.3: Uncached load and stores on page 51
).
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22 Load/store unit (LSU)
2.3.2 Addressing modes
The ST220 supports one addressing mode – the effective address is an immediate
(constant) plus a register.
2.3.3 Alignment
1 All load and store instructions work on data stored on the "natural alignment" of the data type; that is, words on word boundaries, half-word on half word boundaries.
2 Load and store operations with misaligned addresses raise an exception which makes possible the implementation of misaligned loads by trap handlers.
3 For a byte or half-word load , the data from memory is loaded into the least significant part of a register and is either sign-extended or zero extended according to the instruction defintion.
4 For a byte or half-word store , the data stored from the least significant part of a register.
2.3.4 Control registers
The LSU maps a part of the address space that is devoted to control registers (see the Control Registers chapter for details). The LSU control register block intercepts loads and stores to this area of memory so that it can process the operation. No access to the data cache is made for control register operations. Transactions are made across the 32-bit control register bus to those control registers that live outside the LSU.
2.3.5 Cache purging
Cache purging (flush and invalidate) operations are provided on the ST220.
They allow for purging lines and sets from the data cache, and invalidating the entire instruction cache.
2.3.6 Dismissible loads
Dismissible loads are used to support software load speculation. This allows the compiler to schedule a load in advance of a condition that predicates its use.
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Load/store unit (LSU) 23
Dismissible loads are required to return the same value as a normal load if such an operation can be executed without causing an exception. Otherwise dismissible loads return zero.
In the event that misaligned accesses are supported through a software trap handler, the ST220 may be configured to trap non-aligned dismissible loads , see the
Chapter 5: Traps: exceptions and interrupts on page 31
. The data protection unit can be configured to return zero for dismissible loads in cases where they can be executed without exception; this is to support peripherals which have destructive read behavior.
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Architectural state
This chapter describes the architectural state of the ST220 core.
3.1 Program counter (PC)
The PC contains a 32-bit byte address pointing to the beginning of the current bundle in memory.
The two LSBs of the PC are always zero.
The general purpose register file contains 64 words of 32 bits, R 0 ... R 63.
Reading register zero, R 0, always returns the value zero. Writing values to R 0, has no effect on the processor state.
3.2.1 Link register
Register 63, R 63, is the architectural link register used by the call and return mechanism. R 63 is updated by explicit register writes and the call operation. Some restrictions apply to accessing the link register, see
Section 4.3.1: Restrictions on link register on page 30 .
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3.3 Program status word (PSW)
The program status word (
PSW
) contains control information that affects the operation of the ST220 processor.
3.3.1 Bit fields
The PSW contains the following bit fields:
USER _ MODE
Reserved
Reserved
DEBUG _ MODE
Reserved
Name
INT _ ENABLE
Reserved
Reserved
SPECLOAD _ MALIGNTRAP _ EN
SPECLOAD _ DPUTRAP _ EN
DPU _ ENABLE
IPU _ ENABLE
DBREAK _ ENABLE
IBREAK _ ENABLE
Bit(s)
Access
(U/S)
RO/RW
Reset Comment
0
1
2
3
4
5
8
9
6
7
RO/RW
RO/RO
RO/RO
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
10
11
12
RO/RO
RO/RO
RO/RW
[31:13] RO/RO
0x0
0x0
0x0
0x0
Table 1: PSW bit fields
When 1 the core is in user mode, otherwise supervisor mode.
When 1 external interrupts are enabled.
Reserved
Reserved
When 1 enables exceptions on speculative load misalignment errors.
When 1 exceptions on speculative load
DPU traps are enabled.
When 1 the DPU is enabled.
When 1 the IPU is enabled.
When 1 data breakpoints are enabled.
When 1 instruction breakpoints are enabled.
Reserved
Reserved
When 1 the core is in debug mode.
Reserved
Access to bits in the control register is restricted (read only or read write) dependant on the value of
USER
_
MODE
at the time of access.
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Program status word (PSW) 27
3.3.2 USER_MODE
The USER _ MODE bit indicates whether the machine is in user mode or supervisor mode. When in user mode, the processor has restricted access:
•
The memory access protection units (see
Chapter 6: Memory access protection units on page 39 ) define the level of access to memory in both
user and supervisor modes.
•
In user mode there is limited access to control registers (see
Chapter 9: Control registers on page 65 ).
•
Certain instructions can not be executed in user
).
3.3.3 PSW Access
The PSW
can be accessed as a control register, Section 3.5: Control registers on page 28
.
3.3.4 Supported method for changing the PSW
To update the
PSW correctly the following method, using the rfi operation, is recommended. The required status word should be stored into the
SAVED
_
PSW
and the address of the code to be executed directly after the change should be stored in the
SAVED
_
PC
. Then executing an rfi atomically copies the
SAVED
_
PSW
into the
PSW and the
SAVED
_
PC
into the
PC
. At least four bundles are required to ensure that the changes to
SAVED
_
PC
and
SAVED
_
PSW
take effect before the rfi is executed.
Example : Procedure to write the
PSW
, (in ST220 assembler code),
_sys_set_psw:
stw SAVED_PC[$r0.0] = $r0.63;; // Return address
stw SAVED_PSW[$r0.0] = $r0.4;; // New value
nop ;;
nop ;;
nop ;;
nop ;;
rfi ;;
Note: Interrupts must be disabled during this sequence.
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28 Branch register file
The branch register file contains 8 single bit branch registers,
B
0 ... B
7 .
Additional architectural state is held in a number of memory mapped control
registers, Chapter 9: Control registers on page 65 . These registers include support
for interrupts and exceptions, and memory protection.
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Execution pipeline and latencies
This chapter describes the architecturally visible pipeline and operation latencies.
The ST220 uses a pipelined execution scheme. This pipeline is architecturally visible in a number of areas:
•
Operation latencies
•
Bypassing
•
Usage restrictions
The execution pipeline is three cycles long. It comprises of three stage E1, E2 and
E3. All operations begin in E1. Operands are read or bypassed to an operation at the start of E1. All results are written at the end of E3.
This execution pipeline allows arithmetic and load / store operations to execute for up to three cycles. The results of operations which complete earlier than E3 are made available for bypassing as operands to subsequent operations, though strictly operations do not complete until the end of the E3 stage. This is when the architectural state is updated.
The pipeline is designed to efficiently implement the serial execution of the code (see
Chapter 15: Execution model on page 105
).
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30 Operation latencies
ST220 operations begin in E1 cycle and complete in either E1, E2 or E3. The time taken for an operation to produce a result is called the operation latency. For simple operations like add and subtract the latency is a single cycle. For operations like multiply and load the latency is three cycles.
Note: Operational latencies may vary between different members of the ST200 processor family.
4.3.1 Restrictions on link register
As a performance optimization a speculative link register ( SLR ) has been added which is a copy of possible future updates to R 63. In the implementation this register is updated earlier in the pipeline than R 63. SLR is used as the source for register indirect branch operations.
It is possible to observe that SLR is not a true copy of R 63. This can only occurs in the following cases;
•
Register indirect call and goto operations. These require R 63 to be stable.
Solution; R 63 must not be modified in the three bundles preceding one of these operations.
•
The taking of an interrupt or exception just prior to an update of R 63 but after
SLR has been changed speculatively. Solution; All interrupt and exception handlers must explicitly write R 63 prior to the execution of an rfi , icall or igoto .
This requirement can easily be met with a mov operation from R 63 to R 63 in one of the first bundles of the trap handler.
A number of operations cannot target R 63 for efficiency reasons. These include
multiply operations, byte and half word load operations (see Chapter 17: Instruction set on page 135
).
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Traps: exceptions and interrupts
In the ST220 architecture, exceptions and interrupts are jointly termed traps. This chapter describes the trap mechanism.
The ST220 defines two types of traps:
•
External asynchronous traps (interrupts).
•
Internal synchronous traps (exceptions resulting from operation execution).
A trap point is the point in the program execution where a trap occurs. All bundles executed before the trap point will have completed updating architectural state; and no architectural state will have been undated by subsequent bundles. For an exception, the trap point is the (start of the) bundle which caused the exception. For an interrupt, the trap point is (the start of) the bundle whose execution has been interrupted. Typically this is a bundle that had been executed shortly after the interrupt was raised or enabled.
The flow diagram,
, defines when a trap is taken. The aim
of this chapter is to define the steps that are carried out when a trap is to be taken.
In effect, taking a trap can be viewed as executing an operation which branches to the required handler, with a number of side effects. The side effects are defined by the statements below. An external interrupt is treated as an EXTERN _ INT exception, with only debug interrupts being handled differently.
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32 Exception handling
At the trap point, the ST220 transfers execution to the trap handler, starting at the address held in the
HANDLER
_
PC
control register, and saves the execution state as detailed in
Table 5.3: Saved execution state
. All operations issued before the trapping bundle are allowed to complete. All operations issued after and including the trapping bundle are discarded. The architectural state, with the exception of saved execution state, is exactly that at the trap point. Hence ST220 interrupts and exceptions can be considered precise.
Traps are handled strictly (in order), and indivisibly with respect to the bundle stream.
Due to the fact that there may be more than one operation executing at once, it is possible to have more than one exception thrown in a bundle. However, only the highest priority exception is passed to the handler.
5.3 Saved execution state
Directly following a trap the saved execution state defines the reason for the trap and the precise trap point in the execution flow of the processor. Control registers are used to store these values for use by the handler routine.
Taking an exception can be summarized as:
NEXT_PC
←
// Branch to the exception handler
EXCEPT_CAUSE
←
// Store information
EXCEPT_ADDR
←
// for the handler
SAVED_PSW
←
// Save the PSW and PC
SAVED_PC
←
PSW[USER_MODE]
←
// Enter supervisor mode
PSW[INT_ENABLE]
←
// Disable interrupts
PSW[IBREAK_ENABLE]
←
// Disable instruction breakpoints
PSW[DBREAK_ENABLE]
←
// Disable data breakpoints
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Saved execution state 33
Where the function HighestPriority returns the highest priority exception from those that have been thrown (please refer to
DataAddress function defines the value that is stored into the
EXCEPT
_
ADDR
control register. Its return value will either be 0 or the effective address of data which has triggered the exception.
Therefore, variable
← is equivalent to:
IF ((exception = DBREAK) OR
(exception = MISALIGNED_TRAP) OR
(exception = CREG_NO_MAPPING) OR
(exception = CREG_ACCESS_VIOLATION) OR
(exception = DPU_NO_TRANSLATION) OR
(exception = DPU_ACCESS_VIOLATION)) THEN
variable
←
ELSE
variable
←
Where value is the optional argument that will have been passed to the THROW
(see
Section 16.4.5: Exceptions on page 121 ) when the exception was generated.
The rfi (return from interrupt) operation is used to recommence execution at the trap point. An rfi operation will cause the following state updates:
PC
←
// Address execution control is
// transferred to by rfi. Can be
// altered during the exception
// handler routine.
PSW
←
// Restore saved_psw. Can be
// altered during the exception
// handler routine.
SAVED_PC
←
SAVED_PSW
←
// Restore previous saved_pc
// Restore previous saved_psw
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5.4 Interrupts
All interrupts are effectively treated by the ST220 as an exception of type
EXTERN
_
INT
. Individual interrupt lines are indicated by registers in the interrupt
controller, Chapter 12: Interrupt controller on page 79 .
5.5 Debug interrupt handling
Please refer to
Chapter 13: Debugging support on page 85
.
5.6 Exception types and priorities
The table below shows the possible exceptions and the bit number in the
EXCEPT _ CAUSE control register that each corresponds to. Since only one exception is raised at a time, simultaneous exceptions are prioritized. The table is listed in exception priority order starting with the highest priority.
STBUS _ DC _ ERROR
EXTERN _ INT
IBREAK
SBREAK
ILL _ INST
Name
STBUS _ IC _ ERROR
IPU _ NO _ TRANSLATION
IPU _ ACCESS _ VIOLATION
Bit(s)
Access
(U/S)
Reset Comment
0
1
2
3
4
5
6
7
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
The Instruction Cache caused a bus error.
The Data Cache caused a bus error.
There was an external interrupt.
The IPU has triggered a breakpoint on an instruction address.
There was no mapping in the IPU for the given address.
Permission to access an address controlled by the IPU was not met.
A software breakpoint was found.
The bundle could not be decoded into legal sequence of operations or a privileged operation is being issued in user mode.
Table 2: EXCEPT_CAUSE bit fields
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Exception types and priorities 35
DBREAK
SDI _ TIMEOUT
Name
MISALIGNED _ TRAP
CREG _ NO _ MAPPING
CREG _ ACCESS _ VIOLATION
DPU _ NO _ TRANSLATION
DPU _ ACCESS _ VIOLATION
Bit(s)
Access
(U/S)
Reset Comment
8
9
10
11
12
13
14
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
0x0
0x0
0x0
0x0
0x0
0x0
0x0
The DPU has triggered a breakpoint on a data address.
The address is misaligned and misaligned accesses are not supported.
The load or store address was in control register space, but no control register exists at that exact address.
A store to a control register was attempted whilst in user mode.
There was no mapping in the DPU for the given address.
Permission to access an address controlled by the DPU was not met.
One of the SDI interfaces timed out while being accessed.
Table 2: EXCEPT_CAUSE bit fields
5.6.1 Illegal instruction definition
An illegal instruction exception is caused when an illegal bundle is executed. A legal bundle and all syllables contained in it must conform to the restrictions as detailed in
Chapter 17: Instruction set on page 135 .
A legal bundle and all syllables contained in it must conform to the following:
•
All syllables must be valid operations
•
A bundle must have a stop bit that is, four zero stop bits are illegal.
•
Unused opcode fields must be set to zero, including bit 30.
•
Any branch or call operation must appear as the first syllable of a bundle.
•
Multiply operations must appear at odd word addresses.
•
Long immediate extensions must appear at even word addresses.
•
Immediate extensions must associate with an operation that is in the same bundle and has an immediate format that can be extended.
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•
A privileged operation can only be executed in supervisor mode.
•
Only one memory operation can be performed in each bundle.
•
A sync operation must be alone in a bundle.
•
An sbrk operation must have the stop bit set.
•
Destination registers in a bundle have to be unique, with the exception of R0.
•
ldb , ldh and mul operations must not have R63 as a destination register.
5.7 Speculative load considerations
Speculative (or dismissible) loads are defined such that they execute as normal loads except in the following cases:
1 The address is in a peripheral region where a speculative load may be destructive. This is indicated by the
DPU [ SPEC
_
ZERO ] . In this case a zero is always returned and no access is made to the peripheral region.
2 A normal load would cause an exception. Generally, in this case, the load is considered to have been incorrectly speculated and the data will not utilized in the correct execution of the program. Zero is returned by default, the following two sub-sections detail the exceptions to this behavior.
3 If a dismissible load causes a bus error then a bus error exception is always raised. The DPU should always be set up to prevent dismissible loads from causing bus errors.
The overall speculative load behavior is summarized in
Table 3: Summary of a dismissible read of address “a” from memory .
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Result
0
0
0
0
1
0
0
1
1
0
1
0
1
0
0
1
0
1 x
0
0
1
0
0
0
1
0
0
0
0
0
1 x
0 x x
0
1 x
0
0
1 x
0
0
0
1
0 Data = ReadMemory(a)
1 Data = 0 x Data = 0 x Data = 0
0 Data = ReadMemory(a)
1 DPU _ ACCESS _ VIOLATION x DPU _ NO _ TRANSLATION x Data = 0
0 Data = ReadMemory(a)
1 Data = 0 x Data = 0 x MISALIGNED _ TRAP
0 Data = ReadMemory(a)
1 DPU _ ACCESS _ VIOLATION x DPU _ NO _ TRANSLATION x MISALIGNED _ TRAP x Data = 0 x x
Table 3: Summary of a dismissible read of address “a” from memory
37
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5.7.1 Misaligned implementation
Application or system software may require misalignment support, with misaligned accesses being correctly interpreted by the exception handler. To improve speculative load support for misaligned addresses, a control value
PSW [ SPECLOAD _ MALIGNTRAP _ EN ] can be set which causes speculative loads to trap on misaligned addresses rather than returning zero.
5.7.2 Speculative load exceptions
In some cases the software system may require a speculative load to cause a DPU exception instead of returning zero. This can be indicated by setting the
SPECLOAD _ DPUTRAP _ EN bit in the PSW control register.
Note: Misaligned is not treated as a DPU trap.
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Memory access protection units
The ST220 contains two memory protection units, one for instruction fetches (IPU) and one for load and store accesses (DPU). These units restrict access to memory according to whether the processor is in user or supervisor mode (see
Section 3.3.2: USER_MODE on page 27
) and also controls cacheability of memory accesses and the operation of speculative loads. The protection units do not provide address translation.
Note: The DPU is not used for control register access.
6.1 Description
On reset the instruction and data protection units are disabled, they are enabled
and disabled through the PSW control register (see Section 3.3: Program status word
). For further details on the behavior of the processor when a protection unit is disabled (see
Section 6.3.5: Operation when protection unit is disabled on page 46 ).
Note: It is stongly recommended that the IPU and DPU are enabled as soon as possible to protect against the generation of bus errors. Speculative loads should not be used until the DPU is enabled.
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The control registers of the protection units define a number of regions
1
of address space. Each region has information associated with it, including:
•
base address of region,
•
size of region,
•
access permissions of the region.
Note: Refer to
IPU attribute registers on page 44 for full details.
The size of a region is a ‘power of two’ number of bytes between 4 Kbyte and 4 Gbyte.
The base of a region must be aligned on a size of region boundary.
The DPU and IPU differ in the number of regions and the access permissions supported. The IPU supports four regions (0-3) and the DPU supports eight regions
(0-7).
The protection units allow regions to overlap which makes it possible to achieve complex mappings with a limited number of regions. If an address falls within more than one region, the information from the highest numbered region is used by the protection unit.
The protection units implement memory access restrictions including supervisor and user modes. They do not provide support for memory translation.
6.2 Operation
When enabled, each protection unit works by checking the address against the entries it holds. There are a number of possible outcomes:
No mapping
One region hit
Multiple region hits
There is no mapping for the address in the protection unit.
The properties of the selected region are applied.
The properties of the highest priority region are used.
1. The DPU/IPU should be disabled before making changes to the regions.
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Operation 41
6.2.1 Example use of overlapping regions
If 4 Kbyte of supervisor code and 28 Kbyte of user code need to be mapped into a
32 Kbyte area of memory, the number of regions required are:
Overlapping regions not supported
One 4 K byte region for supervisor code
One 16 K byte region for user code
One 8 K byte region for user code
One 4 K byte region for user code
Overlapping regions supported
One 4 K byte region for supervisor code
One 32 K byte region for user code
Table 4: Overlapping regions
Diagrammatically, this is shown in
4 Kbyte
4 Kbyte
8 Kbyte
4 Kbyte
Supervisor code
User code
16 Kbyte
32 Kbyte
Overlapping regions not supported
Overlapping regions supported
Figure 3: Overlapping regions
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With overlapping regions, the 4 Kbyte of supervisor code would be put into a higher priority region. This ensures that the supervisor mapping takes precedence over the user mapping.
6.2.2 Undefined address space
The provision of overlapping regions of memory allows the default protection for otherwise unmapped memory to be programmed.
This can be done by setting region 0 to be 4 Gbyte in size, based at address 0. The behavior of otherwise unmapped memory can be defined, that is, setting permissions for no access in supervisor and user modes. By default an unmapped area of memory will create a ‘no translation’ exception for addresses with no translation.
6.3 Protection unit registers
6.3.1 Region base registers
Region base registers define the areas of memory that are controlled by the protection unit. Each region register contains a field to describe the base address of the memory region it is to cover.
REGION _ ZERO
REGION _ BASE
Name Bit(s)
Access
(U/S)
[11:0] RO/RO
[31:12] RO/RW
Reset
0x0
0x0
Always zero.
Region base.
Table 5: DPU_REGION0 bit fields
Comment
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Protection unit registers 43
6.3.2 Region attribute registers
A summary of the fields within attribute registers is as follows:
•
The
OFFSET
field gives the size of the region.
•
Protection information (
PROT
) is encoded into two bits,
•
The
ENABLE
bit enables the region when set to 1, otherwise the region is disabled.
•
Cacheability is indicated by the
CACHEABLE
bit.
•
The
SPEC _ ZERO
bit indicates speculative load behavior in the region.
DPU attributes
Each DPU region has an attribute register that defines the properties and behavior of that region.
ENABLE
PROT
Reserved
CACHEABLE
SPEC _ ZERO
Reserved
OFFSET
Reserved
Name Bit(s)
Access
(U/S)
Reset Comment
0
[2:1]
[6:3]
7
8
RO/RW
RO/RW
RO/RO
RO/RW
RO/RW
0x0
0x0
0x0
0x0
0x0
[11:9] RO/RO
[16:12] RO/RW
[31:17] RO/RO
0x0
0x0
0x0
Table 6: DPU_ATR0 bit fields
Enables this region.
Protection attributes of this region.
Reserved
When set the region is cacheable.
When set speculative loads to this region return 0.
Reserved
The size of this region.
Reserved
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IPU attribute registers
The attributes of each IPU region are slightly different.
ENABLE
PROT
Reserved
OFFSET
Reserved
Name Bit(s)
Access
(U/S)
Reset Comment
0
[2:1]
RO/RW
RO/RW
[11:3] RO/RO
[16:12] RO/RW
[31:17] RO/RO
0x0
0x0
0x0
0x0
0x0
Table 7: IPU_ATR0 bit fields
Enables this region.
Protection attributes of this region.
Reserved
The size of this region.
Reserved
Offset field
The base of the region has to be aligned to the size of the region given in
OFFSET
(in the corresponding region attribute register). This restriction allows for faster computation of a region hit in the implementation. For example, the smallest region offset of 4 Kbyte must have a base address aligned to a 4 Kbyte boundary.
The offset value determines the size of the region, with the possible values given in
.
Offset[4:0]
01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101
Region size
4
K byte
8
K byte
16
K byte
32
K byte
64
K byte
128
K byte
256
K byte
512
K byte
1
M byte
2
M byte
4
M byte
Offset[4:0]
10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
Region size
8
M byte
16
M byte
32
M byte
64
M byte
128
M byte
256
M byte
512
M byte
1
G byte
2
G byte
4
G byte
Table 8: Offset field
An operating system (OS) can use large regions to set default permissions for the entire memory space.
The IPU has four regions. The four region and attribute registers are numbered from 0 to 3. If there are no matches between the given address and any described region an
IPU
_
NO
_
TRANSLATION
exception is generated.
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Protection unit registers 45
00
01
10
11
The DPU has eight regions. The eight region and attribute registers, numbered from
0 to 7. If there are no matches between the given address and any described region a
DPU
_
NO
_
TRANSLATION
exception is generated.
DPU protection field
The DPU has the following encoding for its protection bits:
Value User
No Access
Read/write
Read/write
Read/write
Supervisor
No access
No access
Read only
Read/write
The generation of the DPU _ ACCESS _ VIOLATION exception is summarized as follows:
00
01
10
11
Protection value Memory access
Supervisor mode User mode
Load Store Load Store
Access violation Access violation Access violation Access violation
OK OK Access violation Access violation
OK
OK
OK
OK
OK
OK
Access violation
OK
IPU protection field
00
01
10
11
Value Supervisor
Execute
No access
Execute
Reserved
User
Execute
No access
No access
The generation of the IPU _ ACCESS _ VIOLATION is conditional upon whether the machine is in supervisor or user mode, on a region by region basis according to the above table.
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6.3.3 Cacheable field
This field is used by the D-side memory subsystem to determine whether it may cache data from the region or not.
6.3.4 Speculative load returns zero field
In certain cases normal loads should return the data as expected but speculative loads to the same location should return zero without doing a memory access. If the
SPEC _ ZERO bit for the region is set in the attribute register, the LSU will be instructed to return zero as data and not make a memory request.
For a detailed description of how exceptions are handled with respect to this bit
being set, see Section 5.7: Speculative load considerations on page 36
.
6.3.5 Operation when protection unit is disabled
IPU
DPU
Cached, no protection.
Uncached, no protection. Speculative loads act as normal loads .
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®
Memory subsystem
This chapter describes the operation of the ST220 processor memory subsystem. The memory subsystem includes the caches, protection units, write buffer, prefetch cache and the core memory controller (CMC).
The memory subsystem is split broadly into two parts, the instruction side (I-side) and the data side (D-side). The CMC interfaces these two halves to the STBus port.
The I-side, containing the instruction cache and instruction protection unit (IPU), supports the fetching of instructions. The D-side, containing the data cache, data protection unit (DPU), prefetch cache and write buffer, support the storing and loading of data.
The ST220 ensures that data access are coherent with other data accesses. There is no guarantee of coherency between instruction and data accesses (see
7.5.3: Coherency between I-side and D-side on page 55
) or between the core and external memory. To ensure coherency data must be purged from the core as decribed later in this chapter.
The functions of the IPU and DPU are described in detail in
Chapter 6: Memory access protection units on page 39 , the streaming data interface (SDI) in
Streaming data interface (SDI) on page 57
.
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Load
Store
Unit
(LSU)
Read/Write/
Flush/Sync/Prefetch
Request
Read
Word
Data Cache
Uncached
Read/Writes
& Cache Fill
Cluster
Instruction
Cache
Read
4x32 bit
PC
Instruction
Buffer
PC and
Branch Unit
Busy
Writes &
(Reads/Prefetch/Sync/Flush)
Fetched
Data
Prefetches &
(Reads/Writes/Flush)
Write Buffer
Busy
Write
Data
Prefetch Buffer
Prefetch
Request
Prefetch
Data
D-Side
Memory
Subsystem
Read
Request
Read Response
Cache Line
CMC
STBUS
I-Side Memory
Subsystem
Figure 4: Memory subsystem block diagram
Within the ST220 the instruction buffer is responsible for issuing instructions to the processor core. The instruction cache fetches cache lines from memory, via the CMC and sends bundles of up to four operations to the instruction buffer.
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I-side memory subsystem 49
7.2.1 Instruction buffer
The instruction buffer attempts to fetch ahead in the instruction stream in order to keep its buffer full. When a branch is taken the instruction buffer is invalidated and a fetch started from the target address.
After a branch the instruction buffer will take one cycle to fetch the next bundle from the cache, this means the ST220 will stall for one cycle. If the branch is to a bundle that spans two cache lines then it will take two cycles to fetch the bundle and thus the ST220 will stall for two cycles.
7.2.2 Instruction cache
Instructions are always cached; there is no support for uncached instruction fetching.
Self modifying code (loaders for example) must invalidate the cache explicitly.
The instruction cache is a 32 Kbyte direct mapped cache with 64-byte lines. It receives fetch requests from the instruction buffer and returns a group of up to four
32-bit operations (16 bytes).
When instructions are requested from the cache it uses the address to determine whether they are already present in the cache. If the instructions are not in the cache, they are fetched from memory and stored into the cache, during which time the processor will stall. The requested instruction bundle is then returned to the instruction buffer.
To invalidate the instruction cache safely, two operations must be executed:
•
The first is prgins , which invalidates the whole instruction cache and causes any subsequent instruction fetches to be made from memory rather than from the cache.
•
The second is syncins , which ensure that all previous bundles have completed, and that their effects have completed, before any subsequent bundles are started.
This guarantees that the next bundle will be fetched with an invalidated cache, and therefore from memory. If this operation is not performed the subsequent bundle might have been prefetched and might not correspond to the instruction in memory. Currently, the syncins operation is a pseudo operation implemented as a goto the next bundle.
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7.2.3 I-side bus error
If the I-side memory subsystem causes a bus error, an STBUS _ IC _ ERROR exception is raised. Bus errors are asynchronous events and are not associated with a particular bundle.
In this case the cache will not be updated.
7.3 D-side memory subsystem
All data accesses take place through the D-side memory subsystem which contains the data cache, the prefetch cache and the write buffer. The data cache is 32 Kbyte
4-way associative with a 32-byte line. It is operated with a fixed write-back, no allocate on write-miss policy.
At most one of the write buffer, the data cache or the prefetch cache can contain a copy of the data for a particular address.
7.3.1 Load store unit
The load store unit (LSU) performs all data access operations. The cacheability is dependent on the address of the access and is determined by the DPU. In addition to load and store there are operations which prefetch data, flush and synchronize the
D-side memory subsystem.
The data cache sends write misses and dirty data to the write buffer (see Section
7.3.9: Write buffer on page 53
).
The write buffer combines write transactions and sends them out to memory.
7.3.2 Cached loads and stores
Cached loads and stores are performed through the data cache.
The memory subsystem can optimize these operations for performance.
For example, the memory subsystem can transfer more data than specified by the load (that is, a loading cache line), aggregate accesses (i.e. combining writes in write buffer) and/or re-order accesses (i.e. cache causes word accesses to be re-ordered).
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The memory subsystem presents a consistent view of cached memory to the ST220 programmer, that is, a store followed by a load to the same address will always return the stored data. To guarantee ordering of accesses to external memory in cached regions, purge and sync operations must be used.
7.3.3 Uncached load and stores
Uncached loads and stores are performed directly on the STBus. Data from an uncached region of memory will never be brought into the data cache or prefetch cache.
Section 7.5.6: Cached data in uncached region on page 56 .
The precise amount of data specified in the access is transferred and the access is not aggregated with any other. The implementation does not optimize these accesses.
To guarantee that an uncached store has completed, either a sync or an uncached load to the same bus target must be issued.
7.3.4 Prefetching data
The prefetch cache prefetches and stores data from external memory and sends it to the data cache when (and if) it is required.
A pft operation is a hint to the memory subsystem that the given item of data may be accessed in the future. The operation specifies an address which can be prefetched by the prefetch cache. Prefetches have no effect on the functionality of the CPU but may change its performance. A pft operation may be ignored.
Prefetches to uncached areas, control registers and invalid addresses (that is, may cause a DPU exception) are treated as nops .
The prefetch cache contains eight entries. Each entry contains an entry valid bit, a prefetch address, a data valid bit and 32 bytes of data space.
When a pft request is made and accepted, it enters the prefetch cache as an outstanding prefetch request, with the data valid bit clear. Older entries may be discarded if the prefetch cache is full. The prefetch cache will attempt to access the memory system to fetch the line containing the prefetch address. When a fetch completes the data valid bit is set. The prefetch cache supports multiple outstanding memory requests.
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Entries in the prefetch cache are tested when a data cache read miss occurs. If an entry match occurs and the data valid bit is set, the prefetched line is loaded into the data cache as if it were fetched from external memory. If the data valid bit is clear, the data cache stalls until the data is returned from external memory. The entry in the prefetch cache is then marked as empty and can be reused.
Entries in the prefetch cache are tested when a data cache write miss occurs. If an entry match occurs the prefetch cache entry is invalidated.
7.3.5 Purging data caches
The following purge (flush and invalidate) operations are used to ensure a copy of a particular data item is not cached in the D-side of the memory subsystem.
1 prgadd purges a line which hits the address operand from both caches (data and prefetch).
2 prgset purges the lines in the data cache set indicated by the address operand and purges the entire prefetch buffer.
These operations flush out the specified data. Dirty lines are written to the write buffer and the line is invalidated. Purge addresses are treated as byte aligned.
Purge operations cannot cause DPU exceptions.
7.3.6 D-side synchronization
This is achieved by executing the sync operation. Once the bundle containing the sync operation has completed, the following conditions hold:
1 All previous loads , stores and pfts have completed.
2 No future memory operations have started.
3 The write buffer is empty, all pending writes to external memory have completed.
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7.3.7 D-side bus errors
If the D-side memory subsystem causes a bus error, a STBUS _ DC _ ERROR exception is raised. Bus errors are asynchronous events and are not associated with a particular operation.
In the case of writes the data will have already been discarded and therefore the write is lost. The write may or may not have completed.
In the case of reads the cache will not be updated.
7.3.8 Operations
The memory subsystem supports the following operations:
Type Word aligned Half word aligned Byte aligned
Load
Store
Prefetch
Purge
Sync
Load word
Load Dismissible Load word
Store word
Load half unsigned
Load half unsigned
Store half
Load half signed
Load half signed
Load byte unsigned
Load byte unsigned
Store byte
Prefetch
Purge address
Purge set
Sync
Load byte signed
Load byte signed
It is a requirement that half word load/stores are half word aligned (2 bytes) and word load / stores are word aligned (4 bytes). Misaligned accesses will cause a
MISALIGNED _ TRAP exception.
7.3.9 Write buffer
Writes that miss the data cache and dirty lines that are evicted from the cache are held in the write buffer pending write back to external memory.
The write buffer is a write combining buffer that holds up to four entries. Each entry has 32 bytes of data, an address and 32 bits of byte masks. The write buffer is operated as an LRU (least recently used) buffer.
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Write combining allows individual close proximity writes to be merged into a single entry. Write combining improves performance significantly (for a no write allocate cache) when performing sequences of writes to blocks of data which have not been brought into the cache.
7.4 Core memory controller (CMC)
The CMC allows multiple masters to access the STBus via a single port. The CMC arbitrates between multiple requestors and correctly routes responses.
The memory subsystem requires some additional explanation of some key operations and methods of use. This section is intended to provide this information without filling out the previous sections.
7.5.1 Forcing writes to external memory
After any purge operations have taken place a sync should be issued to ensure all writes, including cache write backs, have completed. This combination of operations will guarantee that the purged data will not be in the data cache, prefetch cache or write buffer.
The sync operation should also be used to ensure that uncached writes have reached external memory.
7.5.2 Memory ordering
The sync operation should be used:
•
to ensure that all uncached writes have completed,
•
to enforce a particular ordering of memory operations,
•
to flush the write buffer of pending external memory writes.
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Additional notes 55
7.5.3 Coherency between I-side and D-side
There is no coherency guaranteed between the external memory and the D-side and
I-side memory subsystems. If coherency is desired then the memory subsystem has to be purged and synchronized.
This is achieved by the following sequence:
1 Flush the entire data cache by issuing prgset operations for every set of lines in the cache.
2 Sync the D-side by issuing a sync.
3 Invalidate the entire instruction cache by issuing a prgins.
4 Sync the I-side by issuing a syncins.
This sequence can be modified to perform coherency on a smaller memory region.
7.5.4 Changing memory to uncacheable
Data memory can be cacheable or uncacheable. Instruction memory is always cacheable.
To change an area of data memory from being cacheable to uncachable it is necessary to:
1 Mark region uncacheable in the DPU.
2 Flush it by issuing prgadd or prgset operations.
3 Sync the data cache by issuing a sync .
The region is now uncached and all loads and store operations to data within it are guaranteed to be uncacheable.
Note: Once a region is marked uncacheable no addresses from that region can become cached; a load to an uncacheable address which misses the cache will not cause the address to be allocated in the cache.
7.5.5 Reset state
After reset all lines in the instruction cache and data cache are marked as invalid.
The write buffer and prefetch cache entries are marked as empty.
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7.5.6 Cached data in uncached region
Non-cacheable accesses also go to the memory system via the data cache tag ram matching hardware. A side-effect of this implementation is that even non-cacheable accesses will cause a hit if the requested address is already in the cache. This can happen if the user changes an already cached location from cacheable to non-cacheable status.
If data from an uncached region is left in the cache, due to a change in the region’s cacheability, then any accesses to this data will be treated as cached.
To prevent this seemingly unpredictable behavior a region that is changed from cacheable to uncachable must be purged from the cache. To change a region to uncached see
Section 7.5.4: Changing memory to uncacheable on page 55
.
7.5.7 Prefetch performance
The prefetch cache is intended to improve performance. This is achieved by explicitly fetching data which lies in external memory and hiding the latency associated with that fetch. A number of points must be borne in mind to make the prefetch cache work effectively.
1 Data must be prefetched well in advance of use. The latency of an external memory access needs to be hidden between the pft operation and the first load operation which uses data from the prefetched line. This latency is in the region of 30 - 50 bundles for stall free bundles.
2 The prefetch cache size should be taken into account, such that the number of outstanding prefetches does not exceed the number of entries in the prefetch cache.
3 Unused prefetches increase bandwidth and waste entries in the prefetch cache.
The first two points indicate a window for which prefetches might be considered.
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ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Streaming data interface
(SDI)
8.1 Overview
The ST220 SDI is designed to allow fast and easy connection of on-chip peripherals.
Each SDI is unidirectional and includes handshakes to prevent data loss and improve data flow.
The ST220 implements four SDI interfaces, two input ports and two output ports.
Data In
Data In
Data Out
Data Out
SDI
Input
SDI
Input
SDI Output
ST220 Core
Control
Registers
SDI Output
Cluster
Figure 5: SDI overview
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The SDIs:
•
provide a mechanism for attaching streaming hardware to the processor core
•
reduce STBus traffic and associated processor stall cycles
•
reduce cache pollution and control complexity
•
prevent deadlock through a timeout mechanism
•
allow communication between clock domains without complex synchronization hardware
The SDI ports are accessed via control registers in the core.
Data is communicated synchronously through either output port or input port to the processor. Data is communicated in order, that is, the n-th data item communicated will arrive after the (n - 1)th item and before the (n + 1)th data item.
Writes ( stores ) to an output port will block if the SDI is full. Conversely reads
( loads ) from an input port will block if the channel is empty. The ST220 blocks execution by stalling the entire processor. No execution proceeds until the channel becomes ready for the requested communication, or an interrupt or timeout exception occurs.
Interrupts can also be taken while waiting on the SDI.
8.2.1 Data width
The SDI interface is 32-bits wide.
External to the SDI port, however, the data width can be arbitrary. For example connecting to a DCT peripheral which consumes 16-bits, data could be sent from the
ST220 as single 16-bit items. The ST220 can only write 32-bit data to control registers, so writing a pair of 16 bit values in a packed word would be twice as fast.
Note in this case the peripheral has to expect pairs of 16-bit values.
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Communication channel 59
In its basic form the SDI can be used as a communication channel to and from the processor. It is fully synchronized, allowing idealized input and output to be dealt with directly by the processor using load and store operations directly access the processor registers.
The SDI accesses can be initiated from C program code as accesses to volatile variables.
8.3.1 Timeouts
The timeouts operate as monitors to each individual SDI access. If an access remains stalled for too long, as defined by the control registers, an exception will occur.
8.4 Registers
The SDI interfaces directly to the ST220 load store unit. The interface is through a number of memory mapped registers in the control register address space.
The addresses of these registers are detailed in
Chapter 9: Control registers on page 65
.
8.4.1 Input channel memory mapping
SDI i _
DATA
SDI i _
READY
The
SDI i _
DATA
register is the location from which data is read from the input channel. The processor control and channel logic synchronize to ensure no data is lost. If the
SDI i _
DATA
register is empty the processor will stall. Writing this register has no effect and the processor will not stall.
The
SDI i _
READY
register is implementation specific. If non zero it indicates that the channel has data ready to be read.
This value indicates a minimum number of ready items.
Returning the exact amount of data ready to be read from the channel may not be possible for a number of reasons, that is, clock boundary issues, propagation delays, hence the looser condition of the minimum number of ready items. In its simplest form this ready value can be 1, indicating at least one item is ready.
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SDI i _
CONTROL
The
SDI i _
CONTROL
register is used to reset the channel and the
SDI i _
TIMEOUT
register. The usage of the bits are defined in
. The definition of the privilege bits is given in Section
.
PRIV
RESETINPUT
RESETOUTPUT
INPUTNOTOUTPUT
Reserved
MASTERNOTSLAVE
TIMEOUTENABLE
Reserved
Name Bit(s)
Access
(U/S)
Reset Comment
[1:0]
2
3
4
5
6
7
RO/RW
RO/RO
RO/RW
RO/RO
RO/RO
RO/RO
RO/RW
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Privilege bits.
RESETINPUT (Read Only) acts as
RESETREQUEST when slave,
RESETACK when master.
RESETOUTPUT, acts as
RESETREQUEST when master,
RESETACK when slave.
INPUTNOTOUTPUT (Read only).
Reserved
MASTERNOTSLAVE (Read only).
Timeout Disable (set to 1 to disable timeout interrupts).
Reserved [31:8] RO/RO 0x0
Table 9: SDI0_CONTROL bit fields
SDI i _
COUNT
The
SDI i _
TIMEOUT
register is reset to this value each time an SDI data value is successfully accessed. The value may be read or written. At reset it is set to a fixed value defined by the particular implementation. Time-outs can be disabled via the
SDI i _
CONTROL
register.
SDI i _
TIMEOUT
The number of cycles an SDI data access will be allowed to stall before a timeout exception will be raised. The value may be read or written. This register will normally be set to the value of
SDI i _
COUNT
. Exceptions to this are when it has been specifically set to another value, or when an SDI access has taken a timeout exception or been interrupted. In the case of an SDI timeout the
SDI i _
TIMEOUT
register will contain the value zero.
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Registers 61
8.4.2 Output channel memory mapping
SDI
SDI i _ DATA i _
READY
The SDI i _ DATA register is the location from which data is written to the output channel. The processor control and channel logic synchronize to ensure no data is overwritten. If the SDI i _ DATA register is full, the processor will stall. Reading this value has no effect and the processor will not stall. The value returned is implementation specific.
The
SDI i _
READY
register is implementation specific. If non zero it indicates that the channel has space where data can be written.
This value indicates a minimum number of empty spaces where data can be written. In an implementation where the channel is connected to a FIFO this register could indicate, full, notfull, the
FIFO is half empty by returning (for example) the values 0, 1, 32.
Returning the exact amount of data space available in the channel may not be possible for a number of reasons, that is, clock boundary issues, propagation delays, hence the looser condition of the minimum number of ready items. In the simplest form this ready value can be 1, indicating at least one item can be written.
SDI i _
CONTROL
Bits defined as Section 8.4.1: Input channel memory mapping on page 59 .
SDI i _
COUNT
Defined as
Section 8.4.1: Input channel memory mapping on page 59 .
SDI i _
TIMEOUT
Defined as
Section 8.4.1: Input channel memory mapping on page 59 .
8.4.3 Protection
The SDI register space is protected from malicious usage via access permissions held in each SDI i _ CONTROL register. The reset behaviour is that accesses to the SDI registers are only allowed in supervisor mode.
The protection can be loosened to allow user access to an SDI i _ DATA and SDI i _ READY registers. This is achieved via the SDI i _ CONTROL register, PRIV [1:0] two bit field, indicating the access allowed for each SDI.
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00
SDI_Access_Priv
01
10
11
Allowed privilege
Supervisor
User
Supervisor
User
Not defined
Not defined
Any access allowed
Protected, will cause exception
Any access allowed
Allow access to data and ready register
Reserved
Reserved
Comment
Table 10: Access Privileges for SDI Ports
8.5 Exceptions, interrupts, reset and restart
8.5.1 Interrupts
While stalled accessing the SDI, the processor can take any processor interrupt. The interrupt will be taken as if it occurred just prior to the bundle accessing the SDI.
Return from interrupt
The rfi from the exception handler will continue, as is normal operation, at the point prior to the interrupt.
If the SDI has become ready during execution of the interrupt handler the
SDI i _ TIMEOUT register will be reset to the value in SDI i _ COUNT .
If however the SDI is not ready, the processor will revert to the stalled state. This will be waiting for the channel to become ready while counting down the
SDI i _ TIMEOUT register from the value held prior to the exception.
Access to SDI registers
The interrupt handler can access all the SDI registers.
Note: Accessing the SDI i _ DATA register may alter the state of the processor observed by the interrupted processor.
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Exceptions, interrupts, reset and restart 63
8.5.2 SDI exceptions
In this case the EXCEPT _ CAUSE register will indicate an SDI timeout exception. The exception address will point to the SDI register on which the processor was waiting when the exception occurred.
An ST220 communications SDI timeout exception will occur if the processor is actively waiting for a response from the interface for longer than the interface’s timeout period.
The ST220 exception handler, in the case of a SDI timeout exception, is able to restart the communicating process. This is achieved by executing an rfi to the instruction that caused the exception. This will cause re-execution of the instruction accessing the SDI.
Note: The SDI i _ TIMEOUT register will need increasing from the zero value that caused the exception, otherwise the exception will be triggered again immediately.
The timeout exception is generated by the processor and not the channel.
8.5.3 Restart (or soft reset)
A channel can only be restarted by the master of the channel.
A master may be either an input or an output channel.
Figure 6: Soft reset control structure on page 64
shows how the reset structure is connected.
A reset is initiated by the master by setting the
RESETREQUEST
bit in the CONTROL register. This causes the channel to begin the reset process. Once acknowledged (i.e.
RESETACK
= 1) as having been received by the slave, and consequently the entire channel structure being reset, the reset is removed (that is,
RESETREQUEST
= 0) is communicated to the slave port. Once acknowledged (that is,
RESTACK
= 0), this indicates that the entire channel has exited the reset state.
The slave reset can be used to reset a slave subsystem.
Normally the output channel will be the master. However in cases where the output channel is connected to a dump peripheral it may be necessary to make the input channel the master, particularly where this is a processor interface.
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The restart structure outlined will work across asynchronous clock boundaries.
Slave
Data
Transport
Data
Transport
Control
Transport
Control
Transport
ResetReq
ResetAck
Master t
ResetReques
ResetAck
1
3
4
2
Figure 6: Soft reset control structure
1) Master requests reset. Subsystem resets itself and consumes all data presented at inputs.
RESETREQUEST
is forwarded to other slave side subsystems.
2) All units in reset. After subsystem has reset itself AND all slave side subsystems have sent
RESETACK
,
RESETACK
can be forwarded to master.
3) Master requests leave reset. Unit forwards removal of
RESETREQUEST
to all slave-side subsystems. Unit leaves reset and stops consuming data.
4) All units out of reset. On receipt of
RESETACK
from all subsytems,
RESETACK
is forwarded to master. System can restart.
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ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Control registers
The ST220 control registers contain processor state which is not commonly accessed by application code. This includes accessing the protection units, PSW , exception registers and breakpoint registers.
Control registers
1
are mapped into the address space, allowing access through normal load and store operations.
All control register accesses are word (32-bit) operations. Byte and half word load and stores to control registers are not supported and will generate
CREG _ ACCESS _ VIOLATION exceptions.
Dismissible loads to control register space always return zero. Control register loads or stores are executed within the LSU without reference to the DPU regions.
9.2 Exceptions
The control register unit generates an exception when a load or store tries to:
•
access a control register that does not exist ( CREG _ NO _ MAPPING ),
•
write to a control register without correct permissions
( CREG _ ACCESS _ VIOLATION ),
1. Control registers can not be accessed via the STBus.
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•
perform a byte and half word accesses to control registers
( CREG _ ACCESS _ VIOLATION ),
•
perform a misaligned word access to a control register (
CREG
_
NO
_
MAPPING
)
For details of the exception cause register see
Section 5.6: Exception types and priorities on page 34
.
PSW
SAVED _ PSW
SAVED _ PC
Below is a table of the control register addresses on the ST220.
The control registers start from a base of 0xFFFF0000, offsets listed in the table are relative to this.
The Access column shows the access rights in user and supervisor mode.
NA No access (protection fault)
RO
RW
CF
Read only
Read/Write
Configurable
Name
HANDLER _ PC
EXCEPT _ CAUSE
Offset
Access
(U/S)
Comment
0xfff8
0xfff0
RO/RW
RO/RW
The Program Status Word.
Saved PSW, written by hardware on exception.
0xffe8
0xffe0
0xffd8
RO/RW
RO/RW
RO/RW
Saved Program Counter, written by hardware on exception.
The address of the exception handler code.
A one hot vector of trap (exception/interrupt) types, indicating the cause of the last trap.
Written by the hardware on a trap.
Table 11: Control Registers - BASE: CREG_BASE
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Control register addresses 67
SCRATCH 1
SCRATCH 2
DPU _ REGION 0
DPU _ ATR 0
DPU _ REGION 1
DPU _ ATR 1
DPU _ REGION 2
DPU _ ATR 2
DPU _ REGION 3
DPU _ ATR 3
DPU _ REGION 4
DPU _ ATR 4
DPU _ REGION 5
DPU _ ATR 5
Name
EXCEPT _ ADDR
ST 200_ VERSION
SAVED _ SAVED _ PSW
SAVED _ SAVED _ PC
PERIPHERAL _ BASE
Offset
Access
(U/S)
Comment
0xffd0
0xffc8
RO/RW
RO/RO
This will be the data effective address in the case of either a DPU, CREG, DBREAK, or
MISALIGNED_TRAP exception. For other exception types this register will be zero.
The version number of the core. For the
ST220 returns 0x01.
0xffc0
0xffb8
0xffb0
RO/RW
RO/RW
RO/RO
PSW saved by debug unit interrupt.
PC saved by debug unit interrupt.
0xffa8
0xffa0
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
Base address of peripheral registers. The top
12 bits of this register are wired to the peripheral base input pins.
Scratch register reserved for use by the interrupt handler.
Scratch register reserved for use by the debug interrupt handler.
DPU region address.
0xff80
0xff78
0xff70
0xff68
0xff60
0xff58
0xff50
0xff48
0xff40
0xff38
0xff30
DPU region attribute.
DPU region address.
DPU region attribute.
DPU region address.
DPU region attribute.
DPU region address.
DPU region attribute.
DPU region address.
DPU region attribute.
DPU region address.
0xff28 RO/RW DPU region attribute.
Table 11: Control Registers - BASE: CREG_BASE
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Name
DPU _ REGION 6
DPU _ ATR 6
DPU _ REGION 7
DPU _ ATR 7
DBREAK _ LOWER
DBREAK _ UPPER
DBREAK _ CONTROL
IPU _ REGION 0
IPU _ ATR 0
IPU _ REGION 1
IPU _ ATR 1
IPU _ REGION 2
IPU _ ATR 2
IPU _ REGION 3
IPU _ ATR 3
IBREAK _ LOWER
IBREAK _ UPPER
IBREAK _ CONTROL
PM _ CR
PM _ CNT 0
PM _ CNT 1
PM _ CNT 2
PM _ CNT 3
PM _ PCLK
Offset
Access
(U/S)
Comment
0xfe38
0xfe30
0xfe28
0xfe20
0xfe18
0xfe10
0xfe08
0xfdd0
0xff20
0xff18
0xff10
0xff08
0xfe80
0xfe78
0xfe70
0xfe40
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
DPU region address.
DPU region attribute.
DPU region address.
DPU region attribute.
Data breakpoint lower address.
Data breakpoint upper address.
Data breakpoint control.
IPU region address.
IPU region attribute.
IPU region address.
IPU region attribute.
IPU region address.
IPU region attribute.
IPU region address.
IPU region attribute.
Instruction breakpoint lower address.
0xfdc8
0xfdc0
0xf800
0xf808
RO/RW
RO/RW
RO/RW
RO/RW
Instruction breakpoint upper address.
Instruction breakpoint control.
Performance monitoring control.
Performance monitor counter 0 value.
0xf810
0xf818
0xf820
0xf828
RO/RW
RO/RW
RO/RW
RO/RO
Performance monitor counter 1 value.
Performance monitor counter 2 value.
Performance monitor counter 3 value.
Performance monitor core cycle counter.
Table 11: Control Registers - BASE: CREG_BASE
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Control register addresses
Name
SDI 0_ DATA
SDI 0_ READY
SDI 0_ CONTROL
SDI 0_ COUNT
SDI 0_ TIMEOUT
SDI 1_ DATA
SDI 1_ READY
SDI 1_ CONTROL
SDI 1_ COUNT
SDI 1_ TIMEOUT
SDI 2_ DATA
SDI 2_ READY
SDI 2_ CONTROL
SDI 2_ COUNT
SDI 2_ TIMEOUT
SDI 3_ DATA
SDI 3_ READY
SDI 3_ CONTROL
SDI 3_ COUNT
SDI 3_ TIMEOUT
Offset
Access
(U/S)
Comment
0xe418
0xe420
0xe800
0xe808
0xe810
0xe818
0xe820
0xec00
0xe000
0xe008
0xe010
0xe018
0xe020
0xe400
0xe408
0xe410
CF/RW
CF/RW
RO/RW
RO/RW
RO/RW
CF/RW
CF/RW
RO/RW
RO/RW
RO/RW
CF/RW
CF/RW
RO/RW
RO/RW
RO/RW
CF/RW
SDI 0 data.
SDI 0 ready.
SDI 0 control.
SDI 0 count.
SDI 0 timeout.
SDI 1 data.
SDI 1 ready.
SDI 1 control.
SDI 1 count.
SDI 1 timeout.
SDI 2 data.
SDI 2 ready.
SDI 2 control.
SDI 2 count.
SDI 2 timeout.
SDI 3 data.
0xec08
0xec10
0xec18
0xec20
CF/RW
RO/RW
RO/RW
RO/RW
SDI 3 ready.
SDI 3 control.
SDI 3 count.
SDI 3 timeout.
Table 11: Control Registers - BASE: CREG_BASE
69
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®
Timers
Three timers are provided on the ST220. These are controlled by registers mapped into the ST220 memory space (see
Chapter 11: Peripheral addresses on page 75 ).
Timer Reload
TIMECNST
Mux
0
Test
TIMECNTR
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TIMEDIVIDE
Decrement
Bit i
TIMESTART
TIMECNTL
AND
Timer Interrupt
Figure 7: Timers
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72 Operation
10.1 Operation
For each of the three timers ( i = 0, 1, 2), the
TIMECNTR i register is the current value of the timer. This value is decremented on each timer tick until zero is reached.
Upon the next tick,
TIMECNTR i is loaded with
TIMECNST i and the i th timer interrupt is raised if enabled. The
TIMECNTL i register controls the enabling of interrupts for each timer.
Timer counting is enabled by the i th LSB of the TIMESTART register. Counters are not reset when disabled. Hence initial values can be written using the TIMECNTR i registers.
The frequency of timer ticks is controlled by programming the
TIMEDIVIDE
register.
These registers are covered in more detail in the following subsections.
10.1.1 TIMEDIVIDE
Th e TIMEDIVIDE register sets the number of bus clock cycles between each timer tick.
This register can be programmed with values between 0 and 65535 (only the bottom
16 bits are used). The divide value is equal to the value of this register plus one. This register will reset to zero (divide by 1). Writing this register sets the divide value and reading it returns the current divide value.
It is expected that the boot code will setup the TIMEDIVIDE register so that timer ticks occur every 1us.
10.1.2 TIMECNTR i
Name
COUNT
Bit(s)
Access
(U/S)
RW
Reset Comment
[31:0] 0x0 Current value of the timer counters.
Table 12: TIMECNTR0 bit fields
The TIMECNTR i registers hold the current values of the timer counters.
Writing to these registers can be used to set initial values for the counters.
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Operation 73
10.1.3 TIMECNST i
Name
CONST
Bit(s)
Access
(U/S)
Reset Comment
[31:0] RW 0x0 Constant to be reloaded when the timer reaches zero.
Table 13: TIMECNST0 bit fields
The
TIMECNST i registers set the value to be reloaded into each corresponding timer on reaching zero. If interrupts are enabled, this will define the number of ticks between interrupts.
10.1.4 TIMECNTL i
Name
ENABLE
Reserved
Bit(s)
Access
(U/S)
Reset Comment
0
[31:1]
RW
RO
0x0
0x0
Enable the timer interrupt.
Reserved
Table 14: TIMECNTL0 bit fields
The TIMECNTL i registers enable the timer interrupts the processor. The LSB of each register ( ENABLE ) enables the corresponding timer interrupt.
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10.1.5 TIMESTART
Name
T 0
T 1
T 2
Reserved
Bit(s)
Access
(U/S)
Reset Comment
0
1
2
[31:3]
RW
RW
RW
RO
0x0
0x0
0x0
0x0
Table 15: TIMESTART bit fields
Enable for timer 0.
Enable for timer 1.
Enable for timer 2.
Reserved
The
TIMESTART
register contains enable bits for each timers, (T0 for timer 0, T1 for timer 1 and T2 for timer 2), a set bit indicates enable and a clear bit disable. When disabled, a timer value remains constant.
10.2 Timer interrupts
.
Note: These bits remain set when the interrupt is taken and must be explicitly cleared.
10.3 Programming the timer
The
TIMECNST i registers set the value to be reloaded into the corresponding timer.
The value is loaded on the timer tick after a zero is reached, such that, the duration between timers reaching zero is (
TIMECNST i + 1). (For example, setting it to 99 will cause a reload and timer interrupt (if enabled) every 100 ticks.
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Peripheral addresses
On the ST220 the interrupt controller, DSU, DSU ROM and the timers are memory mapped peripherals. Under normal usage these peripherals should, with the exception of the DSU ROM, be mapped in an uncacheable region in the DPU.
11.1 Peripheral addresses
Below is a table of the peripheral register addresses on the ST220.
The peripheral registers start from the peripheral base address which can be found by reading the PERIPHERAL _ BASE
register (see Chapter 9: Control registers on page 65
).
The Access column shows the access rights:
RO Read only
RW
CF
Read/write
Configurable
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TIMESTART
TIMECNST 0
TIMECNTR 0
TIMECNTL 0
TIMECNST 1
TIMECNTR 1
TIMECNTL 1
TIMECNST 2
TIMECNTR 2
TIMECNTL 2
INTPENDING 0
INTPENDING 1
INTMASK 0
INTMASK 1
INTTEST 0
INTTEST 1
INTCLR 0
INTCLR 1
INTSET 0
INTSET 1
TIMEDIVIDE
INTMASKCLR 0
INTMASKCLR 1
INTMASKSET 0
11.1.1 Interrupt controller & timer registers
The interrupt controller and timer registers start from PERIPHERAL _ BASE + 0x0.
Name Offset
Access
(U/S)
Comment
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RO
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0x40
0x48
0x50
0x58
0x60
0x68
0x70
0x78
0x0
0x8
0x10
0x18
0x20
0x28
0x30
0x38
0x80
0x88
0x90
0x98
0x100
0x108
0x110
0x118
Table 16: Interrupt Controller - BASE: INTCR_BASE
Interrupt pending bits 31:0.
Interrupt pending bits 63:32.
Interrupt mask bits 31:0.
Interrupt mask bits 63:32.
Interrupt test register bits 31:0.
Interrupt test register bits 63:32.
Interrupt clear register bits 31:0.
Interrupt clear register bits 63:32.
Interrupt set register bits 31:0.
Interrupt clear register bits 63:32.
Timer start.
Timer constant.
Timer counter.
Timer control.
Timer constant.
Timer counter.
Timer control.
Timer constant.
Timer counter.
Timer control.
Timer divide.
Interrupt mask clear bits 31:0.
Interrupt mask clear bits 63:32.
Interrupt mask set bits 31:0.
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Peripheral addresses
Name
INTMASKSET 1
Offset
Access
(U/S)
Comment
0x120 RW Interrupt mask set bits 63:32.
Table 16: Interrupt Controller - BASE: INTCR_BASE
DSR 7
DSR 8
DSR 9
DSR 10
DSR 11
DSR 12
DSR 13
DSR 14
DSR 0
DSR 1
DSR 2
DSR 3
DSR 4
DSR 5
DSR 6
DSR 15
DSR 16
DSR 17
DSR 18
11.1.2 DSU registers
The interrupt controller registers start from PERIPHERAL _ BASE + 0x3000
Name Offset
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RW
RW
RW
RW
RW
RW
Access
(U/S)
Comment
0x38
0x40
0x48
0x50
0x58
0x60
0x68
0x70
0x0
0x8
0x10
0x18
0x20
0x28
0x30
0x78
0x80
0x88
0x90
Table 17: Debug Support Unit - BASE: DSU_BASE
DSU version.
DSU status.
DSU output.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
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DSR 19
DSR 20
DSR 21
DSR 22
DSR 23
DSR 24
DSR 25
DSR 26
DSR 27
DSR 28
DSR 29
DSR 30
DSR 31
Name Offset
Access
(U/S)
Comment
0x98
0xa0
0xa8
0xb0
0xb8
0xc0
0xc8
0xd0
0xd8
0xe0
0xe8
0xf0
0xf8
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
Table 17: Debug Support Unit - BASE: DSU_BASE
11.1.3 DSU ROM
The DSU ROM starts from PERIPHERAL _ BASE + 0x4000 (see
Chapter 13: Debugging support on page 85 ).
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Interrupt controller
The ST220 interrupt controller supports up to 64 interrupt sources. The system is programmed via a number of 64-bit memory-mapped control registers.
12.1 Architecture
The structure of the interrupt controller is shown in Figure 8 .
External
Events
‘OR’
64 lines
‘AND’
64 lines
OR
Interrupt Line
To Processor
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Figure 8: Interrupt controller
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12.2 Operation
An interrupting event takes an interrupt line high. This is then sampled, causing the corresponding bit in the 64-bit
INTPENDING
register to be set. The
INTPENDING register is then parallel AND-ed with the
INTMASK
register. The masked interrupts are then OR-red into a single interrupt line that is presented to the processor core.
This architecture ensures that:
•
all external interrupts will interrupt the processor,
•
interrupts can be individually enabled or disabled.
Setting or clearing bits in the
INTMASK
register enables or disables the corresponding interrupt lines.
12.2.1 Test register
External interrupts are wide OR-ed with the contents of the INTTEST register before being sampled by the INTPENDING register. This allows the programmer to simulate interrupts into the processor for test purposes.
12.3 Interrupt registers
For the addresses of these memory mapped registers see Chapter 11: Peripheral addresses on page 75
.
12.3.1 Interrupt pending register
The 64-bit
INT PENDING
register holds the current interrupt status. Bits in this register are set by external interrupts or the
INTTEST
register.
A number of bits in the
INTPENDING
register are preassigned to ST220 peripherals.
The remaining bits can be assigned to other peripherals or external devices.
Name:
INTPENDING
0[31:0],
INTPENDING
1[63:32 ]
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Interrupt registers 81
TIMER 0
TIMER 1
TIMER 2
Reserved
Reserved
Name
0
1
Bit(s)
2
[15:3]
Access
(U/S)
RO/RO
RO/RO
RO/RO
RO/RO
[31:16] RO/RO
Reset
0x0
0x0
0x0
0x0
0x0
Comment
Interrupt is pending from timer 0.
Interrupt is pending from timer 1.
Interrupt is pending from timer 2.
System defined - refer to data sheet.
System defined non-maskable interrupts
- refer to data sheet.
Table 18: INTPENDING0 bit fields
Reserved
Name Bit(s)
[31:0]
Access
(U/S)
RO/RO
Reset Comment
0x0 System defined - refer to data sheet.
Table 19: INTPENDING1 bit fields
12.3.2 Interrupt mask register (INTMASK)
The
INTMASK
register is a 64 bit register whose contents are AND-ed with the
INTPENDING
register. It is used to enable and disable external interrupts.
Name:
Reset Value:
INTMASK
0
0[31:0],
INTMASK
1[63:32]
Interrupts are enabled by setting, and disabled by clearing, the corresponding bits the
INTMASK
register.
Bits 31:16 are fixed set, so that the corresponding interrupt lines are permanently enabled.
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INTMASKCLR and INTMASKSET
Two 64-bit address locations in the interrupt controller memory space support bit-wise access to the INTMASK register. A store to these locations causes the corresponding bits in the INTMASK register to be cleared or set.
Name:
INTMASKCLR
0[31:0],
INTMASKCLR
1[63:32],
INTMASKSET
0[31:0],
INTMASKSET
1[63:32]
0 Reset Value:
Using this method of accessing the INTMASK register avoids any problems caused by interrupts occuring during a Read-Modify-Write sequence and therefore avoids the need to have interrupts disabled while modifying these registers.
12.3.3 Interrupt test register (INTTEST)
The INT TEST register is a 64-bit register whose contents are OR-ed with external interrupts. It provides a mechanism for simulating interrupts to the processor.
Name:
Reset Value:
INTTEST
0
0[31:0], INTTEST 1[63:32]
Setting bits in the INTTEST register causes the corresponding bits in the INTPENDING register to be set.
INTCLR and INTSET
Two 64-bit address locations in the interrupt controller memory space support bit-wise access to the INTTEST register. A store to these locations causes the corresponding bits in the INTTEST register to be cleared or set.
Name:
Reset Value:
INTCLR
0
0[31:0], INTCLR 1[63:32], INTSET 0[31:0], INTSET 1[63:32]
Using this method of accessing the INTTEST register avoids the overhead in a direct write of having to read, save and restore unaccessed bits.
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12.4 Programming
12.4.1 Enabling/disabling interrupts
Interrupts are enabled and disabled by setting and clearing the appropriate bits in the INTMASK register.
In the ST220 interrupts 31:16 are non-maskable and permanently enabled.
INTMASK register bits 31:16 are tied to high.
The INTMASK register can written to directly as two 32-bit words, or bit-wise using the mask clear and mask set locations, see
INTMASKCLR and INTMASKSET on page 82
.
12.4.2 Test register
Interrupts can be simulated for test purposes by setting bits in the
INTTEST
register.
This register is directly OR-red with the external interrupt signals into the
INT PENDING
register.
The
INTTEST
register can written to directly as two 32-bit words, or bit-wise using the test clear and test set locations, see
.
Note: INTTEST register bits are not reset when the interrupt is taken and must be explicitly cleared by the program.
12.4.3 Interrupt priority
The interrupt handling code is responsible for prioritization of interrupts. No hardware support is provided.
12.4.4 Timer interrupts
The first three bits in the
INTTEST
register are also used in conjunction with the timer. When a timer interrupt occurs the corrisponding bit in the
INTTEST
register is set (timer 0 sets bit 0, timer 1 sets bit 1 and timer 2 sets bit 2). This prevents timer interrupts from being lost. When a timer interrupt is serviced the software should clear the correct bit in the
INTTEST
register.
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Debugging support
13.1 Overview
Debugging support on the ST220 is provided by 4 main components.
•
Core
The ST220 core includes a non maskable debug interrupt, and additional state to support the taking of debug interrupts. The core also contains hardware breakpoint support.
•
DSU
Shared DSU registers and state machine which generates debug interrupts and send responses over debug interface.
•
Debug ROM
Default program run in response to debug interrupt. This program uses the DSU registers to send higher level protocols over the debug interface. This program implements the DSU_PEEK , DSU_POKE , DSU_CALL_OR_RETURN and DSU_FLUSH operations.
•
Host debug interface
The hardware link, using the TAPlink protocol, to any connected host target interface (HTI). Supports peek , poke , peeked and event messages.
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13.2 Core
13.2.1 Debug interrupts
The ST220 can accept and service interrupts from the DSU. Debug interrupts are higher priority than normal interrupts, cannot be masked, and place the ST220 in a debug state.
Debug interrupt handling
A debug interrupt is handled differently to other external interrupts.
Taking a debug interrupt can be summarized as:
NEXT_PC
←
SAVED_SAVED_PSW
←
SAVED_SAVED_PC
←
SAVED_PSW
←
SAVED_PC
←
PSW[USER_MODE]
←
PSW[INT_ENABLE]
←
PSW[IBREAK_ENABLE]
←
PSW[DBREAK_ENABLE]
←
PSW[IPU_ENABLE]
←
PSW[DPU_ENABLE]
←
PSW[DEBUG_MODE]
←
Exiting debug mode
Debug mode is exited, and normal mode re-entered, when the DEBUG _ MODE bit is cleared in the PSW . The only supported method for writing the PSW is via the rfi operation (see
Section 3.3.4: Supported method for changing the PSW ).
Note: Although clearing the DEBUG _ MODE bit causes the ST220 to exit debug mode, attempting to set the DEBUG _ MODE bit when it is not already set does not cause the core to enter debug mode and the DEBUG _ MODE bit remains clear. Debug mode can only be entered by taking a debug interrupt from the DSU.
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13.2.2 Hardware breakpoint support
Breakpoints are supported by:
•
enable bits in the
PSW
,
•
address registers to define memory ranges,
•
control register to specify comparison operations.
The safe way to use the breakpoint registers is to disable the breakpoints and then set the control and address registers before enabling the breakpoints again. This will prevent spurious breaks due to inconsistent control and address registers.
Enable bits
Breakpoints are enabled though the PSW , one bit for instruction breakpoints and another data breakpoints (see
Section 3.3: Program status word (PSW)
).
Address registers
Two 32-bit registers are used to define addresses for the instruction and data breakpoints (
IBREAK
_
LOWER
,
DBREAK
_
LOWER
,
IBREAK
_
UPPER
,
DBREAK
_
UPPER
).
These registers are all reset to the value 0.
Control registers
Bits [3:0] in this register determine the comparison operations performed on the breakpoint addresses. If the comparison is true then a breakpoint exception (
IBREAK or
DBREAK
) is signaled.
For instruction breakpoints the bundle address is used for comparison. For data breakpoints, the data effective address is used for comparison. The following comparison operations are defined.
0
1
2
3
Bit Break point comparison
Address <= Upper && Address >= Lower
Address > Upper || Address < Lower
Address == Upper || Address == Lower
Address & Upper == Lower
Table 20: Breakpoint register comparisons
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13.3 Debug support unit
The DSU allows both software and hardware to be debugged from a host by giving direct access to the ST220 core.
13.3.1 Architecture
The architecture of the DSU is shown in Figure 9
.
Debug Support Unit
WRITEENABLE
Host
Host debug interface
Control block
Shared register bank
Debug
ROM
DEBUG_INTERRUPT
DEBUG_INTERRUPT_TAKEN
STBus port
ST220 core
Figure 9: DSU architecture
The DSU is controlled by a host via the debug interface. The DSU control block interacts directly with the ST220 core via the DEBUG _ INTERRUPT and
DEBUG _ INTERRUPT _ TAKEN signals, and the shared register block.
The shared registers can also be accessed via the STBus port.
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13.3.2 Shared register bank
The 32 shared registers consists of 3 reserved registers ( DSR 0-2) and 29 general purpose registers ( DSR 3-31). These are used to implement communication between the host and the target by the debug handler.
The shared register bank is 32-bits wide and only supports 32-bit STBus operations.
DSU shared registers are listed below.
Register
Name
DSR 0
DSR
DSR
1
2
Description
DSU version register
DSU status register
DSU output register
DSR 3-31
R
RW
Bits 0-5 R, others RW
RW
RW
Comments
Contains ID numbers for DSU, core, and chip version.
Contains DSU control and status bits.
Supports message transfer from target to HTI.
General purpose registers.
The STBus addresses of the DSU registers are detailed in
Chapter 11: Peripheral addresses on page 75
.
Shared access conventions
The DSU shared registers are accesable independently from both the DSU and the
STBus. The ST220 and DSU have no hardware support for synchronizing writes, so software conventions are used to prevent write conflicts.
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13.3.3 DSU control registers
Name
PRODUCT _ ID
CORE _ VERSION
DSU _ VERSION
Bit(s)
[15:0]
Access
(U/S)
RO
[23:16] RO
[31:24] RO
Reset Comment
0x0002 Chip ID.
0x02
0x02
ST220 core version number.
DSU design version number.
Table 21: DSR0 bit fields
DSU status register (DSR1)
The DSU status register contains the DSU status and control bits.
Name
HW _ FLAGS
SW _ FLAGS
DSU version register (DSR0)
The DSU version register is a read-only ID register:
DEBUG _ INTERRUPT _ TAKEN
SUPERVISOR _ WRITE _ ENABLE
USER _ WRITE _ ENABLE
Reserved
OUTPUT _ PENDING
Bit(s)
Access
(U/S)
RO
Reset Comment
0
1
2
[4:3]
5
RW
RW
RO
RO
0x0
0x1
0x0
0x0
0x0
[15:6] RW
[31:16] RW
0x0
0x0
Table 22: DSR1 bit fields
Value of DEBUG_INTERRUPT_TAKEN signal, active high.
STBus writes enabled if the core is in supervisor mode (regardless of debug mode).
STBus writes enabled if the core is in user mode (regardless of debug mode).
Reserved
DSR2 contains a byte to be sent to the
HTI which has not yet been sent.
Reserved for future hardware purposes.
Reserved for future software use.
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DSU output register (DSR2)
The lower 8 bits of the DSU output register are sent to the TAPlink (to any attached host) on being written.
Name
DATA
Reserved
Bit(s)
[7:0]
[31:8]
Access
(U/S)
RW
RO
Reset
0x0
0x0
Table 23: DSR2 bit fields
Comment
Output data.
Always zero.
If OUTPUT _ PENDING is non-zero then the byte most recently written has not yet been sent to the HTI and additional writes to the DSR 2 will not affect the byte being sent even if they change the contents of the register.
Messages sent via the DSR 2 may be delayed if the DSU is busy.
13.4 Debug ROM
The 1024-byte debug ROM is an ST220 peripheral. This contains the debug initialization loop and the default debug handler.
13.4.1 Debug initialization loop
On reset the ST220 starts executing at the beginning of the boot ROM. However, if the
DEBUG
_
ENABLE
signal is asserted execution starts at the debug initialization loop (this is the first word of the debug ROM). This word contains a single syllable bundle which loops back to the same location, allowing the DSU to intervene and configure the core before it executes any code.
Note: Where the
DEBUG
_
ENABLE
signal cannot be asserted, the boot ROM should start with a tight loop, or perhaps just a delay loop, to allow time for the DSU to interrupt the processor before it takes any action.
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13.4.2 Default debug handler
The default debug handler program starts at the second word of the debug ROM. It supports simple host-target debugging and the ability to install a more complex debug handler. The STBus address of the ROM is given in
Chapter 11: Peripheral addresses on page 75
.
Operation
On taking a debug interrupt, the default debug handler is executed. This first tests if a user handler is installed,
DSR
3 non zero, and if so branches to this address.
Otherwise the handler waits in the command loop.
Command loop
The command loop reads and processes commands from a host, delivered via the
TAPlink, to the DSU shared registers. Usage of the designated registers is shown in
.
Register name
DSU _ COMMAND
DSU _ ARG 1,2,3
DSU _ RESPONSE
Host use
Set with command
Set with arguments for command, before setting DSU _ COMMAND
Zeroed after being read
Target use
Zeroed when command accepted
Set with response arguments before setting DSU _ RESPONSE
Set to indicate outcome of a command
Table 24: Command register usage
When the command is complete, the default debug handler stores the results in the argument registers and sets a success code in the response register.
Default handler commands
DSU_PEEK (DSU_COMMAND =4)
Reads the 32-bit memory location addressed by
DSU
_
ARG
1 and returns the data in
DSU
_
ARG
1. The address must be word aligned. If the operation is successful
DSU
_
RESPONSE
is set to
DSU
_
PEEKED
(1) and a
TAPLINK
_
EVENT
_
DEFAULT
(reason=7) event is sent to the HTI.
Note: Any code greater than 4 is interpreted as a
DSU
_
PEEK
command.
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DSU_POKE (DSU_COMMAND = 3)
Writes the 32-bit data word in DSU _ ARG 2 to the memory location addressed by
DSU _ ARG 1. The address must be word aligned. If the operation is successful
DSU _ RESPONSE is set to DSU _ POKED (2) and a TAPLINK _ EVENT _ DEFAULT
(reason=7) event is sent to the HTI.
DSU_CALL_OR_RETURN (DSU_COMMAND = 1)
Calls the routine addressed by
DSU
_
ARG
1. If the called routine does not return this is effectively a branch. If
DSU
_
ARG
1 is zero this is a return call. Just before calling the user routine, or returning from a call,
DSU
_
RESPONSE
is set to
DSU
_
RETURNING
(3) and a
TAPLINK
_
EVENT
_
DEFAULT
(reason=7) event is sent to the host.
DSU_FLUSH (DSU_COMMAND = 2)
Flushes the address range delimited by
DSU
_
ARG
1 and
DSU
_
ARG
2 from data and instruction caches.
If a command was successful DSU _ RESPONSE is set to
DSU _ FLUSHED
(4) and a
TAPLINK _ EVENT _ DEFAULT
(reason=7) event is sent to the host.
Trap handler
If a trap occurs while a command is being processed, for example, an invalid address supplied on a peek or poke :
•
the operation in progress is completed by loading the
PC
of the offending bundle, the exception cause, and the exception address into
DSR
_
ARG
1,
DSR
_
ARG
2 and
DSR
_
ARG
3 respectively.
•
DSU
_
RESPONSE
is set to
DSU _ GOT _ EXCEPTION
(Code=5) and a
TAPLINK _ EVENT _ DEFAULT
(Reason=7) event is sent to the HTI.
•
As for all exceptions, the
SAVED
_
PC
and
SAVED
_
PSW
registers will have been updated when the exception occured.
Context restore
Prior to exit the default handler restores any state it has altered.
Note: The context may have been additionally altered by commands issued.
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Default handler register usage
The following DSU registers are defined and used by the default debug handler program:
DSR 14
DSR 15
DSR 16
DSR 17
DSR 18
DSR 19
DSR 20
DSR 21
DSR 22
DSR 23
DSR 24
DSR 25
DSR 26
DSR number
DSR 3
DSR 4-8 a
DSR 9 a
DSR 10 a
DSR
DSR
DSR
11
12
13 a
Designation Comment
DSR _ USER _ DEBUG _ HANDLER Control switches to this address if content is non-zero.
DSU _ ARG 4-8 Not used in current debug handler.
DSU _ ARG 3 Command argument 3.
DSU _ ARG 2 Command argument 2. Used by DSU _ POKE and
DSU _ FLUSH .
Command argument 1. Used by all DSU commands.
DSU _ ARG 1
DSU _ COMMAND
DSU _ RESPONSE
Context saving
Context saving
Context saving
Context saving
Context saving
Context saving
Context saving
Context saving
Context saving
Context saving
Context saving
Context saving
Context saving
Command register. Written by HTI, cleared by target when command accepted.
Response register. Set by target to a completion code, cleared by HTI before issuing next command.
Saves SCR 4_ REG b
Saves SCR 1_ REG b
Saves SCR 2_ REG b
Saves SCR 3_ REG b
Saves the branch bits
Saves LINK _ REG b
Saves HANDLER _ PC
Saves SAVED _ SAVED _ PSW
Saves SAVED _ SAVED _ PC
Saves SAVED _ PSW
Saves SAVED _ PC
Saves EXCAUSE
Saves EXADDRESS
Table 25: DSU command registers
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DSR number
Designation Comment
DSR 27-30 Unused
DSR 31 Context saving
Unused
Saves DSR1
Table 25: DSU command registers a. Argument registers are placed before the command register in the address space so that a command and its arguments can be loaded with a single poke operation.
b. As defined by the ABI (see ST200 Programming Manual )
13.5 Host debug interface
Exchange of information with the host is via a host target interface (HTI) adaptor.
The DSU connects to the HTI via a JTAG interface, and the HTI connects to the host via Ethernet, USB, serial port or parallel port. This is illustrated in
All host-target communication is done with peek , poke , peeked and event messages sent between the host and the DSU.
Host
HTI adapter
JTAG
DSU ST220 core
Figure 10: DSU overview
13.5.1 Message format
Commands are sent to the DSU in Taplink message format consisting of a bidirectional byte stream which is interpreted by the DSU as a stream of commands.
Figure 11 shows the DSU commands in Taplink message format.
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HTI Initiated Messages
Poke DSR Address
Peek DSR Address
HTI or Target Initiated Messages
Event
First Data Word Second...
Response Messages
Peeked First Data Word Second Data Word Third...
Header
Byte
2nd
Byte
Figure 11: DSU commands
Note: Messages are transmitted little endian, independent of the endianness of the ST220 core.
Header bytes
Header bytes contain command-specific information such as the range of registers to be accessed. Header byte formats for the 4 DSU commands are illustrated in
Poke
Peek
Peeked
Event
7 6 5 4 word count
3 2
7 6 5 4 word count
3 2
7
7
6
6 channel
5 4 word count
3
5
2
4 3 reason
2
Header Byte
1
0
1
0
1
1
1
1
0
1
0
0
0
0
0
1
Figure 12: Header bytes
Subsequent Bytes
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Peek and poke operation
Peek and poke commands read and write the shared DSU registers. Each command uses a 6-bit count and one byte as a register address. The byte address references the first register in the range, and the count indicates how many registers are accessed. Counts greater than 32 are interpreted as 32.
Register addresses wrap, so a peek or poke with an address of 30 and a count of 4 will access registers
DSR
30,
DSR
31,
DSR
0 and
DSR
1, in that order.
The result of a peek command is returned to the host using a peeked message.
Note: Peeked messages are not supported from the host to the target and their behavior is undefined.
13.5.2 Operation
Generating debug interrupts
In order to interrupt the core, the host sends an event with reason=1. The event is decoded by the DSU and a
DEBUG _ INTERRUPT
signal is sent to the ST220. When the
ST220 takes the interrupt (as described in
Debug interrupt handling on page 86 )
the
DEBUG _ INTERRUPT _ TAKEN
signal goes high.
The functionality available to the host is then dependent on the debug handler program running. The default handler uses designated shared registers to provides
the higher level operations detailed in Default handler commands on page 92 .
Core initiated events
The core can also request service from the host by sending it an event message.
This is done by writing the event to the
DSR
2 (the output register). The channel and reason fields of the event message are not examined by the hardware and can be used as desired by the software.
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Performance monitoring
The ST220 provides a hardware instrumentation system which consists of a control register ( PM _ CR ), a core clock counter ( PM _ PCLK ) and four event counters ( PM _ CNT i , i
= 0, 1, 2, 3). They are all mapped to addresses in the control register space as defined in
Section 9.3: Control register addresses on page 66 .
The system allows the user to simultaneously monitor up to four of the sixteen predefined events.
14.1 Events
The programmable events supported by the ST220 are the following:
Unit
Data cache
Encoding
00000
00001
00010
Event Description
DHit
DMiss
Data cache hits. The number of load and stores that hit the cache. This includes uncached accesses that hit the cache.
The number of load and stores that miss the cache. This includes stores that miss the cache and are sent to the write buffer.
Uncached accesses are not included in this count.
DMissCycles The number of cycles the core is stalled due to the data cache being busy.
Table 26: Monitored events
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Data cache
(cont’d)
Instruction cache
Core
Unit
Reserved
Encoding
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
1xxxx
Event Description
PftIssued
PftHits
WBHits
IHit
IMiss
IMissCycles
IBufInvalid
Bundles
LDST
TakenBr
NotTakenBr
Exceptions
Interrupts
Undefined
The number of prefetches that are sent to the
STBus.
The number of cached loads that hit the prefetch buffer.
The number of writes that hit the write buffer.
The number of accesses the instruction buffer made that hit the instruction cache.
The number of accesses the instruction buffer made that missed the instruction cache.
The number of cycles the instruction cache was stalled for.
Duration where IBuffer is not able to issue a bundles to the pipeline.
Bundles executed
Load/Store instructions executed
Number of taken branches
Number of branches not taken
Number of exceptions and debug interrupts
Number of interrupts
These 16 event numbers are unused on the ST220 and are reserved for future usage.
Table 26: Monitored events
All the events relating to the architectural state of the machine are sampled when bundles commit.
14.2 Access to registers
As all the performance monitoring registers are mapped into the control register space, writing to them is only supported in supervisor mode. An attempt to write to a register in user mode will cause a CREG _ ACCESS _ VIOLATION exception.
Reading from the registers is permitted in both user and supervisor modes.
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14.3 Control register (PM_CR)
The control register is used to reset and enable all the counters, and define the events of the four programmable count registers. The purpose of each of the fields is given below:
Name
ENB
RST
Reserved
EVENT 0
EVENT 1
EVENT 2
EVENT 3
Bit(s)
Access
(U/S)
RO/RW
Reset Comment
0
1
[11:2]
[16:12]
[21:17]
[26:22]
[31:27]
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
0x0
0x0
0x0
0x0
0x0
0x0
0x0
When 1, counting is enabled. When 0 counting is disabled.
When a 1 is written all the counters
(PM_CNT0-3 and PM_PCLK) are set to zero. If a 0 is written it is ignored. This field does not retain its value and so always reads as 0.
Reserved
5-bit field specifying the event being monitored for this counter. Only values
0-15 have defined events associated with them.
5-bit field specifying the event being monitored for this counter. Only values
0-15 have defined events associated with them.
5-bit field specifying the event being monitored for this counter. Only values
0-15 have defined events associated with them.
5-bit field specifying the event being monitored for this counter. Only values
0-15 have defined events associated with them.
Table 27: PM_CR bit fields
Writing to the PM _ CR updates the value and reading from the PM _ CR returns the register’s current value.
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14.4 Event counters (PM_CNT
i
)
Each of the four event counters is incremented by one each time the countable event specified in the
PM _ CR
occurs. The four programmable event counters can record any one of the events specified in
.
Reading from these registers return the current event count. Writing will change the current count. If a counter is written at the same time as an event triggers the counter to increment then the increment is ignored.
14.5 Clock counter (PM_PCLK)
The
PM
_
PCLK
register is read only. Reading the
PM
_
PCLK
register returns a 32-bit value. Writes to
PM
_
PCLK
are ignored. This counter will silently wrap back to zero when it overflows.
14.6 Recording events
To start recording, an ST220 general purpose register needs to be written with the desired fields. This can be achieved by first reading the
PM
_
CR
register, then modifying it as appropriate. The
ENB
bit needs to be set to 1. The
RST
bit needs to be set to 1 if the counters are to be reset. The four programmable counter fields need to be set or modified to reflect change in events being recorded. The value in the register is then written to the memory mapped
PM
_
CR
for the operation to begin.
To stop recoding, the value of
PM
_
CR
be read, the
ENB
bit set to zero, and then written back to
PM
_
CR
. No other bits must be changed. If the
RST
bit is set to 1 then the
PM
_
CNT i registers will be reset.
Whilst counting events over a long period of time, the 32-bit counters may overflow.
This overflow will happen silently and the values will wrap around to zero. To obtain a continuous profile the counters must be read and reset at appropriate regular intervals (depending on the core clock frequency).
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Instruction
Cache
Cntr3 Cntr2 Cntr1 Cntr0 0 (Res) r e
/5
32:1 Mux
PM_CNT0
(Incrementor 32-bit )
/5
Data
Cache
32:1 Mux
/5
32:1 Mux
PM_CNT1
(Incrementor 32-bit )
/5
/1
/1
PM_CNT2
(Incrementor 32-bit )
Core
32:1 Mux
PM_CNT3
(Incrementor 32-bit )
P Clk
Figure 13: Performance monitor hardware organization
PM_PCLK
(Incrementor 32-bit )
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Execution model
15.1 Introduction
This chapter defines the way in which bundles are executed in terms of their component operations.
In the absence of any exceptional behavior the execution is straightforward.
The bundle is fetched from memory. The operations within it are decoded, and their operands read. The operations then execute and writeback their results to the architectural state of the machine. It is important to note that all instructions in a bundle commit their results to the state of the machine at the same point in time.
This is known as the commit point.
In the presence of exceptional behavior the commit point is used to distinguish between recoverable and non-recoverable exceptions.
Exceptions which can be detected prior to the commit point are treated as recoverable. They are recoverable because the machine state has not been updated, hence the state prior to the execution of the bundle can be recovered. In some cases the cause of the exception can be corrected and the bundle restarted.
Conversely non-recoverable exceptions are detected after the commit point.
Machine state has been updated and in some cases it may not even be clear which bundle caused the exception. Non-recoverable exceptions are naturally of a serious nature and cannot be restarted. The cause is normally an error in the external memory system, these translate to a bus error exception. On the ST220 this is the only non-recoverable exception.
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15.2 Bundle fetch, decode, and execute
The fetching, decoding and executing of bundles is specified using an abstract sequential model to show the effects on the architectural state of the machine. In this abstract model, each bundle is executed sequentially with respect to other bundles. This means that all actions associated with one bundle are completed before any actions associated with the next are started.
Implementations will generally make substantial optimizations over this abstract model. However, for typical well-disciplined bundle sequences these effects will not be architecturally visible. A fuller description of the behavior in other cases is defined by the
Chapter 5: Traps: exceptions and interrupts on page 31 .
Note: This simple model does not take into account the latency constraints of operands, and is therefore only valid for hazard free code. All code generated by the compiler is hazard free.
The execution flow shown in Figure 14
uses notation defined in
Specification notation on page 109
. Additional functions that have been used to abstract out details are described in
.
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Bundle fetch, decode, and execute
Start
BUNDLE_PC ZeroExtend
32
(PC);
Yes
Debug interrupt?
Yes
Bus error?
Yes
No
Interrupt?
Data Cache?
No
Yes
THROW
STBUS_IC_ERROR
THROW
STBUS_DC_ERROR
No
Fetch bundle from memory
No
THROW
EXTERN_INT
NumWords(PC) > 4 Yes
THROW
ILL_INST
No
NUM_OPERS NumWords(PC) - NumExtImms(PC);
BUNDLE_SIZE NumWords(PC) x 4;
PC Register(BUNDLE_PC + BUNDLE_SIZE);
REPEAT oper FROM 1 FOR NUM_OPERS
Pre-commit(oper);
InitiateDebugIntHandler();
Exception detected?
Yes
No
REPEAT oper FROM 1 FOR NUM_OPERS
Commit(oper);
InitiateExceptionHandler();
Figure 14: Execution model
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15.3 Functions
The flow chart, Figure 14 , contains a number of functions which abstract out some
the details. Those functions are described in this section. Starting with those used in the decode phase, then execution of operations, and finally the exceptional cases.
15.3.1 Bundle decode
Function
NumWords(address)
NumExtImms(address)
Description
Returns the number of words in the bundle. The return value is equal to the number of contiguous words, starting from address , without their stop bit set + 1.
Returns the number of extended immediates in the bundle starting at address .
Table 28: Bundle decode functions
15.3.2 Operation execution
Pre-commit(n)
Function
Commit(n)
Description
For the operation n th
operation in the bundle, execute the
Pre-commit phase ( Section 17.3
a
.
For the operation n th
operation in the bundle, execute the Commit
)
Table 29: Operation execution functions a. Where n is in the range [1 .. number of operations in the bundle] inclusive.
15.3.3 Exceptional cases
Function
InitiateExceptionHandler()
InitiateDebugIntHandler()
Description
Execute the statements defined in
Section 5.3: Saved execution state on page 32 .
Execute the statements defined in
Debug interrupt handling on page 86
.
Table 30: Operation execution functions
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Specification notation
16.1 Overview
The language used to describe the operations, exceptions and interrupts has the following features:
•
a simple variable and type system (see Section 16.2
),
•
expressions (see
),
•
•
notation for the architectural state of the machine (see Section 16.5
Additional mechanisms are defined to model memory (
).
Each instruction is described using informal text as well as the formal language.
Sometimes it is inappropriate for one of these descriptions to convey the full semantics. In such cases the two descriptions must be taken together to constitute the full specification. In the case of an ambiguity or a conflict, the notational language takes precedence over the text.
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16.2 Variables and types
Variables are used to hold state. The type of a variable determines the set of values that the variable can take and the available operators. The scalar types are integers, booleans and bit-fields. One-dimensional arrays of scalar types are also supported.
The architectural state of the machine is represented by a set of variables. Each of these variables has an associated type, which is either a bit-field or an array of bit-fields. Bit-fields are used to give a bit-accurate representation.
Additional variables are used to hold temporary values. The type of temporary variables is determined by their context rather than explicit declaration. The type of a temporary variable is an integer, a boolean or an array of these.
16.2.1 Integer
An integer variable can take the value of any mathematical integer. No limits are imposed on the range of integers supported. Integers obey their standard mathematical properties. Integer operations do not overflow. The integer operators are defined so that singularities do not occur. For example, no definition is given to the result of divide by zero; the operator is simply not available when the divisor is zero.
The representation of literal integer values is achieved using the following notations:
•
Unsigned decimal numbers are represented by the regular expression: [0-9]+
•
Signed decimal numbers are represented by the regular expression: -[0-9]+
•
Hexadecimal numbers are represented by the regular expression:
0x[0-9a-fA-F]+
•
Binary numbers are represented by the regular expression: 0b[0-1]+
These notations are standard and map onto integer values in the obvious way.
Underscore characters (‘ _ ’) can be inserted into any of the above literal representations. These do not change the represented value but can be used as spacers to aid readability.
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16.2.2 Boolean
A boolean variable can take two values:
•
Boolean false. The literal representation of boolean false is FALSE .
•
Boolean true. The literal representation of boolean true is TRUE .
16.2.3 Bit-fields
Bit-fields are provided to define ‘bit-accurate’ storage.
Bit-fields containing arbitrary numbers of bits are supported. A bit-field of b bits contains bits numbered from 0 (the least significant bit) up to b-1 (the most significant bit). Each bit can take the value 0 or the value 1 .
Bit-fields are mapped to, and from, unsigned integers in the usual way. If bit i of a b -bit bit-field, where i is in [0, b) , is set then it contributes 2 i
to the integral value of the bit-field. The integral value of the bit-field as a whole is an integer in the range
[0, 2 b
) .
Bit-fields are mapped to, and from, signed integers using two’s complement representation. This is as above, except that the bit b-1 of a b -bit bit-field contributes -2
(b-1)
to the integral value of the bit-field. The integral value of the bit-field as a whole is an integer in the range [-2 b-1
, 2 b-1
) .
A bit-field may be used in place of an integer value. In this case the integral value of the bit-field is used. A bit-field variable may be used in place of an integer variable as the target of an assignment. In this case the integer must be in the range of values supported by the bit-field.
16.2.4 Arrays
One-dimensional arrays of the above types are also available. Indexing into an n -element array A is achieved using the notation A[i] where A is an array of some type and i is an integer in the range [0, n) . This selects the i th.
element of the array
A . If i is zero this selects the first entry, and if i is n-1 then this selects the last entry.
The type of the selected element is the base type of the array.
Multi-dimensional arrays are not provided.
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16.3 Expressions
Expressions are constructed from monadic operators, dyadic operators and functions applied to variables and literal values.
There are no defined precedence and associativity rules for the operators.
Parentheses are used to specify the expression unambiguously.
Sub-expressions can be evaluated in any order. If a particular evaluation order is required, then sub-expressions must be split into separate statements.
16.3.1 Integer arithmetic operators
Since the notation uses straightforward mathematical integers, the set of standard mathematical operators is available and already defined.
The standard dyadic operators are listed in Table 31
.
i + j i - j i
× j i / j i \ j
*
Operation Description
Integer addition
Integer subtraction
Integer multiplication
Integer division*
Integer remainder*
These operators are defined only for j <> 0
Table 31: Standard dyadic operators
The standard monadic operators are described in
.
- i
|i|
Operator Description
Integer negation
Integer modulus (absolute value)
Table 32: Standard monadic operators
The division operator truncates towards zero. The remainder operator is consistent with this. The sign of the result of the remainder operator follows the sign of the dividend. Division and remainder are not defined for a divisor of zero.
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Expressions
For a numerator ( n ) and a denominator ( d ), the following properties hold where d ≠ 0 :
0
≤ (
– n n
⁄
= d d
–
= n
×
\
( d n
⁄
= d
– ( n ⁄ d )
)
+
=
( n \ d
)
–
( n \ d
) n ⁄ n \ d
) < d
– n \ – d = n \ d where n
≥
0 and d
>
0
113
16.3.2 Integer shift operators
The available integer shift operators are listed in
.
n << b n >> b
Operation Description
Integer left shift
Integer right shift
Table 33: Shift operators
The shift operators are defined on integers as follows where b ≥ 0 : n « b = n
×
2 b n » b = n
⁄
2 b
( n – 2 b
+ 1
) ⁄
2 b where where n
≥
0 n
<
0
Note that right shifting by b places is a division by 2 b
but with the result rounded towards minus infinity. This contrasts with division, which rounds towards zero, and is the reason why the right shift definition is separate for positive and negative n .
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16.3.3 Integer bitwise operators
The available integer bitwise operators are listed in
.
i ∧ j i
∨
j i
⊕
j
~ i
Operation n
<b FOR m> n
<b>
Description
Integer bitwise AND
Integer bitwise OR
Integer bitwise XOR
Integer bitwise NOT
Integer bit-field extraction: extract m bits starting at bit b from integer n
Integer bit-field extraction: extract 1 bit starting at bit b from integer n
Table 34: Bitwise operators
In order to define bitwise operations all integers are considered as having an infinitely long two’s complement representation. Bit 0 is the least significant bit of this representation, bit 1 is the next higher bit, and so on. The value of bit b , where b ≥ 0 , in integer n is given by:
BIT ( n b ) =
( n
⁄
2 b
)
\2
BIT ( n b ) = 1 – BIT ( ( – n – 1
) , b ) where where n
≥
0 n
<
0
Care must be taken whenever the infinitely long two’s complement representation of a negative number is constructed. This representation will contain an infinite number of higher bits with the value 1 representing the sign. Typically, a subsequent conversion operation is used to discard these upper bits and return the result back to a finite value.
Bitwise AND ( ∧ ), OR ( ∨ ), XOR ( ⊕ ) and NOT ( ∼ ) are defined on integers as follows, where b takes all values such that b ≥ 0 :
BIT ( i
∧ j
, b ) = BIT ( i b )
×
BIT ( j b )
BIT ( i ∨ j , b ) = BIT ( i ∧ j , b ) + BIT ( i ⊕ j , b )
BIT ( i
⊕ j
, b ) =
(
BIT ( i b ) + BIT ( j b )
)
\2
( i b ) = 1 – BIT ( i b )
Note that bitwise NOT of any finite positive i will result in a value containing an infinite number of higher bits with the value 1 representing the sign.
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Expressions
Bitwise extraction is defined on integers as follows, where b ≥ 0 and m > 0 : n
⟨ b FOR m
⟩
= ( n » b ) ∧ (
2 m
– 1
) n = n
⟨ b FOR 1
⟩
The result of n
<b FOR m> is an integer in the range [0, 2 m
) .
i = j i ≠ j i < j i
>
j i ≤ i
≥
j
16.3.4 Relational operators
Relational operators are defined to compare integral values and give a boolean result.
Operation Description
Result is TRUE if i is equal to j , otherwise FALSE
Result is TRUE if i is not equal to j , otherwise FALSE
Result is TRUE if i is less than j , otherwise FALSE
Result is TRUE if i is greater than j , otherwise FALSE
Result is TRUE if i is less than or equal to j , otherwise FALSE
Result is TRUE if i is greater than or equal to j , otherwise FALSE
Table 35: Relational operators
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16.3.5 Boolean operators
Boolean operators are defined to perform logical AND , OR , XOR and NOT . These operators have boolean sources and result. Additionally, the conversion operator
INT is defined to convert a boolean source into an integer result.
Operation i AND j i OR j i XOR j
NOT i
INT i
Description
Result is TRUE if i and j are both true, otherwise FALSE
Result is TRUE if either/both i and j are true, otherwise FALSE
Result is TRUE if exactly one of i and j are true, otherwise FALSE
Result is TRUE if i is false, otherwise FALSE
Result is 0 if i is false, otherwise 1
Table 36: Boolean operators
16.3.6 Single-value functions
In some cases it is inconvenient or inappropriate to describe an expression directly in the specification language. In these cases a function call is used to reference the undescribed behavior.
A single-value function evaluates to a single value (the result), which can be used in an expression. The type of the result value can be determined by the expression context from which the function is called. There are also multiple-value functions which evaluate to multiple values. These are only available in an assignment context, and are described in
Section 16.4.2: Assignment on page 118
.
Functions can contain side-effects.
Arithmetic functions
Function
CountLeadingZeros(i)
Description
Convert integer i to 32-bit bitfield and return the number of leading zeros in the bitfield. For example:
If i
<31>
is 1 then the return value is 0.
If all bits are 0 then the return value is 32 .
Table 37: Arithmetic functions
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Scalar conversions
Two monadic functions are defined to support conversion from integers to bit-limited signed and unsigned number ranges. For a bit-limited integer representation containing n bits, the signed number range is [-2 n-1
, 2 n-1
) while the unsigned number range is [0, 2 n
) .
These functions are often used to convert between signed and unsigned bit-limited integers and between bit-fields and integer values.
Function
ZeroExtend n
(i)
SignExtend n
(i)
Description
Convert integer i to an n -bit 2’s complement unsigned range
Convert integer i to an n -bit 2’s complement signed range
Table 38: Integer conversion operators
These two functions are defined as follows, where n > 0 :
ZeroExtend n i = i ⟨
0 FOR n
⟩
SignExtend n
= i
⟨ i
⟨
0 FOR n ⟩
0 FOR
( n – 1
) ⟩
– 2 n where i
⟨ n – 1
⟩
= 0 where i
⟨ n – 1
⟩
= 1
For syntactic convenience, conversion functions are also defined for converting an integer or boolean to a single bit and to a value which can be stored as a 32-bit
register. Table 39 shows the additional functions provided.
Bit(i)
Operation
Register(i)
Description
If i is a boolean, then this is equivalent to Bit(INT i) .
Otherwise, convert lowest bit of integer i to a 1-bit value
This is a convenient notation for i
<0>
If i is a boolean, then this is equivalent to Register(INT i) .
Otherwise, convert lowest 32 bits of integer i to an unsigned 32-bit value
This is a convenient notation for i
<0 FOR 32>
Table 39: Conversion operators from integers to bit-fields
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16.4 Statements
An instruction specification consists of a sequence of statements. These statements are processed sequentially in order to specify the effect of the instruction on the architectural state of the machine. The available statements are discussed in this section.
Each statement has a semi-colon terminator. A sequence of statements can be aggregated into a statement block using ‘ { ’ to introduce the block and ‘ } ’ to terminate the block. A statement block can be used anywhere that a statement can.
16.4.1 Undefined behavior
The statement:
UNDEFINED(); indicates that the resultant behavior is architecturally undefined.
A particular implementation can choose to specify an implementation-defined behavior in such cases. It is very likely that any implementation-defined behavior will vary from implementation to implementation. Exploitation of implementation-defined behavior should be avoided to allow software to be portable between implementations.
In cases where architecturally undefined behavior can occur in user mode, the implementation will ensure that implemented behavior does not break the protection model. Thus, the implemented behavior will be some execution flow that is permitted for that user mode thread.
16.4.2 Assignment
The ‘ ← example assignment statement is: variable
←
The expression can be constructed from variables, literals, operators and functions as described in
Section 16.3: Expressions on page 112 . The expression is fully
evaluated before the assignment takes place. The variable can be an integer, a boolean, a bit-field or an array of one of these types.
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Assignment to architectural state
This is where the variable is part of the architectural state (as described in
Table 40: Scalar architectural state on page 122 ). The type of the expression and the
type of the variable must match, or the type of the variable must be able to represent all possible values of the expression.
Assignment to a temporary
Alternatively, if the variable is not part of the architectural state, then it is a temporary variable. The type of the variable is determined by the type of expression.
A temporary variable must be assigned to, before it is used in the instruction specification.
Assignment of an undefined value
An assignment of the following form results in a variable being initialized with an architecturally undefined value: variable
←
After assignment the variable will hold a value which is valid for its type. However, the value is architecturally undefined. The actual value can be unpredictable; that is to say the value indicated by UNDEFINED can vary with each use of
UNDEFINED . Architecturally-undefined values can occur in both user and privileged modes.
A particular implementation can choose to specify an implementation-defined value in such cases. It is very likely that any implementation-defined values will vary from implementation to implementation. Exploitation of implementation-defined values should be avoided to allow software to be portable between implementations.
Assignment of multiple values
Multi-value functions are used to return multiple values, and are only available when used in a multiple assignment context. The syntax consists of a list of comma-separated variables, an assignment symbol followed by a function call. The function is evaluated and returns multiple results into the variables listed. The number of variables and the number of results of the function must match. The assigned variables must all be distinct (that is, no aliases).
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For example, a two-valued assignment from a function call with 3 parameters can be represented as: variable1, variable2
←
16.4.3 Conditional
Conditional behavior is specified using IF , ELSE IF and ELSE .
Conditions are expressions that result in a boolean value. If the condition after an
IF is true, then its block of statements is executed and the whole conditional then completes. If the condition is false, then any ELSE IF clauses are processed, in turn, in the same fashion. If no conditions are met and there is an ELSE clause then its block of statements is executed. Finally, if no conditions are met and there is no
ELSE clause, then the statement has no effect apart from the evaluation of the condition expressions.
The ELSE IF and ELSE clauses are optional. In ambiguous cases, the ELSE matches with the nearest IF .
For example:
IF (condition1) block1
ELSE IF (condition2) block2
ELSE block3
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16.4.4 Repetition
Repetitive behavior is specified using the following construct:
REPEAT i FROM m FOR n STEP s block
The block of statements is iterated n times, with the integer i taking the values: m, m + s, m + 2s, m + 3s, up to m + (n - 1) × s .
The behavior is equivalent to textually writing the block n times with i being substituted with the appropriate value in each copy of the block.
The value of n must be greater or equal to 0 , and the value of s must be non-zero.
The values of the expressions for m , n and s must be constant across the iteration.
The integer i must not be assigned to within the iterated block. The STEP s can be omitted in which case the step-size takes the default value of 1 .
16.4.5 Exceptions
Exception handling is triggered by a THROW statement. When an exception is thrown, no further statements are executed from the operation specification; no architectural state is updated. Furthermore, if any one of the operations in a bundle triggers an exception then none of the operations will update any architectural state.
If any operation in a bundle triggers an exception then an exception will be taken.
The actions associated with the taking of an exception are described in Section 5.2
.
There are two forms of throw statement:
THROW type; and:
THROW type, value; where type indicates the type of exception which is launched, and value is an optional argument to the exception handling sequence. If value is not given, then it is UNDEFINED .
The exception types and priorities are described in detail in
Chapter 5: Traps: exceptions and interrupts on page 31
.
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16.4.6 Procedures
Procedure statements contain a procedure name followed by a list of comma-separated arguments contained within parentheses followed by a semi-colon. The execution of procedures typically causes side-effects to the architectural state of the machine.
Procedures are generally used where it is difficult or inappropriate to specify the effect of an instruction using the abstract execution model. A fuller description of the effect of the instruction will be given in the surrounding text.
An example procedure with two parameters is: proc(param1, param2);
16.5 Architectural state
Chapter 3: Architectural state on page 25 contains a full description of the visible
state. The notations used in the specification to refer to this state are summarized in
and
. Each item of scalar architectural state is a bit-field of a particular width. Each item of array architectural state is an array of bit-fields of a particular width.
PC
LR
Architectural state
PSW
SAVED _ PC
SAVED _ PSW
SAVED _ SAVED _ PC
SAVED _ SAVED _ PSW
R
I
where i is in [0, 63]
Type is a bit-field containing:
Description
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
32 bits
Program counter; address of the current bundle
Program Status Word
Copy of the PC used during interrupts
Copy of the PSW used during interrupts
Copy of the PC used during debug interrupts
Copy of the PSW used during debug interrupts
64 x 32-bit general purpose registers
R0 reads as zero
Assignments to R0 are ignored
Link Register, synonym for R63
Table 40: Scalar architectural state
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B
I
Architectural state where i is in [0, 7]
Type is a bit-field containing:
1 bit
Description
8 x 1-bit Branch Registers
Table 40: Scalar architectural state
CR
I
Architectural state
where i is index of the control register
MEM[i] where i is in [0, 2
32
)
Type is an array of bitfields each containing:
32 bits
8 bits
Description
Control Registers, for which some specifications refer to individual control registers by their
names as defined in the Chapter 9: Control registers on page 65.
2
32
bytes of memory
Table 41: Array architectural state
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16.6 Memory and control registers
16.6.1 Support functions
The following functions are used in the memory and control register descriptions.
Function
DataBreakPoint(address)
Misaligned n
(address)
DPUNoTranslation(address)
DPUSpecLoadRetZero(address)
ReadAccessViolation(address)
WriteAccessViolation(address)
IsCRegSpace(address)
UndefinedCReg(address)
CRegIndex(address)
CRegReadAccessViolation(index)
CRegWriteAccessViolation(index)
BusReadError(address)
IsDBreakHit(address)
Description
Result is TRUE if address is in the range defined by data breakpoint control mechanism (
Chapter 6: Memory access protection units on page 39 ), otherwise
FALSE
Result is TRUE if address is not n -bit aligned, otherwise FALSE
Result is TRUE if the DPU has no mapping for address , otherwise
FALSE
Result is TRUE if the region containing address has the S bit of its
attribute field set ( Chapter 6: Memory access protection units on page 39 ), otherwise
FALSE
Result is TRUE if read access to address is not permitted by the
DPU, otherwise FALSE
Result is TRUE if write access to address is not permitted by the
DPU, otherwise FALSE
Result is TRUE if address is in the control register space, otherwise FALSE
Result is TRUE if address does not correspond to a defined control register, otherwise FALSE
Returns the index of the control register which maps to address
Result is TRUE if read access is not permitted to the given control register, otherwise FALSE
Result is TRUE if write access is not permitted to given control register, otherwise FALSE
Result is TRUE if reading from address generates a Bus Error, otherwise FALSE
Result is TRUE if address will trigger a data breakpoint, otherwise it is FALSE
Table 42: Support functions
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16.6.2 Memory model
The instruction specification uses a simple model of memory. It assumes, for example, that any caches are not architecturally visible. However, a fuller description of the behavior in other cases is defined by the text of the architecture manual.
Array slicing can be used to view an array as consisting of elements of a larger size.
The notation MEM[s FOR n] , where n > 0 , denotes a memory slice containing the elements MEM[s] , MEM[s+1] through to MEM[s+n-1] . The type of this slice is a bit-field exactly large enough to contain a concatenation of the n selected elements.
In this case it contain 8n bits since the base type of MEM is byte.
The order of the concatenation depends on the endianness of the processor:
•
If the processor is operating in a little endian mode, the concatenation order obeys the following condition as i (the byte number) varies in the range [0, n) :
(
MEM
[ s FOR n ] )
⟨
8 i FOR 8
⟩
= MEM
[ s + i ]
This equivalence states that byte number i , using little endian byte numbering
(that is, byte 0 is bits 0 to 7 ), in the bit-field MEM[s FOR n] is the i th.
byte in memory counting upwards from MEM[s] .
•
If the processor is operating in a big endian mode, the concatenation order obeys the following condition as i (the byte number) varies in the range [0, n) :
(
MEM
[ s FOR n ] )
⟨
8
( n – 1 – i
)
FOR 8
⟩
= MEM
[ s + i ]
This equivalence states that byte number i , using big endian byte numbering
(that is, byte 0 is bits 8n-8 to 8n-1 ), in the bit-field MEM[s FOR n] is the i th.
byte in memory counting upwards from MEM[s] .
For syntactic convenience, functions and procedures are provided to read and write memory.
Support functions
The specification of the memory instructions relies on the support functions listed in
. These functions are used to model the behavior of the Data
Protection Unit and Instruction Protection Unit described in
Chapter 6: Memory access protection units on page 39
.
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Reading memory
The following functions are provided to support the reading of memory:
Function Description
ReadCheckMemory n
(address) Throws any non-BusError exception generated by an n -bit read from address
ReadMemory n
(address)
DisReadMemory n
(address)
Issues an n -bit read to
DisReadCheckMemory n
(address) Throws any non-BusError exception generated by an n -bit dismissible read from address
Returns either exception) n address
-bits from
(can generate BusError exception) address or 0 (can generate BusError
ReadMemResponse() Returns the value of the read request issued
Table 43: Memory read functions
The ReadCheckMemory n
procedure takes an integer parameter to indicate the address being accessed. The number of bits being read ( n ) is one of 8 , 16 , or 32 . The procedure throws any alignment or access violation exceptions generated by a read access to that address.
ReadCheckMemory n
(a); is equivalent to:
IF (Misaligned n
(a))
THROW MISALIGNED_TRAP, a;
IF (PSW[DPU_ENABLE]) {
IF (DPUNoTranslation(a))
THROW DPU_NO_TRANSLATION, a;
IF (ReadAccessViolation(a))
THROW DPU_ACCESS_VIOLATION, a;
}
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Similarly, if the memory access is a dismissible read:
DisReadCheckMemory n
(a); is equivalent to:
IF (Misaligned n
(a) AND PSW[SPECLOAD_MALIGNTRAP_EN])
THROW MISALIGNED_TRAP, a;
IF (PSW[DPU_ENABLE] AND PSW[SPECLOAD_DPUTRAP_EN]) {
IF (DPUNoTranslation(a))
THROW DPU_NO_TRANSLATION, a;
IF (ReadAccessViolation(a) AND NOT DPUSpecLoadRetZero(a))
THROW DPU_ACCESS_VIOLATION, a;
}
The ReadMemory n
procedure takes an integer parameter to indicate the address being accessed. The number of bits being read ( n ) is one of 8 , 16 , or 32 . The required bytes are read from memory, interpreted according to endianness, and the read bit-field value assigned to a temporary integer. If the read memory value is to be interpreted as signed, then a sign-extension should be used when accessing the result using ReadMemResponse . The procedure call:
ReadMemory n
(a); is equivalent to: width
←
IF (BusReadError(a))
THROW BUS_DC_ERROR, a; // Non-recoverable mem_response
←
MEM[a FOR width];
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The DisReadMemory n performs the same functionality for a dismissible read from memory. The procedure call:
DisReadMemory n
(a); is equivalent to: width
←
IF (NOT DPUSpecLoadRetZero(a) AND
NOT Misaligned n
(a) AND
NOT ReadAccessViolation(a)) {
IF (BusReadError(a))
THROW BUS_DC_ERROR, a; // Non-recoverable mem_response
←
MEM[a FOR width];
}
ELSE mem_response
←
0;
The function ReadMemResponse returns the data that will have been read from memory. The assignment: result
← is equivalent to: result
←
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Prefetching memory
The following procedure is provided to denote memory prefetch.
Function
PrefetchMemory(address)
Description
Prefetch memory if possible.
Table 44: Memory prefetch procedure
This is used for a software-directed data prefetch from a specified effective address.
This is a hint to give advance notice that particular data will be required.
PrefetchMemory , performs the implementation-specific prefetch when the address is valid:
PrefetchMemory(a); equivalent to:
IF (PSW[DPU_ENABLE])
IF (NOT DPUNoTranslation(a) AND NOT ReadAccessViolation(a))
Prefetch(a); where Prefetch is a cache operation defined in
Section 16.6.4: Cache model on page 133 . Prefetching memory will not generate any exceptions.
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Writing memory
The following procedures are provided to write memory.
Function
WriteCheckMemory n
(address)
WriteMemory n
(address, value)
Description
Throws any exception generated by an n -bit write to address
Aligned n -bit write to memory
Table 45: Memory write procedures
The WriteCheckMemory n
procedure takes an integer parameter to indicate the address being accessed. The number of bits being written ( n ) is one of 8 , 16 , or 32 .
The procedure throws any alignment or access violation exceptions generated by a write access to that address.
WriteCheckMemory n
(a); is equivalent to:
IF (Misaligned n
(a))
THROW MISALIGNED_TRAP, a;
IF (PSW[DPU_ENABLE]) {
IF (DPUNoTranslation(a))
THROW DPU_NO_TRANSLATION, a;
IF (WriteAccessViolation(a))
THROW DPU_ACCESS_VIOLATION, a;
}
The WriteMemory n
procedure takes an integer parameter to indicate the address being accessed, followed by an integer parameter containing the value to be written.
The number of bits being written ( n ) is one of 8 , 16 , 32 or 64 bits. The written value is interpreted as a bit-field of the required size; all higher bits of the value are discarded. The bytes are written to memory, ordered according to endianness. The statement:
WriteMemory n
(a, value); is equivalent to: width
←
MEM[a FOR width]
← value
<0 FOR n>
;
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16.6.3 Control register model
Reading control registers
The following procedures are provided to read from control registers.
Note: Only word (32-bit) control register accesses are supported.
Function Description
ReadCheckCReg(address)
ReadCReg(address)
Throws any exception generated by reading from address in the control register space
Issues a read from the control register mapped to address
Table 46: Control register read functions
The ReadCheckCReg procedure takes an integer parameter to indicate the address being accessed. The procedure throws any alignment or non-mapping exception generated by reading from the control register space.
ReadCheckCReg(a); is equivalent to:
IF (UndefinedCReg(a))
THROW CREG_NO_MAPPING, a; index
←
CRegIndex(a);
IF (CRegReadAccessViolation(index))
THROW CREG_ACCESS_VIOLATION, a;
The control register file is denoted CR . The function ReadCReg is provided:
ReadCReg(a); is equivalent to: index
←
CRegIndex(a); mem_response
←
CR index
;
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Writing control registers
The following procedures are provided to read from control registers. Note that only word (32-bit) control register accesses are supported
Function
WriteCheckCReg(address)
WriteCReg(address, value)
Description
Throws any exception generated by writing to the address in the control register space
Writes value to the control register mapped to address
Table 47: Control registers write procedures
The WriteCheckCReg procedure takes an integer parameter to indicate the address being accessed. The procedure throws any alignment, non-mapping or access violation exceptions generated by writing to the control register space:
WriteCheckCReg(a); is equivalent to:
IF (UndefinedCReg(a))
THROW CREG_NO_MAPPING, a; index
←
CRegIndex(a);
IF (CRegWriteAccessViolation(index))
THROW CREG_ACCESS_VIOLATION, a;
A procedure called WriteCReg is provided to write control registers:
WriteCReg(a, value); is equivalent to: index
←
CRegIndex(a);
CR index
← value;
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16.6.4 Cache model
Cache operations are used to prefetch and purge lines in caches. The effects of these operations are beyond the scope of the specification language, and are therefore modelled using procedure calls. The behavior of these procedure calls is elaborated
in the Chapter 7: Memory subsystem on page 47 .
Procedure
PurgeIns( )
Sync( )
PurgeAddress(address)
PurgeSet(address)
Prefetch(address)
Description
Invalidate the entire instruction cache
Data memory subsystem synchronization function
Purge address from the data cache
Purge a set of lines from the data cache
Prefetch a data cache line if it is in cachable memory
Table 48: Procedures to model cache operations
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Instruction set
17.1 Introduction
This chapter contains descriptions of all the operations and macros
(pseudo-operations) in the ST220 instruction set. Section 17.2
order to describe how operations are encoded in the context of bundles.
17.2 Bundle encoding
An instruction bundle consists of between one and four consecutive 32-bit words, known as syllables. Each syllable encodes either an operation or an extended immediate. The most significant bit of each syllable (bit 31) is a stop bit which is set to indicate that it is the last in the bundle.
A syllable will therefore look like:
0 31 30 29 stop bit reserved operation
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17.2.1 Extended immediates
Many operations have an Immediate form. In general only small (9-bit) immediates can be directly encoded in a single word syllable. In the event that larger immediates are required, an immediate extension is used. This extension is encoded in an adjacent word in the bundle, making the operation effectively a two-word operation.
These immediate extensions associate either with the operation to their left or their right in the bundle. Bit 23 is used to indicate the association: imml immr s s
010101
010101
0
1 extension extension
Figure 15:
The semantic descriptions of Immediate form operations use the following function to take into account possible immediate extensions:
Imm(i)
Function Description
Given short immediate value i , returns an integer value that represents the full immediate.
Table 49: Extended immediate functions
This function effectively performs the following:
If there is an immr word to the left (word address - 1) or an imml word to the right
(word address + 1) in the bundle, then Imm returns:
(ZeroExtend
23
(extension) << 9) + ZeroExtend
9
(i);
Where extension represents the lower 23 bits of the associated immr or imml .
Otherwise Imm returns:
SignExtend
9
(i);
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17.2.2 Encoding restrictions
There are a number of restrictions placed on the encoding of bundles. It is the duty of the assembler to ensure that these restriction are obeyed.
1 Long immediates must be encoded at even word addresses.
2 Multiply operations must be encoded at odd word addresses.
3 There may only be one control flow operation per bundle, and it must be the first syllable.
4 There may only be one load or store operation per bundle.
17.3 Operation specifications
The specification of each operation contains the following fields:
•
Name: The name of the operation with an optional subscript. The subscript is used to distinguish between operations with different operand types. For example, there are Register and Immediate format integer operations. If no subscript is used, then there is only one format for the operation.
•
Syntax: Presents the assembly syntax of the operation ( ST200 Programming
Manual ).
•
Encoding: The binary encoding is summarized in a table. It shows which bits are used for the opcode, which bits are reserved (empty fields) and which bit-fields encode the operands. The operands will either be register designators or immediate constants.
•
Semantics: A table containing the statements ( Section 16.4
) that define the
operation. The notation used is defined in Chapter 16 on page 109
. The table is divided into two parts by the commit point:
Pre-commit phase:
•
No architectural state of the machine is updated.
•
Any recoverable exceptions will be thrown here.
Commit phase - executed if no exceptions have been thrown:
← Commit point
•
All architectural state is updated.
•
Any exceptions thrown here are non-recoverable a
.
a. For the ST220 the only non-recoverable exception is a bus error.
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•
Description: A brief textual description of the operation.
•
Restrictions: Contains any details of restrictions, these may be of the following types:
-
Address/Bundle: In encoding a bundle with the operation there are a number of possible restrictions which may apply. They are detailed in
.
-
Latency: Certain operands have latency constraints that must be observed.
-
Destination restrictions: Certain operations are not allowed to use the Link
Register (
LR
) as a destination.
•
Exceptions: If this operation is able to throw any exceptions, they will be listed here. The semantics of the operation will detail how and when they are thrown.
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Example operations
17.4 Example operations
17.4.1 add Immediate
The specification for this operation is shown below:
add
Immediate add R
IDEST
= R
SRC
1
, ISRC 2 s 0010 00000 ISRC 2 IDEST SRC 1
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 )); result ← operand1 + operand2;
R
IDEST
← Register(result);
Description:
Add
Restrictions:
No address/bundle restrictions.
No latency constraints.
The operation is given the subscript Immediate to indicate that one of its source operands is an immediate rather than both being registers.
The next line of the description shows the assembly syntax of the operation.
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Just below is the binary encoding table with fields showing:
•
The opcode: Bits 29:21.
•
The operands: An s
in bit 31 represents the stop bit ( Section 17.2
-
The 9-bit immediate constant, bits 20:12.
-
The destination register designator, bits 11:6.
-
The source register designator, bits 5:0.
•
Unused bits: Bit 30.
The semantics table specifies the effects of the executing this operation. The table is divided into two parts. The first half containing statements which do not affect the architectural state of the machine. The second half containing statements that will not be executed if an exception occurs in the bundle.
The statements themselves are organized into 3 stages as follows:
1 The first 2 statements read the required source information: operand1
←
SignExtend
32
( R
SRC 1
); operand2
←
SignExtend
32
(Imm( ISRC 2 ));
The first statement reads the value of the R
SRC 1
register, interprets it as a signed
32-bit value and assigns this to a temporary integer called operand1 . The second statement passes the value of ISRC 2 to the immediate handling function
Imm
). The result of the function is interpreted as a signed 32-bit value and assigned to a temporary integer called operand2 .
2 The next statement implements the addition: result
← operand1 + operand2;
This statement does not refer to any architectural state. It adds the 2 integers operand1 and operand2 together, and assigns the result to a temporary integer called result . Note that since this is a conventional mathematical addition, the result can contain more significant bits of information than the sources.
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Macros 141
3 The final statement, executed if no exceptions have been thrown in the bundle, updates the architectural state:
R
IDEST
←
Register(result);
The function Register (
) converts the integer result back to a bit-field, discarding any redundant higher bits. This value is then assigned to the R
IDEST
register.
After the semantic description is a simple textual description of the operation.
The section listing restrictions for this operation shows that it has no restrictions at all. This means that up to four of these operations can be used in a bundle, and that all operands will be ready for use by operations in the next bundle.
Finally, this operation can not generate any exceptions.
17.5 Macros
The following are the currently implemented pseudo-operations.
nop mov mtb mov zxtb mfb syncins s s s s s s s
00 0 0 00000
00 0 0 00000
00 0 1 1 1100
00 1 0
00 1 0
00000
01001
01 1 001 SCOND
11 0 001 0
000000
DEST
000000
SRC 2
000000 BDEST
ISRC 2
011111111
IDEST
IDEST
000000001 IDEST
00000000000000000000001
Figure 16: Macros
000000
000000
SRC 1
000000
SRC 1
000000
17.6 Operations
Each operation is now specified. They are listed alphabetically for ease of use. The semantics of the operations are written using the notational language defined in
.
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add
Register s add R
DEST
= R
SRC 1
, R
SRC 2
00 0 0 00000 DEST
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2 result ← operand1 + operand2;
);
R
DEST
← Register(result);
Description:
Add
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 2 SRC 1
Operations
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Operations
add
Immediate s add R
IDEST
= R
SRC 1
, ISRC 2
00 1 0 00000 ISRC 2
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 )); result ← operand1 + operand2;
R
IDEST
← Register(result);
Description:
Add
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
IDEST SRC 1
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addcg
s addcg R
DEST
, B
BDEST
= R
SRC 1
, R
SRC 2
, B
SCOND
01 0010 SCOND BDEST DEST SRC 2
Semantics: operand1 ← ZeroExtend
32
( R
SRC operand2 ← ZeroExtend
32
( R
SRC
1
);
2
); carryin ← ZeroExtend
1
( B
SCOND
); result ← (operand1 + operand2) + carryin; carryout ← Bit(result, 32);
R
DEST
← Register(result);
B
BDEST
← Bit(carryout);
Description:
Add with carry and generate carry
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 1
Operations
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Operations
and
Register s and R
DEST
= R
SRC 1
, R
SRC 2
00 0 0 01001 DEST
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2 result ← operand1 ∧ operand2;
);
R
DEST
← Register(result);
Description:
Bitwise and
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 2 SRC 1
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and
Immediate s and R
IDEST
= R
SRC 1
, ISRC 2
00 1 0 01001 ISRC 2
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 )); result ← operand1 ∧ operand2;
R
IDEST
← Register(result);
Description:
Bitwise and
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
IDEST SRC 1
Operations
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Operations
andc
Register s andc R
DEST
= R
SRC 1
, R
SRC 2
00 0 0 01010 DEST
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2
); result ← (~ operand1) ∧ operand2;
R
DEST
← Register(result);
Description:
Complement and bitwise and
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 2 SRC 1
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andc
Immediate s andc R
IDEST
= R
SRC 1
, ISRC 2
00 1 0 01010 ISRC 2
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 )); result ← (~ operand1) ∧ operand2;
R
IDEST
← Register(result);
Description:
Complement and bitwise and
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
IDEST SRC 1
Operations
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Operations
andl
Register - Register s andl R
DEST
= R
SRC 1
, R
SRC 2
00 0 1 0 1010 DEST
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2
); result ← (operand1 ≠ 0) AND (operand2 ≠ 0);
R
DEST
← Register(result);
Description:
Logical and
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 2 SRC 1
149
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andl
Branch Register - Register s andl B
BDEST
= R
SRC 1
, R
SRC 2
00 0 1 1 1010 BDEST SRC 2
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2
); result ← (operand1 ≠ 0) AND (operand2 ≠ 0);
B
BDEST
← Bit(result);
Description:
Logical and
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
andl
Register - Immediate s andl R
IDEST
= R
SRC 1
, ISRC 2
00 1 1 0 1010 ISRC 2
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 )); result ← (operand1 ≠ 0) AND (operand2 ≠ 0);
R
IDEST
← Register(result);
Description:
Logical and
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
IDEST SRC 1
151
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andl
Branch Register - Immediate s andl B
IBDEST
= R
SRC 1
, ISRC 2
00 1 1 1 1010 ISRC 2 IBDEST SRC 1
Operations
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 )); result ← (operand1 ≠ 0) AND (operand2 ≠ 0);
B
IBDEST
← Bit(result);
Description:
Logical and
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
br
s br B
BCOND
, BTARG
11 1 0 BCOND BTARG
Semantics: operand1 ← ZeroExtend
1
( B
BCOND
); operand2 ← SignExtend
23
( BTARG );
IF (operand1 ≠ 0)
PC ← Register(ZeroExtend
32
(BUNDLE_PC) + (operand2 << 2));
153
Description:
Branch
Restrictions:
Must be the first syllable of a bundle.
Instructions writing B
BCOND
must be followed by 2 bundles before this instruction can be issued.
Exceptions:
None.
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154
break
s break
01 1111111
Semantics:
THROW ILL_INST;
Description:
Break
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
ILL_INST
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
brf
s brf B
BCOND
, BTARG
11 1 1 BCOND BTARG
Semantics: operand1 ← ZeroExtend
1
( B
BCOND
); operand2 ← SignExtend
23
( BTARG );
IF (operand1 = 0)
PC ← Register(ZeroExtend
32
(BUNDLE_PC) + (operand2 << 2));
155
Description:
Branch false
Restrictions:
Must be the first syllable of a bundle.
Instructions writing B
BCOND
must be followed by 2 bundles before this instruction can be issued.
Exceptions:
None.
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156
bswap
s bswap R
IDEST
= R
SRC 1
00 1 0 01110 000000010 IDEST
Semantics: operand1 ← ZeroExtend
32
( R
SRC byte0 ← operand1
< 0 FOR 8 >
; byte1 ← operand1
< 8 FOR 8 >
;
1
); byte2 ← operand1
< 16 FOR 8 > byte3 ← operand1
< 24 FOR 8 >
;
; result ← ((byte0 << 24) ∨ (byte1 << 16)) ∨ ((byte2 << 8) ∨ byte3);
R
IDEST
← Register(result);
Description:
Byte Swap
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
call
Immediate s call LR = BTARG
11 0 000 0 BTARG
Semantics: operand1
←
SignExtend
23
( BTARG );
NEXT_PC
←
PC;
PC ← Register(ZeroExtend
32
(BUNDLE_PC) + (operand1 << 2));
LR ← NEXT_PC;
Description:
Jump and link
Restrictions:
Must be the first syllable of a bundle.
No latency constraints.
Exceptions:
None.
157
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158 Operations
call
Link Register s call LR = LR
11 0 000 1
Semantics:
NEXT_PC
←
PC;
PC ← Register(ZeroExtend
LR ← NEXT_PC;
32
(LR));
Description:
Jump (using Link Register) and link
Restrictions:
Must be the first syllable of a bundle.
Instructions writing LR must be followed by 3 bundles before this instruction can be issued.
Exceptions:
None.
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
clz
s clz R
IDEST
= R
SRC 1
00 1 0 01110 000000100
Semantics: operand1 ← ZeroExtend
32
( R
SRC 1
); result ← CountLeadingZeros(operand1);
R
IDEST
← Register(result);
Description:
Count leading zeros
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
IDEST SRC 1
159
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cmpeq
Register - Register s cmpeq R
DEST
= R
SRC 1
, R
SRC 2
00 0 1 0 0000 DEST
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2 result ← operand1 = operand2;
);
R
DEST
← Register(result);
Description:
Test for equality
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 2 SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
cmpeq
Branch Register - Register s cmpeq B
BDEST
= R
SRC 1
, R
SRC 2
00 0 1 1 0000 BDEST SRC 2
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2 result ← operand1 = operand2;
);
B
BDEST
← Bit(result);
Description:
Test for equality
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 1
161
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cmpeq
Register - Immediate s cmpeq R
IDEST
= R
SRC 1
, ISRC 2
00 1 1 0 0000 ISRC 2 IDEST
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 )); result ← operand1 = operand2;
R
IDEST
← Register(result);
Description:
Test for equality
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
cmpeq
Branch Register - Immediate s cmpeq B
IBDEST
= R
SRC 1
, ISRC 2
00 1 1 1 0000 ISRC 2 IBDEST SRC 1
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 )); result ← operand1 = operand2;
B
IBDEST
← Bit(result);
Description:
Test for equality
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
163
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cmpge
Register - Register s cmpge R
DEST
= R
SRC 1
, R
SRC 2
00 0 1 0 0010 DEST
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2 result ← operand1 ≥ operand2;
);
R
DEST
← Register(result);
Description:
Signed compare equal or greater than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 2 SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
cmpge
Branch Register - Register s cmpge B
BDEST
= R
SRC 1
, R
SRC 2
00 0 1 1 0010 BDEST SRC 2
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2 result ← operand1 ≥ operand2;
);
B
BDEST
← Bit(result);
Description:
Signed compare equal or greater than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 1
165
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cmpge
Register - Immediate s cmpge R
IDEST
= R
SRC 1
, ISRC 2
00 1 1 0 0010 ISRC 2 IDEST
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 )); result ← operand1 ≥ operand2;
R
IDEST
← Register(result);
Description:
Signed compare equal or greater than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
cmpge
Branch Register - Immediate s cmpge B
IBDEST
= R
SRC 1
, ISRC 2
00 1 1 1 0010 ISRC 2 IBDEST SRC 1
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 )); result ← operand1 ≥ operand2;
B
IBDEST
← Bit(result);
Description:
Signed compare equal or greater than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
167
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cmpgeu
Register - Register s cmpgeu R
DEST
= R
SRC 1
, R
SRC 2
00 0 1 0 0011 DEST SRC 2
Semantics: operand1 ← ZeroExtend
32
( R
SRC operand2 ← ZeroExtend
32
( R
SRC result ← operand1 ≥ operand2;
1
);
2
);
R
DEST
← Register(result);
Description:
Unsigned compare equal or greater than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
cmpgeu
Branch Register - Register s cmpgeu B
BDEST
= R
SRC 1
, R
SRC 2
00 0 1 1 0011 BDEST SRC 2
Semantics: operand1 ← ZeroExtend
32
( R
SRC operand2 ← ZeroExtend
32
( R
SRC result ← operand1 ≥ operand2;
1
);
2
);
B
BDEST
← Bit(result);
Description:
Unsigned compare equal or greater than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 1
169
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cmpgeu
Register - Immediate s cmpgeu R
IDEST
= R
SRC 1
, ISRC 2
00 1 1 0 0011 ISRC 2 IDEST
Semantics: operand1 ← ZeroExtend
32
( R
SRC 1
); operand2 ← ZeroExtend
32
(Imm( ISRC 2 )); result ← operand1 ≥ operand2;
R
IDEST
← Register(result);
Description:
Unsigned compare equal or greater than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
cmpgeu
Branch Register - Immediate s cmpgeu B
IBDEST
= R
SRC 1
, ISRC 2
00 1 1 1 0011 ISRC 2 IBDEST SRC 1
Semantics: operand1 ← ZeroExtend
32
( R
SRC 1
); operand2 ← ZeroExtend
32
(Imm( ISRC 2 )); result ← operand1 ≥ operand2;
B
IBDEST
← Bit(result);
Description:
Unsigned compare equal or greater than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
171
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cmpgt
Register - Register s cmpgt R
DEST
= R
SRC 1
, R
SRC 2
00 0 1 0 0100 DEST
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2 result ← operand1 > operand2;
);
R
DEST
← Register(result);
Description:
Signed compare greater than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 2 SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
cmpgt
Branch Register - Register s cmpgt B
BDEST
= R
SRC 1
, R
SRC 2
00 0 1 1 0100 BDEST SRC 2
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2 result ← operand1 > operand2;
);
B
BDEST
← Bit(result);
Description:
Signed compare greater than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 1
173
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cmpgt
Register - Immediate s cmpgt R
IDEST
= R
SRC 1
, ISRC 2
00 1 1 0 0100 ISRC 2 IDEST
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 )); result ← operand1 > operand2;
R
IDEST
← Register(result);
Description:
Signed compare greater than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
cmpgt
Branch Register - Immediate s cmpgt B
IBDEST
= R
SRC 1
, ISRC 2
00 1 1 1 0100 ISRC 2 IBDEST SRC 1
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 )); result ← operand1 > operand2;
B
IBDEST
← Bit(result);
Description:
Signed compare greater than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
175
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cmpgtu
Register - Register s cmpgtu R
DEST
= R
SRC 1
, R
SRC 2
00 0 1 0 0101 DEST SRC 2
Semantics: operand1 ← ZeroExtend
32
( R
SRC operand2 ← ZeroExtend
32
( R
SRC result ← operand1 > operand2;
1
);
2
);
R
DEST
← Register(result);
Description:
Unsigned compare greater than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
cmpgtu
Branch Register - Register s cmpgtu B
BDEST
= R
SRC 1
, R
SRC 2
00 0 1 1 0101 BDEST SRC 2
Semantics: operand1 ← ZeroExtend
32
( R
SRC operand2 ← ZeroExtend
32
( R
SRC result ← operand1 > operand2;
1
);
2
);
B
BDEST
← Bit(result);
Description:
Unsigned compare greater than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 1
177
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cmpgtu
Register - Immediate s cmpgtu R
IDEST
= R
SRC 1
, ISRC 2
00 1 1 0 0101 ISRC 2 IDEST
Semantics: operand1 ← ZeroExtend
32
( R
SRC 1
); operand2 ← ZeroExtend
32
(Imm( ISRC 2 )); result ← operand1 > operand2;
R
IDEST
← Register(result);
Description:
Unsigned compare greater than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
cmpgtu
Branch Register - Immediate s cmpgtu B
IBDEST
= R
SRC 1
, ISRC 2
00 1 1 1 0101 ISRC 2 IBDEST SRC 1
Semantics: operand1 ← ZeroExtend
32
( R
SRC 1
); operand2 ← ZeroExtend
32
(Imm( ISRC 2 )); result ← operand1 > operand2;
B
IBDEST
← Bit(result);
Description:
Unsigned compare greater than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
179
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cmple
Register - Register s cmple R
DEST
= R
SRC 1
, R
SRC 2
00 0 1 0 0110 DEST
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2 result ← operand1 ≤ operand2;
);
R
DEST
← Register(result);
Description:
Signed compare equal or less than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 2 SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
cmple
Branch Register - Register s cmple B
BDEST
= R
SRC 1
, R
SRC 2
00 0 1 1 0110 BDEST SRC 2
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2 result ← operand1 ≤ operand2;
);
B
BDEST
← Bit(result);
Description:
Signed compare equal or less than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 1
181
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cmple
Register - Immediate s cmple R
IDEST
= R
SRC 1
, ISRC 2
00 1 1 0 0110 ISRC 2 IDEST
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 )); result ← operand1 ≤ operand2;
R
IDEST
← Register(result);
Description:
Signed compare equal or less than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
cmple
Branch Register - Immediate s cmple B
IBDEST
= R
SRC 1
, ISRC 2
00 1 1 1 0110 ISRC 2 IBDEST SRC 1
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 )); result ← operand1 ≤ operand2;
B
IBDEST
← Bit(result);
Description:
Signed compare equal or less than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
183
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cmpleu
Register - Register s cmpleu R
DEST
= R
SRC 1
, R
SRC 2
00 0 1 0 0111 DEST SRC 2
Semantics: operand1 ← ZeroExtend
32
( R
SRC operand2 ← ZeroExtend
32
( R
SRC result ← operand1 ≤ operand2;
1
);
2
);
R
DEST
← Register(result);
Description:
Unsigned compare equal or less than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
cmpleu
Branch Register - Register s cmpleu B
BDEST
= R
SRC 1
, R
SRC 2
00 0 1 1 0111 BDEST SRC 2
Semantics: operand1 ← ZeroExtend
32
( R
SRC operand2 ← ZeroExtend
32
( R
SRC result ← operand1 ≤ operand2;
1
);
2
);
B
BDEST
← Bit(result);
Description:
Unsigned compare equal or less than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 1
185
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cmpleu
Register - Immediate s cmpleu R
IDEST
= R
SRC 1
, ISRC 2
00 1 1 0 0111 ISRC 2 IDEST
Semantics: operand1 ← ZeroExtend
32
( R
SRC 1
); operand2 ← ZeroExtend
32
(Imm( ISRC 2 )); result ← operand1 ≤ operand2;
R
IDEST
← Register(result);
Description:
Unsigned compare equal or less than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
cmpleu
Branch Register - Immediate s cmpleu B
IBDEST
= R
SRC 1
, ISRC 2
00 1 1 1 0111 ISRC 2 IBDEST SRC 1
Semantics: operand1 ← ZeroExtend
32
( R
SRC 1
); operand2 ← ZeroExtend
32
(Imm( ISRC 2 )); result ← operand1 ≤ operand2;
B
IBDEST
← Bit(result);
Description:
Unsigned compare equal or less than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
187
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cmplt
Register - Register s cmplt R
DEST
= R
SRC 1
, R
SRC 2
00 0 1 0 1000 DEST
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2 result ← operand1 < operand2;
);
R
DEST
← Register(result);
Description:
Signed compare less than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 2 SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
cmplt
Branch Register - Register s cmplt B
BDEST
= R
SRC 1
, R
SRC 2
00 0 1 1 1000 BDEST SRC 2
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2 result ← operand1 < operand2;
);
B
BDEST
← Bit(result);
Description:
Signed compare less than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 1
189
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cmplt
Register - Immediate s cmplt R
IDEST
= R
SRC 1
, ISRC 2
00 1 1 0 1000 ISRC 2
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 )); result ← operand1 < operand2;
R
IDEST
← Register(result);
Description:
Signed compare less than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
IDEST SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
cmplt
Branch Register - Immediate s cmplt B
IBDEST
= R
SRC 1
, ISRC 2
00 1 1 1 1000 ISRC 2 IBDEST SRC 1
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 )); result ← operand1 < operand2;
B
IBDEST
← Bit(result);
Description:
Signed compare less than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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cmpltu
Register - Register s cmpltu R
DEST
= R
SRC 1
, R
SRC 2
00 0 1 0 1001 DEST
Semantics: operand1 ← ZeroExtend
32
( R
SRC operand2 ← ZeroExtend
32
( R
SRC result ← operand1 < operand2;
1
);
2
);
R
DEST
← Register(result);
Description:
Unsigned compare less than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 2 SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
cmpltu
Branch Register - Register s cmpltu B
BDEST
= R
SRC 1
, R
SRC 2
00 0 1 1 1001 BDEST SRC 2
Semantics: operand1 ← ZeroExtend
32
( R
SRC operand2 ← ZeroExtend
32
( R
SRC result ← operand1 < operand2;
1
);
2
);
B
BDEST
← Bit(result);
Description:
Unsigned compare less than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 1
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cmpltu
Register - Immediate s cmpltu R
IDEST
= R
SRC 1
, ISRC 2
00 1 1 0 1001 ISRC 2 IDEST
Semantics: operand1 ← ZeroExtend
32
( R
SRC 1
); operand2 ← ZeroExtend
32
(Imm( ISRC 2 )); result ← operand1 < operand2;
R
IDEST
← Register(result);
Description:
Unsigned compare less than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
cmpltu
Branch Register - Immediate s cmpltu B
IBDEST
= R
SRC 1
, ISRC 2
00 1 1 1 1001 ISRC 2 IBDEST SRC 1
Semantics: operand1 ← ZeroExtend
32
( R
SRC 1
); operand2 ← ZeroExtend
32
(Imm( ISRC 2 )); result ← operand1 < operand2;
B
IBDEST
← Bit(result);
Description:
Unsigned compare less than
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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cmpne
Register - Register s cmpne R
DEST
= R
SRC 1
, R
SRC 2
00 0 1 0 0001 DEST
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2 result ← operand1 ≠ operand2;
);
R
DEST
← Register(result);
Description:
Test for inequality
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 2 SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
cmpne
Branch Register - Register s cmpne B
BDEST
= R
SRC 1
, R
SRC 2
00 0 1 1 0001 BDEST SRC 2
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2 result ← operand1 ≠ operand2;
);
B
BDEST
← Bit(result);
Description:
Test for inequality
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 1
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cmpne
Register - Immediate s cmpne R
IDEST
= R
SRC 1
, ISRC 2
00 1 1 0 0001 ISRC 2 IDEST
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 )); result ← operand1 ≠ operand2;
R
IDEST
← Register(result);
Description:
Test for inequality
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
cmpne
Branch Register - Immediate s cmpne B
IBDEST
= R
SRC 1
, ISRC 2
00 1 1 1 0001 ISRC 2 IBDEST SRC 1
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 )); result ← operand1 ≠ operand2;
B
IBDEST
← Bit(result);
Description:
Test for inequality
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
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divs
s divs R
DEST
, B
BDEST
= R
SRC 1
, R
SRC 2
, B
SCOND
01 0100 SCOND BDEST DEST SRC 2
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2
); operand3 ← ZeroExtend
1 temp ← ZeroExtend
32
( B
SCOND
);
(operand1 × 2) ∨ (operand3 ∧ 1);
IF (operand1 < 0)
{ result ← temp + operand2; quotientBit ← 1;
}
ELSE
{ result ← temp - operand2; quotientBit ← 0;
}
R
DEST
← Register(result);
B
BDEST
← Bit(quotientBit);
Description:
Non-restoring divide stage
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual
SRC 1
Operations
ADCS 7395369G
Operations
goto
Immediate s goto BTARG
11 0 001 0 BTARG
Semantics: operand1
←
SignExtend
23
( BTARG );
PC
←
Register(ZeroExtend
32
(BUNDLE_PC) + (operand1 << 2));
Description:
Jump
Restrictions:
Must be the first syllable of a bundle.
No latency constraints.
Exceptions:
None.
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goto
Link Register s goto LR
11 0 001 1
Semantics:
PC
←
Register(ZeroExtend
32
(LR));
Description:
Jump (using Link Register)
Restrictions:
Must be the first syllable of a bundle.
Instructions writing LR must be followed by 3 bundles before this instruction can be issued.
Exceptions:
None.
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
imml
s imml imm
01 01010
Semantics: extension
←
ZeroExtend
23
(imm);
Description:
Long immediate for previous syllable
Restrictions:
Must be encoded at even word addresses.
No latency constraints.
Exceptions:
None.
IMM
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immr
s immr imm
01 01011
Semantics: extension
←
ZeroExtend
23
(imm);
Description:
Long immediate for next syllable
Restrictions:
Must be encoded at even word addresses.
No latency constraints.
Exceptions:
None.
IMM
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
ldb
s ldb R
IDEST
= ISRC 2 [ R
SRC 1
]
10 0011 0 ISRC 2 IDEST SRC 1
Semantics: base ← SignExtend
32
(Imm( ISRC 2 )); offset ← SignExtend
32 ea ← ZeroExtend
32
( R
SRC 1
);
(base + offset);
IF (IsDBreakHit(ea))
THROW DBREAK;
IF (IsCRegSpace(ea))
THROW CREG_ACCESS_VIOLATION;
ReadCheckMemory
8
(ea);
ReadMemory
8
(ea); result ← SignExtend
8
R
IDEST
(ReadMemResponse());
← Register(result);
Description:
Signed load byte
Restrictions:
Cannot write the link register (LR).
Uses the load/store unit, for which only one operation is allowed per bundle.
This instruction must be followed by 2 bundles before
R
IDEST
can be read.
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Exceptions:
DBREAK
CREG_ACCESS_VIOLATION
DBREAK
MISALIGNED_TRAP
DPU_NO_TRANSLATION
DPU_ACCESS_VIOLATION
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
ldb.d
s ldb.d R
IDEST
= ISRC 2 [ R
SRC 1
]
10 0011 1 ISRC 2 IDEST SRC 1
Semantics: base ← SignExtend
32
(Imm( ISRC 2 )); offset ← SignExtend
32 ea ← ZeroExtend
32
( R
SRC 1
);
(base + offset);
IF (IsDBreakHit(ea))
THROW DBREAK;
IF (NOT IsCRegSpace(ea))
DisReadCheckMemory
8
(ea);
IF (NOT IsCRegSpace(ea))
DisReadMemory
8
(ea);
IF (IsCRegSpace(ea)) result ← 0;
ELSE result ← SignExtend
8
(ReadMemResponse());
R
IDEST
← Register(result);
Description:
Signed load byte dismissable
Restrictions:
Cannot write the link register (LR).
Uses the load/store unit, for which only one operation is allowed per bundle.
This instruction must be followed by 2 bundles before R
IDEST
can be read.
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Exceptions:
DBREAK
DBREAK
MISALIGNED_TRAP
DPU_NO_TRANSLATION
DPU_ACCESS_VIOLATION
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
ldbu
s ldbu R
IDEST
= ISRC 2 [ R
SRC 1
]
10 0100 0 ISRC 2 IDEST SRC 1
Semantics: base ← SignExtend
32
(Imm( ISRC 2 )); offset ← SignExtend
32 ea ← ZeroExtend
32
( R
SRC 1
);
(base + offset);
IF (IsDBreakHit(ea))
THROW DBREAK;
IF (IsCRegSpace(ea))
THROW CREG_ACCESS_VIOLATION;
ReadCheckMemory
8
(ea);
ReadMemory
8
(ea); result ← ZeroExtend
8
R
IDEST
(ReadMemResponse());
← Register(result);
Description:
Unsigned load byte
Restrictions:
Cannot write the link register (LR).
Uses the load/store unit, for which only one operation is allowed per bundle.
This instruction must be followed by 2 bundles before
R
IDEST
can be read.
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Exceptions:
DBREAK
CREG_ACCESS_VIOLATION
DBREAK
MISALIGNED_TRAP
DPU_NO_TRANSLATION
DPU_ACCESS_VIOLATION
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
ldbu.d
s ldbu.d R
IDEST
= ISRC 2 [ R
SRC 1
]
10 0100 1 ISRC 2 IDEST SRC 1
Semantics: base ← SignExtend
32
(Imm( ISRC 2 )); offset ← SignExtend
32 ea ← ZeroExtend
32
( R
SRC 1
);
(base + offset);
IF (IsDBreakHit(ea))
THROW DBREAK;
IF (NOT IsCRegSpace(ea))
DisReadCheckMemory
8
(ea);
IF (NOT IsCRegSpace(ea))
DisReadMemory
8
(ea);
IF (IsCRegSpace(ea)) result ← 0;
ELSE result ← ZeroExtend
8
(ReadMemResponse());
R
IDEST
← Register(result);
Description:
Unsigned load byte dismissable
Restrictions:
Cannot write the link register (LR).
Uses the load/store unit, for which only one operation is allowed per bundle.
This instruction must be followed by 2 bundles before R
IDEST
can be read.
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Exceptions:
DBREAK
DBREAK
MISALIGNED_TRAP
DPU_NO_TRANSLATION
DPU_ACCESS_VIOLATION
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
ldh
s ldh R
IDEST
= ISRC 2 [ R
SRC 1
]
10 0001 0 ISRC 2 IDEST SRC 1
Semantics: base ← SignExtend
32
(Imm( ISRC 2 )); offset ← SignExtend
32 ea ← ZeroExtend
32
( R
SRC 1
);
(base + offset);
IF (IsDBreakHit(ea))
THROW DBREAK;
IF (IsCRegSpace(ea))
THROW CREG_ACCESS_VIOLATION;
ReadCheckMemory
16
(ea);
ReadMemory
16
(ea); result ← SignExtend
16
R
IDEST
(ReadMemResponse());
← Register(result);
Description:
Signed load half-word
Restrictions:
Cannot write the link register (LR).
Uses the load/store unit, for which only one operation is allowed per bundle.
This instruction must be followed by 2 bundles before
R
IDEST
can be read.
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Exceptions:
DBREAK
CREG_ACCESS_VIOLATION
DBREAK
MISALIGNED_TRAP
DPU_NO_TRANSLATION
DPU_ACCESS_VIOLATION
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
ldh.d
s ldh.d R
IDEST
= ISRC 2 [ R
SRC 1
]
10 0001 1 ISRC 2 IDEST SRC 1
Semantics: base ← SignExtend
32
(Imm( ISRC 2 )); offset ← SignExtend
32 ea ← ZeroExtend
32
( R
SRC 1
);
(base + offset);
IF (IsDBreakHit(ea))
THROW DBREAK;
IF (NOT IsCRegSpace(ea))
DisReadCheckMemory
16
(ea);
IF (NOT IsCRegSpace(ea))
DisReadMemory
16
(ea);
IF (IsCRegSpace(ea)) result ← 0;
ELSE result ← SignExtend
16
(ReadMemResponse());
R
IDEST
← Register(result);
Description:
Signed load half-word dismissable
Restrictions:
Cannot write the link register (LR).
Uses the load/store unit, for which only one operation is allowed per bundle.
This instruction must be followed by 2 bundles before R
IDEST
can be read.
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Exceptions:
DBREAK
DBREAK
MISALIGNED_TRAP
DPU_NO_TRANSLATION
DPU_ACCESS_VIOLATION
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
ldhu
s ldhu R
IDEST
= ISRC 2 [ R
SRC 1
]
10 0010 0 ISRC 2 IDEST SRC 1
Semantics: base ← SignExtend
32
(Imm( ISRC 2 )); offset ← SignExtend
32 ea ← ZeroExtend
32
( R
SRC 1
);
(base + offset);
IF (IsDBreakHit(ea))
THROW DBREAK;
IF (IsCRegSpace(ea))
THROW CREG_ACCESS_VIOLATION;
ReadCheckMemory
16
(ea);
ReadMemory
16
(ea); result ← ZeroExtend
16
R
IDEST
(ReadMemResponse());
← Register(result);
Description:
Unsigned load half-word
Restrictions:
Cannot write the link register (LR).
Uses the load/store unit, for which only one operation is allowed per bundle.
This instruction must be followed by 2 bundles before
R
IDEST
can be read.
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Exceptions:
DBREAK
CREG_ACCESS_VIOLATION
DBREAK
MISALIGNED_TRAP
DPU_NO_TRANSLATION
DPU_ACCESS_VIOLATION
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
ldhu.d
s ldhu.d R
IDEST
= ISRC 2 [ R
SRC 1
]
10 0010 1 ISRC 2 IDEST SRC 1
Semantics: base ← SignExtend
32
(Imm( ISRC 2 )); offset ← SignExtend
32 ea ← ZeroExtend
32
( R
SRC 1
);
(base + offset);
IF (IsDBreakHit(ea))
THROW DBREAK;
IF (NOT IsCRegSpace(ea))
DisReadCheckMemory
16
(ea);
IF (NOT IsCRegSpace(ea))
DisReadMemory
16
(ea);
IF (IsCRegSpace(ea)) result ← 0;
ELSE result ← ZeroExtend
16
(ReadMemResponse());
R
IDEST
← Register(result);
Description:
Unsigned load half-word dismissable
Restrictions:
Cannot write the link register (LR).
Uses the load/store unit, for which only one operation is allowed per bundle.
This instruction must be followed by 2 bundles before R
IDEST
can be read.
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Exceptions:
DBREAK
DBREAK
MISALIGNED_TRAP
DPU_NO_TRANSLATION
DPU_ACCESS_VIOLATION
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
ldw
s ldw R
IDEST
= ISRC 2 [ R
SRC 1
]
10 0000 0 ISRC 2 IDEST SRC 1
Semantics: base ← SignExtend
32
(Imm( ISRC 2 )); offset ← SignExtend
32 ea ← ZeroExtend
32
( R
SRC 1
);
(base + offset);
IF (IsDBreakHit(ea))
THROW DBREAK;
IF (IsCRegSpace(ea))
ReadCheckCReg(ea);
ReadCheckMemory
32
(ea);
IF (IsCRegSpace(ea))
ReadCReg(ea);
ELSE
ReadMemory
32
(ea); result ← SignExtend
32
(ReadMemResponse());
R
IDEST
← Register(result);
Description:
Load word
Restrictions:
Uses the load/store unit, for which only one operation is allowed per bundle.
This instruction must be followed by 2 bundles before R
IDEST
can be read.
221
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Exceptions:
DBREAK
MISALIGNED_TRAP
DPU_NO_TRANSLATION
DPU_ACCESS_VIOLATION
CREG_NO_MAPPING
CREG_ACCESS_VIOLATION
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
ldw.d
s ldw.d R
IDEST
= ISRC 2 [ R
SRC 1
]
10 0000 1 ISRC 2 IDEST SRC 1
Semantics: base ← SignExtend
32
(Imm( ISRC 2 )); offset ← SignExtend
32 ea ← ZeroExtend
32
( R
SRC 1
);
(base + offset);
IF (IsDBreakHit(ea))
THROW DBREAK;
IF (NOT IsCRegSpace(ea))
DisReadCheckMemory
32
(ea);
IF (NOT IsCRegSpace(ea))
DisReadMemory
32
(ea);
IF (IsCRegSpace(ea)) result ← 0;
ELSE result ← SignExtend
32
(ReadMemResponse());
R
IDEST
← Register(result);
Description:
Load word dismissable
Restrictions:
Uses the load/store unit, for which only one operation is allowed per bundle.
This instruction must be followed by 2 bundles before R
IDEST
can be read.
223
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Exceptions:
DBREAK
MISALIGNED_TRAP
DPU_NO_TRANSLATION
DPU_ACCESS_VIOLATION
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
max
Register s max R
DEST
= R
SRC 1
, R
SRC 2
00 0 0 10000 DEST
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2
);
IF (operand1 > operand2) result ← operand1;
ELSE result ← operand2;
R
DEST
← Register(result);
Description:
Signed maximum
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 2 SRC 1
225
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max
Immediate s max R
IDEST
= R
SRC 1
, ISRC 2
00 1 0 10000 ISRC 2
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 ));
IF (operand1 > operand2) result ← operand1;
ELSE result ← operand2;
R
IDEST
← Register(result);
Description:
Signed maximum
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
IDEST SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
maxu
Register s maxu R
DEST
= R
SRC 1
, R
SRC 2
00 0 0 10001 DEST
Semantics: operand1 ← ZeroExtend
32
( R
SRC operand2 ← ZeroExtend
32
( R
SRC
1
);
2
);
IF (operand1 > operand2) result ← operand1;
ELSE result ← operand2;
R
DEST
← Register(result);
Description:
Unsigned maximum
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 2 SRC 1
227
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maxu
Immediate s maxu R
IDEST
= R
SRC 1
, ISRC 2
00 1 0 10001 ISRC 2
Semantics: operand1 ← ZeroExtend
32
( R
SRC 1
); operand2 ← ZeroExtend
32
(Imm( ISRC 2 ));
IF (operand1 > operand2) result ← operand1;
ELSE result ← operand2;
R
IDEST
← Register(result);
Description:
Unsigned maximum
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
IDEST SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
min
Register s min R
DEST
= R
SRC 1
, R
SRC 2
00 0 0 10010 DEST
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2
);
IF (operand1 < operand2) result ← operand1;
ELSE result ← operand2;
R
DEST
← Register(result);
Description:
Signed minimum
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 2 SRC 1
229
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min
Immediate s min R
IDEST
= R
SRC 1
, ISRC 2
00 1 0 10010 ISRC 2
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 ));
IF (operand1 < operand2) result ← operand1;
ELSE result ← operand2;
R
IDEST
← Register(result);
Description:
Signed minimum
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
IDEST SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
minu
Register s minu R
DEST
= R
SRC 1
, R
SRC 2
00 0 0 10011 DEST
Semantics: operand1 ← ZeroExtend
32
( R
SRC operand2 ← ZeroExtend
32
( R
SRC
1
);
2
);
IF (operand1 < operand2) result ← operand1;
ELSE result ← operand2;
R
DEST
← Register(result);
Description:
Unsigned minimum
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 2 SRC 1
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minu
Immediate s minu R
IDEST
= R
SRC 1
, ISRC 2
00 1 0 10011 ISRC 2
Semantics: operand1 ← ZeroExtend
32
( R
SRC 1
); operand2 ← ZeroExtend
32
(Imm( ISRC 2 ));
IF (operand1 < operand2) result ← operand1;
ELSE result ← operand2;
R
IDEST
← Register(result);
Description:
Unsigned minimum
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
IDEST SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
mulh
Register s mulh R
DEST
= R
SRC 1
, R
SRC 2
00 0 0 10111 DEST SRC 2 SRC 1
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2
); result ← operand1 × (operand2 >> 16);
R
DEST
← Register(result);
Description:
Word by upper-half-word signed multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
This instruction must be followed by 2 bundles before R
DEST
can be read.
Exceptions:
None.
233
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234 Operations
mulh
Immediate s mulh R
IDEST
= R
SRC 1
, ISRC 2
00 1 0 10111 ISRC 2 IDEST SRC 1
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 )); result ← operand1 × (operand2 >> 16);
R
IDEST
← Register(result);
Description:
Word by upper-half-word signed multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
This instruction must be followed by 2 bundles before R
IDEST
can be read.
Exceptions:
None.
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
mulhh
Register s mulhh R
DEST
= R
SRC 1
, R
SRC 2
00 0 0 11101 DEST SRC 2 SRC 1
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2
); result ← (operand1 >> 16) × (operand2 >> 16);
R
DEST
← Register(result);
Description:
Upper-half-word by upper-half-word signed multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
This instruction must be followed by 2 bundles before R
DEST
can be read.
Exceptions:
None.
235
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ST220 Core and Instruction Set Architecture Manual
236 Operations
mulhh
Immediate s mulhh R
IDEST
= R
SRC 1
, ISRC 2
00 1 0 11101 ISRC 2 IDEST SRC 1
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 )); result ← (operand1 >> 16) × (operand2 >> 16);
R
IDEST
← Register(result);
Description:
Upper-half-word by upper-half-word signed multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
This instruction must be followed by 2 bundles before R
IDEST
can be read.
Exceptions:
None.
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
mulhhs
Register s mulhhs R
DEST
= R
SRC 1
, R
SRC 2
00 0 0 10100 DEST SRC 2 SRC 1
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2
); result ← (operand1 × (operand2 >> 16)) >> 16;
R
DEST
← Register(result);
Description:
Word by upper-half-word signed multiply, returns top 32 bits of 48 bit result
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
This instruction must be followed by 2 bundles before R
DEST
can be read.
Exceptions:
None.
237
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238 Operations
mulhhs
Immediate s mulhhs R
IDEST
= R
SRC 1
, ISRC 2
00 1 0 10100 ISRC 2 IDEST SRC 1
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 )); result ← (operand1 × (operand2 >> 16)) >> 16;
R
IDEST
← Register(result);
Description:
Word by upper-half-word signed multiply, returns top 32 bits of 48 bit result
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
This instruction must be followed by 2 bundles before R
IDEST
can be read.
Exceptions:
None.
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
mulhhu
Register s mulhhu R
DEST
= R
SRC 1
, R
SRC 2
00 0 0 11110 DEST SRC 2 SRC 1
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2
); result ← ZeroExtend
16
(operand1 >> 16) × ZeroExtend
16
(operand2 >> 16);
R
DEST
← Register(result);
Description:
Upper-half-word by upper-half-word unsigned multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
This instruction must be followed by 2 bundles before R
DEST
can be read.
Exceptions:
None.
239
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240 Operations
mulhhu
Immediate s mulhhu R
IDEST
= R
SRC 1
, ISRC 2
00 1 0 11110 ISRC 2 IDEST SRC 1
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 )); result ← ZeroExtend
16
R
IDEST
(operand1 >> 16)
← Register(result);
× ZeroExtend
16
(operand2 >> 16);
Description:
Upper-half-word by upper-half-word unsigned multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
This instruction must be followed by 2 bundles before R
IDEST
can be read.
Exceptions:
None.
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
mulhs
Register s mulhs R
DEST
= R
SRC 1
, R
SRC 2
00 0 0 11111 DEST SRC 2 SRC 1
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2
); result ← (operand1 × ZeroExtend
16
(operand2 >> 16)) << 16;
R
DEST
← Register(result);
Description:
Word by upper-half-word unsigned multiply, left shifted 16
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
This instruction must be followed by 2 bundles before R
DEST
can be read.
Exceptions:
None.
241
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ST220 Core and Instruction Set Architecture Manual
242 Operations
mulhs
Immediate s mulhs R
IDEST
= R
SRC 1
, ISRC 2
00 1 0 11111 ISRC 2 IDEST SRC 1
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 )); result ← (operand1 × ZeroExtend
16
R
IDEST
← Register(result);
(operand2 >> 16)) << 16;
Description:
Word by upper-half-word unsigned multiply, left shifted 16
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
This instruction must be followed by 2 bundles before R
IDEST
can be read.
Exceptions:
None.
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
mulhu
Register s mulhu R
DEST
= R
SRC 1
, R
SRC 2
00 0 0 11000 DEST SRC 2 SRC 1
Semantics: operand1 ← ZeroExtend
32
( R
SRC 1
); operand2 ← SignExtend
32
( R
SRC 2
); result ← operand1 × ZeroExtend
16
(operand2 >> 16);
R
DEST
← Register(result);
Description:
Word by upper-half-word unsigned multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
This instruction must be followed by 2 bundles before R
DEST
can be read.
Exceptions:
None.
243
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ST220 Core and Instruction Set Architecture Manual
244 Operations
mulhu
Immediate s mulhu R
IDEST
= R
SRC 1
, ISRC 2
00 1 0 11000 ISRC 2 IDEST SRC 1
Semantics: operand1 ← ZeroExtend
32
( R
SRC 1
); operand2 ← SignExtend
32
(Imm( ISRC 2 )); result ← operand1 × ZeroExtend
16
R
IDEST
← Register(result);
(operand2 >> 16);
Description:
Word by upper-half-word unsigned multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
This instruction must be followed by 2 bundles before R
IDEST
can be read.
Exceptions:
None.
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
mull
Register s mull R
DEST
= R
SRC 1
, R
SRC 2
00 0 0 10101 DEST SRC 2 SRC 1
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
16
( R
SRC 1
);
( R
SRC 2
); result ← operand1 × operand2;
R
DEST
← Register(result);
Description:
Word by half-word signed multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
This instruction must be followed by 2 bundles before R
DEST
can be read.
Exceptions:
None.
245
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246 Operations
mull
Immediate s mull R
IDEST
= R
SRC 1
, ISRC 2
00 1 0 10101 ISRC 2 IDEST SRC 1
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
16
( R
SRC 1
);
(Imm( ISRC 2 )); result ← operand1 × operand2;
R
IDEST
← Register(result);
Description:
Word by half-word signed multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
This instruction must be followed by 2 bundles before R
IDEST
can be read.
Exceptions:
None.
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
mullh
Register s mullh R
DEST
= R
SRC 1
, R
SRC 2
00 0 0 11011 DEST SRC 2 SRC 1
Semantics: operand1 ← SignExtend
16 operand2 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2
); result ← operand1 × (operand2 >> 16);
R
DEST
← Register(result);
Description:
Half-word by upper-half-word signed multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
This instruction must be followed by 2 bundles before R
DEST
can be read.
Exceptions:
None.
247
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248 Operations
mullh
Immediate s mullh R
IDEST
= R
SRC 1
, ISRC 2
00 1 0 11011 ISRC 2 IDEST SRC 1
Semantics: operand1 ← SignExtend
16 operand2 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 )); result ← operand1 × (operand2 >> 16);
R
IDEST
← Register(result);
Description:
Half-word by upper-half-word signed multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
This instruction must be followed by 2 bundles before R
IDEST
can be read.
Exceptions:
None.
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
mullhu
Register s mullhu R
DEST
= R
SRC 1
, R
SRC 2
00 0 0 11100 DEST SRC 2 SRC 1
Semantics: operand1 ← ZeroExtend
16
( R
SRC 1
); operand2 ← SignExtend
32
( R
SRC 2
); result ← operand1 × ZeroExtend
16
(operand2 >> 16);
R
DEST
← Register(result);
Description:
Half-word by upper-half-word unsigned multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
This instruction must be followed by 2 bundles before R
DEST
can be read.
Exceptions:
None.
249
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ST220 Core and Instruction Set Architecture Manual
250 Operations
mullhu
Immediate s mullhu R
IDEST
= R
SRC 1
, ISRC 2
00 1 0 11100 ISRC 2 IDEST SRC 1
Semantics: operand1 ← ZeroExtend
16
( R
SRC 1
); operand2 ← SignExtend
32
(Imm( ISRC 2 )); result ← operand1 × ZeroExtend
16
R
IDEST
← Register(result);
(operand2 >> 16);
Description:
Half-word by upper-half-word unsigned multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
This instruction must be followed by 2 bundles before R
IDEST
can be read.
Exceptions:
None.
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
mullhus
Register s mullhus R
DEST
= R
SRC 1
, R
SRC 2
00 0 0 01111 DEST
251
SRC 2 SRC 1
Semantics: operand1 ← SignExtend
32 operand2 ← ZeroExtend
16
( R
SRC 1
);
( R
SRC 2
); result ← (operand1 × operand2) >> 32;
R
DEST
← Register(result);
Description:
Word by lower-half-word signed multiply, returns top 16 bits of 48 bit result, sign extended
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
This instruction must be followed by 2 bundles before R
DEST
can be read.
Exceptions:
None.
ADCS 7395369G
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual
252 Operations
mullhus
Immediate s mullhus R
IDEST
= R
SRC 1
, ISRC 2
00 1 0 01111 ISRC 2 IDEST SRC 1
Semantics: operand1 ← SignExtend
32 operand2 ← ZeroExtend
16
( R
SRC 1
);
(Imm( ISRC 2 )); result ← (operand1 × operand2) >> 32;
R
IDEST
← Register(result);
Description:
Word by lower-half-word signed multiply, returns top 16 bits of 48 bit result, sign extended
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
This instruction must be followed by 2 bundles before R
IDEST
can be read.
Exceptions:
None.
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
mulll
Register s mulll R
DEST
= R
SRC 1
, R
SRC 2
00 0 0 11001 DEST SRC 2 SRC 1
Semantics: operand1 ← SignExtend
16 operand2 ← SignExtend
16
( R
SRC 1
);
( R
SRC 2
); result ← operand1 × operand2;
R
DEST
← Register(result);
Description:
Half-word by half-word signed multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
This instruction must be followed by 2 bundles before R
DEST
can be read.
Exceptions:
None.
253
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254 Operations
mulll
Immediate s mulll R
IDEST
= R
SRC 1
, ISRC 2
00 1 0 11001 ISRC 2 IDEST SRC 1
Semantics: operand1 ← SignExtend
16 operand2 ← SignExtend
16
( R
SRC 1
);
(Imm( ISRC 2 )); result ← operand1 × operand2;
R
IDEST
← Register(result);
Description:
Half-word by half-word signed multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
This instruction must be followed by 2 bundles before R
IDEST
can be read.
Exceptions:
None.
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
mulllu
Register s mulllu R
DEST
= R
SRC 1
, R
SRC 2
00 0 0 11010 DEST SRC 2 SRC 1
Semantics: operand1 ← ZeroExtend
16
( R
SRC operand2 ← ZeroExtend
16
( R
SRC
1
);
2
); result ← operand1 × operand2;
R
DEST
← Register(result);
Description:
Half-word by half-word unsigned multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
This instruction must be followed by 2 bundles before R
DEST
can be read.
Exceptions:
None.
255
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ST220 Core and Instruction Set Architecture Manual
256 Operations
mulllu
Immediate s mulllu R
IDEST
= R
SRC 1
, ISRC 2
00 1 0 11010 ISRC 2 IDEST SRC 1
Semantics: operand1 ← ZeroExtend
16
( R
SRC 1
); operand2 ← ZeroExtend
16
(Imm( ISRC 2 )); result ← operand1 × operand2;
R
IDEST
← Register(result);
Description:
Half-word by half-word unsigned multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
This instruction must be followed by 2 bundles before R
IDEST
can be read.
Exceptions:
None.
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
mullu
Register s mullu R
DEST
= R
SRC 1
, R
SRC 2
00 0 0 10110 DEST SRC 2 SRC 1
Semantics: operand1 ← ZeroExtend
32
( R
SRC operand2 ← ZeroExtend
16
( R
SRC
1
);
2
); result ← operand1 × operand2;
R
DEST
← Register(result);
Description:
Word by half-word unsigned multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
This instruction must be followed by 2 bundles before R
DEST
can be read.
Exceptions:
None.
257
ADCS 7395369G
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ST220 Core and Instruction Set Architecture Manual
258 Operations
mullu
Immediate s mullu R
IDEST
= R
SRC 1
, ISRC 2
00 1 0 10110 ISRC 2 IDEST SRC 1
Semantics: operand1 ← ZeroExtend
32
( R
SRC 1
); operand2 ← ZeroExtend
16
(Imm( ISRC 2 )); result ← operand1 × operand2;
R
IDEST
← Register(result);
Description:
Word by half-word unsigned multiply
Restrictions:
Cannot write the link register (LR).
Must be encoded at odd word addresses.
This instruction must be followed by 2 bundles before R
IDEST
can be read.
Exceptions:
None.
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
nandl
Register - Register s nandl R
DEST
= R
SRC 1
, R
SRC 2
00 0 1 0 1011 DEST
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2
); result ← NOT ((operand1 ≠ 0) AND (operand2 ≠ 0));
R
DEST
← Register(result);
Description:
Logical nand
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 2 SRC 1
259
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260
nandl
Branch Register - Register s nandl B
BDEST
= R
SRC 1
, R
SRC 2
00 0 1 1 1011 BDEST SRC 2
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2
); result ← NOT ((operand1 ≠ 0) AND (operand2 ≠ 0));
B
BDEST
← Bit(result);
Description:
Logical nand
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
nandl
Register - Immediate s nandl R
IDEST
= R
SRC 1
, ISRC 2
00 1 1 0 1011 ISRC 2
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 )); result ← NOT ((operand1 ≠ 0) AND (operand2 ≠ 0));
R
IDEST
← Register(result);
Description:
Logical nand
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
IDEST SRC 1
261
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262
nandl
Branch Register - Immediate s nandl B
IBDEST
= R
SRC 1
, ISRC 2
00 1 1 1 1011 ISRC 2 IBDEST SRC 1
Operations
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 )); result ← NOT ((operand1 ≠ 0) AND (operand2 ≠ 0));
B
IBDEST
← Bit(result);
Description:
Logical nand
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
norl
Register - Register s norl R
DEST
= R
SRC 1
, R
SRC 2
00 0 1 0 1101 DEST
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2
); result ← NOT ((operand1 ≠ 0) OR (operand2 ≠ 0));
R
DEST
← Register(result);
Description:
Logical nor
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 2 SRC 1
263
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264
norl
Branch Register - Register s norl B
BDEST
= R
SRC 1
, R
SRC 2
00 0 1 1 1101 BDEST SRC 2
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2
); result ← NOT ((operand1 ≠ 0) OR (operand2 ≠ 0));
B
BDEST
← Bit(result);
Description:
Logical nor
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
norl
Register - Immediate s norl R
IDEST
= R
SRC 1
, ISRC 2
00 1 1 0 1101 ISRC 2
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 )); result ← NOT ((operand1 ≠ 0) OR (operand2 ≠ 0));
R
IDEST
← Register(result);
Description:
Logical nor
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
IDEST SRC 1
265
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266
norl
Branch Register - Immediate s norl B
IBDEST
= R
SRC 1
, ISRC 2
00 1 1 1 1101 ISRC 2 IBDEST SRC 1
Operations
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 )); result ← NOT ((operand1 ≠ 0) OR (operand2 ≠ 0));
B
IBDEST
← Bit(result);
Description:
Logical nor
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
or
Register s or R
DEST
= R
SRC 1
, R
SRC 2
00 0 0 01011
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2 result ← operand1 ∨ operand2;
);
R
DEST
← Register(result);
Description:
Bitwise or
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
DEST SRC 2 SRC 1
267
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or
Immediate s or R
IDEST
= R
SRC 1
, ISRC 2
00 1 0 01011 ISRC 2
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 )); result ← operand1 ∨ operand2;
R
IDEST
← Register(result);
Description:
Bitwise or
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
IDEST SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
orc
Register s orc R
DEST
= R
SRC 1
, R
SRC 2
00 0 0 01100 DEST
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2
); result ← (~ operand1) ∨ operand2;
R
DEST
← Register(result);
Description:
Complement and bitwise or
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 2 SRC 1
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orc
Immediate s orc R
IDEST
= R
SRC 1
, ISRC 2
00 1 0 01100 ISRC 2
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 )); result ← (~ operand1) ∨ operand2;
R
IDEST
← Register(result);
Description:
Complement and bitwise or
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
IDEST SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
orl
Register - Register s orl R
DEST
= R
SRC 1
, R
SRC 2
00 0 1 0 1100 DEST
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2
); result ← (operand1 ≠ 0) OR (operand2 ≠ 0);
R
DEST
← Register(result);
Description:
Logical or
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 2 SRC 1
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orl
Branch Register - Register s orl B
BDEST
= R
SRC 1
, R
SRC 2
00 0 1 1 1100 BDEST SRC 2
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2
); result ← (operand1 ≠ 0) OR (operand2 ≠ 0);
B
BDEST
← Bit(result);
Description:
Logical or
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
orl
Register - Immediate s orl R
IDEST
= R
SRC 1
, ISRC 2
00 1 1 0 1100 ISRC 2
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 )); result ← (operand1 ≠ 0) OR (operand2 ≠ 0);
R
IDEST
← Register(result);
Description:
Logical or
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
IDEST SRC 1
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orl
Branch Register - Immediate s orl B
IBDEST
= R
SRC 1
, ISRC 2
00 1 1 1 1100 ISRC 2 IBDEST SRC 1
Operations
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 )); result ← (operand1 ≠ 0) OR (operand2 ≠ 0);
B
IBDEST
← Bit(result);
Description:
Logical or
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
pft
s pft ISRC 2 [ R
SRC 1
]
10 01101 ISRC 2 SRC 1
Semantics: base ← SignExtend
32
(Imm( ISRC 2 )); offset ← SignExtend
32 ea ← ZeroExtend
32
( R
SRC 1
);
(base + offset);
PrefetchMemory(ea);
Description:
Prefetch
Restrictions:
Uses the load/store unit, for which only one operation is allowed per bundle.
No latency constraints.
Exceptions:
None.
275
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prgadd
s prgadd ISRC 2 [ R
SRC 1
]
10 01110 ISRC 2 SRC 1
Semantics: base ← SignExtend
32
(Imm( ISRC 2 )); offset ← SignExtend
32 ea ← ZeroExtend
32
( R
SRC 1
);
(base + offset);
PurgeAddress(ea);
Description:
Purge the address given from the data cache
Restrictions:
Uses the load/store unit, for which only one operation is allowed per bundle.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
prgins
1 prgins
01 1111100
Semantics:
PurgeIns();
Description:
Purge the instruction cache
Restrictions:
Must be the only one operation in the bundle.
Must be followed by 3 bundles delay before issuing a syncins operation.
No latency constraints.
Exceptions:
None.
277
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278 Operations
prgset
s prgset ISRC 2 [ R
SRC 1
]
10 01111 ISRC 2 SRC 1
Semantics: base ← SignExtend
32
(Imm( ISRC 2 )); offset ← SignExtend
32 ea ← ZeroExtend
32
( R
SRC 1
);
(base + offset);
PurgeSet(ea);
Description:
Purge a set of four cache lines from the data cache
Restrictions:
Uses the load/store unit, for which only one operation is allowed per bundle.
No latency constraints.
Exceptions:
None.
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
rfi
s rfi
11 0 010 0
279
Semantics:
IF (PSW[USER_MODE])
THROW ILL_INST;
PC
←
Register(ZeroExtend
32
(SAVED_PC));
PSW
←
SAVED_PSW;
SAVED_PC ← SAVED_SAVED_PC;
SAVED_PSW
←
SAVED_SAVED_PSW;
Description:
Return from interrupt
Restrictions:
Must be the first syllable of a bundle.
Instructions writing SAVED_PC must be followed by 4 bundles before this instruction can be issued.
Instructions writing SAVED_PSW must be followed by 4 bundles before this instruction can be issued.
Instructions writing SAVED_SAVED_PC must be followed by 4 bundles before this instruction can be issued.
Instructions writing SAVED_SAVED_PSW must be followed by 4 bundles before this instruction can be issued.
Instructions writing PSW must be followed by 4 bundles before this instruction can be issued.
Exceptions:
ILL_INST
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sbrk
1 sbrk
01 1111101
Semantics:
THROW SBREAK;
Description:
Software breakpoint
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
SBREAK
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
sh1add
Register s sh1add R
DEST
= R
SRC 1
, R
SRC 2
00 0 0 00101 DEST
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2
); result ← (operand1 << 1) + operand2;
R
DEST
← Register(result);
Description:
Shift left one and accumulate
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 2 SRC 1
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sh1add
Immediate s sh1add R
IDEST
= R
SRC 1
, ISRC 2
00 1 0 00101 ISRC 2
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 )); result ← (operand1 << 1) + operand2;
R
IDEST
← Register(result);
Description:
Shift left one and accumulate
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
IDEST SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
sh2add
Register s sh2add R
DEST
= R
SRC 1
, R
SRC 2
00 0 0 00110 DEST
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2
); result ← (operand1 << 2) + operand2;
R
DEST
← Register(result);
Description:
Shift left two and accumulate
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 2 SRC 1
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sh2add
Immediate s sh2add R
IDEST
= R
SRC 1
, ISRC 2
00 1 0 00110 ISRC 2
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 )); result ← (operand1 << 2) + operand2;
R
IDEST
← Register(result);
Description:
Shift left two and accumulate
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
IDEST SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
sh3add
Register s sh3add R
DEST
= R
SRC 1
, R
SRC 2
00 0 0 00111 DEST
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2
); result ← (operand1 << 3) + operand2;
R
DEST
← Register(result);
Description:
Shift left three and accumulate
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 2 SRC 1
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sh3add
Immediate s sh3add R
IDEST
= R
SRC 1
, ISRC 2
00 1 0 00111 ISRC 2
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 )); result ← (operand1 << 3) + operand2;
R
IDEST
← Register(result);
Description:
Shift left three and accumulate
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
IDEST SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
sh4add
Register s sh4add R
DEST
= R
SRC 1
, R
SRC 2
00 0 0 01000 DEST
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2
); result ← (operand1 << 4) + operand2;
R
DEST
← Register(result);
Description:
Shift left four and accumulate
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 2 SRC 1
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sh4add
Immediate s sh4add R
IDEST
= R
SRC 1
, ISRC 2
00 1 0 01000 ISRC 2
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 )); result ← (operand1 << 4) + operand2;
R
IDEST
← Register(result);
Description:
Shift left four and accumulate
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
IDEST SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
shl
Register s shl R
DEST
= R
SRC 1
, R
SRC 2
00 0 0 00010 DEST
Semantics: operand1 ← SignExtend
32 distance ← ZeroExtend
8
( R
SRC 1
);
( R
SRC 2
);
IF (distance > 31) result ← 0;
ELSE result ← operand1 << distance;
R
DEST
← Register(result);
Description:
Shift left
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 2 SRC 1
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shl
Immediate s shl R
IDEST
= R
SRC 1
, ISRC 2
00 1 0 00010 ISRC 2
Semantics: operand1 ← SignExtend
32 distance ← ZeroExtend
8
( R
SRC 1
);
(Imm( ISRC 2 ));
IF (distance > 31) result ← 0;
ELSE result ← operand1 << distance;
R
IDEST
← Register(result);
Description:
Shift left
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
IDEST SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
shr
Register s shr R
DEST
= R
SRC 1
, R
SRC 2
00 0 0 00011 DEST
Semantics: operand1 ← SignExtend
32 distance ← ZeroExtend
8
( R
SRC 1
);
( R
SRC 2
); result ← operand1 >> distance;
R
DEST
← Register(result);
Description:
Arithmetic shift right
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 2 SRC 1
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shr
Immediate s shr R
IDEST
= R
SRC 1
, ISRC 2
00 1 0 00011 ISRC 2
Semantics: operand1 ← SignExtend
32 distance ← ZeroExtend
8
( R
SRC 1
);
(Imm( ISRC 2 )); result ← operand1 >> distance;
R
IDEST
← Register(result);
Description:
Arithmetic shift right
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
IDEST SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
shru
Register s shru R
DEST
= R
SRC 1
, R
SRC 2
00 0 0 00100 DEST
Semantics: operand1 ← ZeroExtend
32
( R
SRC distance ← ZeroExtend
8
( R
SRC 2
); result ← operand1 >> distance;
1
);
R
DEST
← Register(result);
Description:
Logical shift right
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 2 SRC 1
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shru
Immediate s shru R
IDEST
= R
SRC 1
, ISRC 2
00 1 0 00100 ISRC 2
Semantics: operand1 ← ZeroExtend
32
( R
SRC 1
); distance ← ZeroExtend
8
(Imm( ISRC 2 )); result ← operand1 >> distance;
R
IDEST
← Register(result);
Description:
Logical shift right
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
IDEST SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
slct
Register s slct R
DEST
= B
SCOND
, R
SRC 1
, R
SRC 2
01 0 000 SCOND DEST
Semantics: operand1 ← ZeroExtend
1
( B
SCOND
); operand2 ← SignExtend
32 operand3 ← SignExtend
32
IF (operand1 ≠ 0) result ← operand2;
( R
SRC 1
);
( R
SRC 2
);
ELSE result ← operand3;
R
DEST
← Register(result);
Description:
Conditional select
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 2 SRC 1
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slct
Immediate s slct R
IDEST
= B
SCOND
, R
SRC 1
, ISRC 2
01 1 000 SCOND ISRC 2
Semantics: operand1 ← ZeroExtend
1
( B
SCOND
); operand2 ← SignExtend
32 operand3 ← SignExtend
32
(Imm( ISRC 2 ));
IF (operand1 ≠ 0) result ← operand2;
( R
SRC 1
);
ELSE result ← operand3;
R
IDEST
← Register(result);
Description:
Conditional select
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
IDEST SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
slctf
Register s slctf R
DEST
= B
SCOND
, R
SRC 1
, R
SRC 2
01 0 001 SCOND DEST
Semantics: operand1 ← ZeroExtend
1
( B
SCOND
); operand2 ← SignExtend
32 operand3 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2
);
IF (operand1 = 0) result ← operand2;
ELSE result ← operand3;
R
DEST
← Register(result);
Description:
Conditional select
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 2 SRC 1
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slctf
Immediate s slctf R
IDEST
= B
SCOND
, R
SRC 1
, ISRC 2
01 1 001 SCOND ISRC 2
Semantics: operand1 ← ZeroExtend
1
( B
SCOND
); operand2 ← SignExtend
32 operand3 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 ));
IF (operand1 = 0) result ← operand2;
ELSE result ← operand3;
R
IDEST
← Register(result);
Description:
Conditional select
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
IDEST SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
stb
s stb ISRC 2 [ R
SRC 1
] = R
SRC 2
10 01100 ISRC 2 SRC 2 SRC 1
Semantics: base ← SignExtend
32
(Imm( ISRC 2 )); offset ← SignExtend
32
( R
SRC 1 operand3 ← SignExtend
32
( R
);
SRC 2
); ea ← ZeroExtend
32
(base + offset);
IF (IsDBreakHit(ea))
THROW DBREAK;
IF (IsCRegSpace(ea))
THROW CREG_ACCESS_VIOLATION;
WriteCheckMemory
8
(ea);
WriteMemory
8
(ea, operand3);
Description:
Store byte
Restrictions:
Uses the load/store unit, for which only one operation is allowed per bundle.
No latency constraints.
Exceptions:
DBREAK
CREG_ACCESS_VIOLATION
DBREAK
MISALIGNED_TRAP
DPU_NO_TRANSLATION
DPU_ACCESS_VIOLATION
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300 Operations
sth
s sth ISRC 2 [ R
SRC 1
] = R
SRC 2
10 01011 ISRC 2 SRC 2 SRC 1
Semantics: base ← SignExtend
32
(Imm( ISRC 2 )); offset ← SignExtend
32
( R
SRC 1 operand3 ← SignExtend
32
( R
);
SRC 2
); ea ← ZeroExtend
32
(base + offset);
IF (IsDBreakHit(ea))
THROW DBREAK;
IF (IsCRegSpace(ea))
THROW CREG_ACCESS_VIOLATION;
WriteCheckMemory
16
(ea);
WriteMemory
16
(ea, operand3);
Description:
Store half-word
Restrictions:
Uses the load/store unit, for which only one operation is allowed per bundle.
No latency constraints.
Exceptions:
DBREAK
CREG_ACCESS_VIOLATION
DBREAK
MISALIGNED_TRAP
DPU_NO_TRANSLATION
DPU_ACCESS_VIOLATION
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
stw
s stw ISRC 2 [ R
SRC 1
] = R
SRC 2
10 01010 ISRC 2 SRC 2 SRC 1
Semantics: base ← SignExtend
32
(Imm( ISRC 2 )); offset ← SignExtend
32
( R
SRC 1 operand3 ← SignExtend
32
( R
);
SRC 2
); ea ← ZeroExtend
32
(base + offset);
IF (IsDBreakHit(ea))
THROW DBREAK;
IF (IsCRegSpace(ea))
WriteCheckCReg(ea);
WriteCheckMemory
32
(ea);
IF (IsCRegSpace(ea))
WriteCReg(ea, operand3);
ELSE
WriteMemory
32
(ea, operand3);
Description:
Store word
Restrictions:
Uses the load/store unit, for which only one operation is allowed per bundle.
No latency constraints.
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Exceptions:
DBREAK
DBREAK
MISALIGNED_TRAP
DPU_NO_TRANSLATION
DPU_ACCESS_VIOLATION
CREG_NO_MAPPING
CREG_ACCESS_VIOLATION
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
sub
Register s sub R
DEST
= R
SRC 2
, R
SRC 1
00 0 0 00001 DEST
Semantics: operand2 ← SignExtend
32 operand1 ← SignExtend
32
( R
SRC 2
);
( R
SRC 1 result ← operand2 - operand1;
);
R
DEST
← Register(result);
Description:
Subtract
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 2 SRC 1
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sub
Immediate s sub R
IDEST
= ISRC 2 , R
SRC 1
00 1 0 00001 ISRC 2
Semantics: operand2 ← SignExtend
32
(Imm( ISRC 2 )); operand1 ← SignExtend
32
( R
SRC 1 result ← operand2 - operand1;
);
R
IDEST
← Register(result);
Description:
Subtract
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
IDEST SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
sxtb
s sxtb R
IDEST
= R
SRC 1
00 1 0 01110 000000000
Semantics: operand1 ← SignExtend
8 result ← operand1;
( R
SRC 1
);
R
IDEST
← Register(result);
Description:
Sign extend byte
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
IDEST SRC 1
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sxth
s sxth R
IDEST
= R
SRC 1
00 1 0 01110 000000001
Semantics: operand1 ← SignExtend
16 result ← operand1;
( R
SRC 1
);
R
IDEST
← Register(result);
Description:
Sign extend half
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
IDEST SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
sync
1 sync
10 10000
Semantics:
Sync();
Description:
Ensure synchronisation
Restrictions:
Uses the load/store unit, for which only one operation is allowed per bundle.
Must be the only syllable in the bundle.
No latency constraints.
Exceptions:
None.
307
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syscall
1 syscall
01 1111110
Semantics:
THROW ILL_INST;
Description:
System call
Restrictions:
Must be the only syllable in the bundle.
No latency constraints.
Exceptions:
ILL_INST
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
xor
Register s xor R
DEST
= R
SRC 1
, R
SRC 2
00 0 0 01101 DEST
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
( R
SRC 2 result ← operand1 ⊕ operand2;
);
R
DEST
← Register(result);
Description:
Bitwise exclusive-or
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
SRC 2 SRC 1
309
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xor
Immediate s xor R
IDEST
= R
SRC 1
, ISRC 2
00 1 0 01101 ISRC 2
Semantics: operand1 ← SignExtend
32 operand2 ← SignExtend
32
( R
SRC 1
);
(Imm( ISRC 2 )); result ← operand1 ⊕ operand2;
R
IDEST
← Register(result);
Description:
Bitwise exclusive-or
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
IDEST SRC 1
Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Operations
zxth
s zxth R
IDEST
= R
SRC 1
00 1 0 01110 000000011
Semantics: operand1 ← ZeroExtend
16 result ← operand1;
( R
SRC 1
);
R
IDEST
← Register(result);
Description:
Zero extend half
Restrictions:
No address/bundle restrictions.
No latency constraints.
Exceptions:
None.
IDEST SRC 1
311
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312 Operations
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Instruction encoding
A.1 Reserved bits
Any bits that are not defined are reserved. These bits must be set to 0.
A.2 Fields
Each instruction encoding is composed of a number of fields representing the operands. These are detailed in the following table.
BCOND
BDEST
BTARG
DEST
IBDEST
ICBUS
IDEST
Field Name Offset
12
6
12
6
23
18
0
IMM
ISRC 2
SCOND
SRC 1
SRC 2
0
12
21
0
6
Size Field represents
3 Branch register containing the branch condition.
3 Destination branch register for register format operations.
23 Branch offset value from PC.
6 Destination general purpose register for register format operations.
3 Destination branch register for immediate format operations.
9 Intercluster bus.
6 Destination general purpose register for immediate format operations.
23 23-bit value used to extend a short immediate.
9 9-bit short immediate value.
3 Source branch register used for select condition or carry.
6 General purpose source register.
6 General purpose source register.
Figure 17: Operand fields
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A.3 Formats
Int3R
Int3I
Monadic s
Cmp3R_Reg s s s
Cmp3R_Br
Cmp3I_Reg
Cmp3I_Br
Imm s s s s
SelectR
SelectI cgen
SysOp
Load
Store
Call
Branch s s s s s s s s
00 0 0 Opcode
00 1 0 Opcode
00 1 0 01110
00 0 1 0 Opcode
00 0 1 1 Opcode BDEST
00 1 1 0 Opcode
00 1 1 1 Opcode
01 Opcode
01 0 Opcode SCOND
01 1 Opcode SCOND
01 Opcode SCOND BDEST
01 Opcode
10 Opcode
10 Opcode
11 0 Opcode
11 1 O p c o d e
BCOND
DEST
ISRC 2
Opcode
DEST
ISRC
ISRC
ISRC
ISRC
2
2
DEST
ISRC 2
DEST
2
2
Figure 18: Formats
BTARG
BTARG
IDEST
SRC 2
SRC 2
IDEST
IDEST
SRC 2
SRC 2
IDEST
IBDEST
IMM
SRC 2
IDEST
SRC 2
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
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Several important points:
•
The
BUNDLE STOP
bit indicates the end of bundle and is set in the last syllable of the bundle.
•
The
CLUSTER
bit is reserved; in ST220 it is set to zero.
•
The format bits are used to decode the class of operation. There are four formats:
Integer
Specific
Memory arithmetic, comparison immediate extension, selects, extended arithmetic load, store
Control transfer branch, call, rfi, goto
•
Additional decoding is performed using the most significant instruction bits.
•
Int3 operations have two base formats, register ( Int3R ) and immediate ( Int3I ).
Bit 27 specifies the Int3 format, 0=register format, 1=immediate format. In register format, the operation consists of R
DEST
= R
SRC 1
Op R
SRC 2
. Immediate format consists of R
DEST
= R
SRC 1
Op IMMEDIATE .
•
Cmp3 format is similar to Int3 except it can have as a destination either a general purpose register or a branch register ( B
BDEST
). In register format, the target register specifier occupies bits 12 to 17, while the target branch register bits 18 to 20. In immediate format, bits 6 to 11 specify either the target general purpose register or target branch register (bits 6 to 8).
•
Load operations follow R
DEST
= Mem[ R
SRC 1
+ IMMEDIATE ] semantics, while stores follow Mem[ R
SRC 1
+ IMMEDIATE ] = R
SRC 2
. Thus bits 6 to 11 specify either the target destination register ( R
DEST
) or the second operand source register
( R
SRC 2
), depending on whether the operation is a load or store .
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A.4 Opcodes
* These operations are not supported by the hardware, but the opcodes are reserved for software investigations.
mulll mulllu mullh mullhu mulhh mulhhu mulhs cmpeq maxu min minu mulhhs mull mullu mulh mulhu add sub shl shr shru sh1add sh2add sh3add sh4add and andc or orc xor mullhus max s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s
00 0 0
00 0 0
00 0 0
00 0 0
00 0 0
00 0 0
00 0 0
00 0 0
00 0 0
00 0 0
00 0 0
00 0 0
00 0 0
00 0 0
00 0 0
00 0 0
00 0 0
00 0 0
00 0 0
00 0 0
00 0 0
00 0 0
00 0 0
00 0 0
00 0 0
00 0 0
00 0 0
00 0 0
11001
11010
11011
11100
00 0 0
00 0 0
11101
11110
00 0 0 11111
00 0 1 0 0000
10001
10010
10011
10100
10101
10110
10111
11000
01000
01001
01010
01011
01100
01101
01111
10000
00000
00001
00010
00011
00100
00101
00110
00111
Figure 19: Instruction encodings
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
317 nandl orl norl add sub shl shr shru cmpgeu cmpgt cmpgtu cmple cmpleu cmplt cmpltu andl sh1add sh2add sh3add sh4add and cmpltu andl nandl orl norl cmpeq cmpne cmpge cmpne cmpge cmpgeu cmpgt cmpgtu cmple cmpleu cmplt s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s
00 0 1 0 0001
00 0 1 0 0010
00 0 1 0 0011
00 0 1 0 0100
00 0 1 0 0101
00 0 1 0 0110
00 0 1 0 0111
00 0 1 0 1000
00 0 1 0 1001
00 0 1 0 1010
00 0 1 0 1011
00 0 1 0 1100
00 0 1 0 1101
00 0 1 1 0000
00 0 1 1 0001
00 0 1 1 0010
00 0 1 1 0011
00 0 1 1 0100
00 0 1 1 0101
00 0 1 1 0110
00 0 1 1 0111
00 0 1 1 1000
00 0 1 1 1001
00 0 1 1 1010
00 0 1 1 1011
00 0 1 1 1100
00 0 1 1 1101
00 1 0 00000
00 1 0
00 1 0
00 1 0
00 1 0
00001
00010
00011
00100
00 1 0
00 1 0
00 1 0
00 1 0
00 1 0
00101
00110
00111
01000
01001
BDEST
BDEST
BDEST
BDEST
BDEST
BDEST
BDEST
BDEST
BDEST
BDEST
BDEST
BDEST
BDEST
BDEST
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
Figure 19: Instruction encodings
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
IDEST
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ST220 Core and Instruction Set Architecture Manual
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
318 mullu mulh mulhu mulll mulllu mullh mullhu mulhh mulhhu mulhs cmpeq cmpne cmpge cmpgeu cmpgt cmpgtu cmple cmpleu cmplt cmpltu andl andc or orc xor sxtb sxth bswap zxth clz mullhus max maxu min minu mulhhs mull s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s
00 1 0
00 1 0
00 1 0
00 1 0
00 1 0
00 1 0
00 1 0
00 1 0
00 1 0
00 1 0
00 1 0
00 1 0
00 1 0
00 1 0
00 1 0
00 1 0
00 1 0
00 1 0
00 1 0
00 1 0
00 1 0
00 1 0
00 1 0
00 1 0
00 1 0
00 1 0
11110
11111
00 1 1 0 0000
00 1 1 0 0001
00 1 1 0 0010
00 1 1 0 0011
00 1 1 0 0100
00 1 1 0 0101
10110
10111
11000
11001
11010
11011
11100
11101
00 1 1 0 0110
00 1 1 0 0111
00 1 1 0 1000
00 1 1 0 1001
00 1 1 0 1010
01110
01111
10000
10001
10010
10011
10100
10101
01010
01011
01100
01101
01110
01110
01110
01110
Figure 19: Instruction encodings
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
000000000
000000001
000000010
000000011
000000100
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
319 slctf prgins sbrk syscall break ldw ldw.d
ldh norl slct slctf addcg divs imml immr slct ldh.d
ldhu ldhu.d
ldb ldb.d
cmpgtu cmple cmpleu cmplt cmpltu andl nandl orl nandl orl norl cmpeq cmpne cmpge cmpgeu cmpgt s s s s
1
1 s
1 s s s s s s s s s s s s s s s s s s s s s s s s s s s s s
10
10
10
10
10
01
10
10
10
00 1 1 0 1011
00 1 1 0 1100
00 1 1 0 1101
00 1 1 1 0000
00 1 1 1 0001
00 1 1 1 0010
00 1 1 1 0011
00 1 1 1 0100
00 1 1 1 0101
00 1 1 1 0110
00 1 1 1 0111
00 1 1 1 1000
00 1 1 1 1001
00 1 1 1 1010
00 1 1 1 1011
00 1 1 1 1100
00 1 1 1 1101
01 0 000 SCOND
01 0 001 SCOND
01 0010 SCOND BDEST
01
01
0100
01010
SCOND BDEST
01 01011
01 1 000 SCOND
01 1 001 SCOND
01 1111100
01
01
1111101
1111110
1111111
0000
0000
0001
0
1
0
0001 1
0010 0
0010 1
0011 0
0011 1
ISRC
ISRC
2
2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
Figure 19: Instruction encodings
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
DEST
DEST
DEST
DEST
IMM
IMM
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IBDEST
IBDEST
IBDEST
IBDEST
IBDEST
IBDEST
IBDEST
IBDEST
IBDEST
IBDEST
IBDEST
IBDEST
IBDEST
IBDEST
SRC 2
SRC 2
SRC 2
SRC 2
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
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ST220 Core and Instruction Set Architecture Manual
320 asm,5 * asm,6 * asm,7 * asm,8 * asm,9 * asm,10 * asm,11 * asm,12 * asm,13 * asm,14 * asm,15 * asm,0 * asm,1 * asm,2 * asm,3 * asm,4 * asm,5 * asm,6 * asm,7 * asm,8 * asm,9 * ldbu ldbu.d
stw sth stb pft prgadd prgset sync send * recv * asm,0 * asm,1 * asm,2 * asm,3 * asm,4 * s s s s s s s s s s s s s s s s s s s s s s s s s s s
1 s s s s s s s s s
10 1 1
10 1 1
10 1 1
10 1 1
10 1 1
10 1 1
10 1 1
10 1 1
10 1 1
10 1 1
10 1 1
10 1 1
10 1 1
10 1 1
10 1 1
10 1 1
10 1 1
10 1 1
10 1 1
10 1 1
10 1 1
10
10
10
10
10
10
10
10
0100 0
0100 1
01010
01011
01100
01101
01110
01111
10 10000
10 1 0 00100
10 1 0
10 1 1
01000
00000
10 1 1
10 1 1
10 1 1
10 1 1
00001
00010
00011
00100
01101
01110
01111
10000
10001
10010
10011
10100
00101
00110
00111
01000
01001
01010
01011
01100
10101
10110
10111
11000
11001
ISRC
ISRC
ISRC
ISRC
ISRC
ISRC
ISRC
ISRC
2
2
2
2
2
2
2
2
Figure 19: Instruction encodings
ICBUS
ICBUS
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
DEST
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
ISRC 2
IDEST
IDEST
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
IDEST
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
SRC 2
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
ADCS 7395369G
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
goto goto rfi br brf asm,10 * asm,11 * asm,12 * asm,13 * asm,14 * asm,15 * call call s s s s s s s s s s s s s
10 1 1
10 1 1
10 1 1
10 1 1
11010
11011
11100
11101
10 1 1
10 1 1
11110
11111
11 0 000 0
11 0 000 1
11 0 001 0
11 0 001 1
11 0 010 0
11 1 0 BCOND
11 1 1 BCOND
ISRC
ISRC
ISRC
ISRC
ISRC
ISRC
2
2
2
2
2
2
Figure 19: Instruction encodings
BTARG
BTARG
BTARG
BTARG
IDEST
IDEST
IDEST
IDEST
IDEST
IDEST
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
SRC 1
321
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ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
®
Glossary
Branch registers The set of eight 1-bit registers that encode the condition for conditional branches and carry bits.
Bundle Wide instruction of multiple operations always issued during the same cycle and executed in parallel.
Cluster
Control register One of a set of address mapped registers maintained by the hardware (or operating system or user). These registers may have side effects and may require supervisor access permissions.
Dispersal
Collection of tightly coupled functional units and register files that perform the computational tasks in an ST200.
The operation of extracting and routing the syllables of one bundle stored in the I-cache line to the proper slots in the bundle buffer. To avoid using I-cache space for empty syllables, only non-empty syllables are stored in the I-cache lines. Hence, it is necessary to “disperse” the syllable of each bundle to the full-size bundle buffer.
General-purpose registers The set of directly addressed fixed-point registers.
ST200 contains one GR file per cluster organized as a bank of 64
32-bit registers. The compiler is responsible for explicitly scheduling data transfers among GRs residing in different clusters.
Level-1 I-cache Level-1 instruction cache also referred as the “closest” or “lowest” cache. Similar notations apply to the Level-1 data cache. ST200 supports multiple Level-1 data caches.
Main memory This is the system-accessible memory, cached.
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Operation
Predication
Speculative
Superscalar
Syllable
VLIW
An operation is an atomic ST200 action, in general considered roughly equivalent to a typical instruction of a traditional 32-bit
RISC machine.
The operation of selectively quashing an operation according to the value of a register (called predicate). One of the simplest forms of predication is a select operation, which is supported in ST200.
A speculative operation (also known as “eager”) is an operation executed prior to the resolution of the branch under which the operation would normally execute. Special attention must be paid to speculative memory load operations to handle the possible resulting exceptions. Speculative memory load operation are sometimes called “dismissible” as any exception deriving from the operation has to be ignored (“dismissed”) by the system.
An architecture with multiple functional units in which instructions are scheduled dynamically by the hardware at run-time.
Encoded component of a bundle that specifies one operation to be executed by the machine functional units. Syllables are composed of register and/or immediate fields and opcode specifiers. A bundle in ST200 may contain multiple syllables, each of them 32-bit wide.
The syllable is also the indivisible unit for the bundle compression/dispersal.
Very long instruction word: instructions (called “bundles” in
ST200 terminology) potentially encode multiple, independent operations, and are fully scheduled at compile time.
STMicroelectronics Confidential
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Index
Numerics
A
B
C
cache 323 carry 323 cluster 323
D
ADCS 7395369G
E
F
FOR 114-115, 117, 121, 125, 127-128, 130
Function
CregReadAccessViolation(index) 124
CregWriteAccessViolation(index) 124
DisReadCheckMemory(address) 126
DPUSpecLoadRetZero(address) 124
InitiateExceptionHandler() 108
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ReadAccessViolation(address) 124
UndefinedControlRegister(address) 124
WriteAccessViolation(address) 124
WriteCheckControl(address) 132
WriteControl(address, value) 132
WriteMemory(address, value) 130
I
L
M
N
O
P
R
S
T
U
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XYZ
327
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ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
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