Instruction encoding. STMicroelectronics ST200-TOOLSET

Instruction encoding

A.1 Reserved bits

Any bits that are not defined are reserved. These bits must be set to 0.

A.2 Fields

Each instruction encoding is composed of a number of fields representing the operands. These are detailed in the following table.

BCOND

BDEST

BTARG

DEST

IBDEST

ICBUS

IDEST

Field Name Offset

12

6

12

6

23

18

0

IMM

ISRC 2

SCOND

SRC 1

SRC 2

0

12

21

0

6

Size Field represents

3 Branch register containing the branch condition.

3 Destination branch register for register format operations.

23 Branch offset value from PC.

6 Destination general purpose register for register format operations.

3 Destination branch register for immediate format operations.

9 Intercluster bus.

6 Destination general purpose register for immediate format operations.

23 23-bit value used to extend a short immediate.

9 9-bit short immediate value.

3 Source branch register used for select condition or carry.

6 General purpose source register.

6 General purpose source register.

Figure 17: Operand fields

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A.3 Formats

Int3R

Int3I

Monadic s

Cmp3R_Reg s s s

Cmp3R_Br

Cmp3I_Reg

Cmp3I_Br

Imm s s s s

SelectR

SelectI cgen

SysOp

Load

Store

Call

Branch s s s s s s s s

00 0 0 Opcode

00 1 0 Opcode

00 1 0 01110

00 0 1 0 Opcode

00 0 1 1 Opcode BDEST

00 1 1 0 Opcode

00 1 1 1 Opcode

01 Opcode

01 0 Opcode SCOND

01 1 Opcode SCOND

01 Opcode SCOND BDEST

01 Opcode

10 Opcode

10 Opcode

11 0 Opcode

11 1 O p c o d e

BCOND

DEST

ISRC 2

Opcode

DEST

ISRC

ISRC

ISRC

ISRC

2

2

DEST

ISRC 2

DEST

2

2

Figure 18: Formats

BTARG

BTARG

IDEST

SRC 2

SRC 2

IDEST

IDEST

SRC 2

SRC 2

IDEST

IBDEST

IMM

SRC 2

IDEST

SRC 2

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

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Several important points:

•

The

BUNDLE STOP

bit indicates the end of bundle and is set in the last syllable of the bundle.

•

The

CLUSTER

bit is reserved; in ST220 it is set to zero.

•

The format bits are used to decode the class of operation. There are four formats:

Integer

Specific

Memory arithmetic, comparison immediate extension, selects, extended arithmetic load, store

Control transfer branch, call, rfi, goto

•

Additional decoding is performed using the most significant instruction bits.

•

Int3 operations have two base formats, register ( Int3R ) and immediate ( Int3I ).

Bit 27 specifies the Int3 format, 0=register format, 1=immediate format. In register format, the operation consists of R

DEST

= R

SRC 1

Op R

SRC 2

. Immediate format consists of R

DEST

= R

SRC 1

Op IMMEDIATE .

•

Cmp3 format is similar to Int3 except it can have as a destination either a general purpose register or a branch register ( B

BDEST

). In register format, the target register specifier occupies bits 12 to 17, while the target branch register bits 18 to 20. In immediate format, bits 6 to 11 specify either the target general purpose register or target branch register (bits 6 to 8).

•

Load operations follow R

DEST

= Mem[ R

SRC 1

+ IMMEDIATE ] semantics, while stores follow Mem[ R

SRC 1

+ IMMEDIATE ] = R

SRC 2

. Thus bits 6 to 11 specify either the target destination register ( R

DEST

) or the second operand source register

( R

SRC 2

), depending on whether the operation is a load or store .

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A.4 Opcodes

* These operations are not supported by the hardware, but the opcodes are reserved for software investigations.

mulll mulllu mullh mullhu mulhh mulhhu mulhs cmpeq maxu min minu mulhhs mull mullu mulh mulhu add sub shl shr shru sh1add sh2add sh3add sh4add and andc or orc xor mullhus max s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s

00 0 0

00 0 0

00 0 0

00 0 0

00 0 0

00 0 0

00 0 0

00 0 0

00 0 0

00 0 0

00 0 0

00 0 0

00 0 0

00 0 0

00 0 0

00 0 0

00 0 0

00 0 0

00 0 0

00 0 0

00 0 0

00 0 0

00 0 0

00 0 0

00 0 0

00 0 0

00 0 0

00 0 0

11001

11010

11011

11100

00 0 0

00 0 0

11101

11110

00 0 0 11111

00 0 1 0 0000

10001

10010

10011

10100

10101

10110

10111

11000

01000

01001

01010

01011

01100

01101

01111

10000

00000

00001

00010

00011

00100

00101

00110

00111

Figure 19: Instruction encodings

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

STMicroelectronics

ST220 Core and Instruction Set Architecture Manual ADCS 7395369G

317 nandl orl norl add sub shl shr shru cmpgeu cmpgt cmpgtu cmple cmpleu cmplt cmpltu andl sh1add sh2add sh3add sh4add and cmpltu andl nandl orl norl cmpeq cmpne cmpge cmpne cmpge cmpgeu cmpgt cmpgtu cmple cmpleu cmplt s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s

00 0 1 0 0001

00 0 1 0 0010

00 0 1 0 0011

00 0 1 0 0100

00 0 1 0 0101

00 0 1 0 0110

00 0 1 0 0111

00 0 1 0 1000

00 0 1 0 1001

00 0 1 0 1010

00 0 1 0 1011

00 0 1 0 1100

00 0 1 0 1101

00 0 1 1 0000

00 0 1 1 0001

00 0 1 1 0010

00 0 1 1 0011

00 0 1 1 0100

00 0 1 1 0101

00 0 1 1 0110

00 0 1 1 0111

00 0 1 1 1000

00 0 1 1 1001

00 0 1 1 1010

00 0 1 1 1011

00 0 1 1 1100

00 0 1 1 1101

00 1 0 00000

00 1 0

00 1 0

00 1 0

00 1 0

00001

00010

00011

00100

00 1 0

00 1 0

00 1 0

00 1 0

00 1 0

00101

00110

00111

01000

01001

BDEST

BDEST

BDEST

BDEST

BDEST

BDEST

BDEST

BDEST

BDEST

BDEST

BDEST

BDEST

BDEST

BDEST

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

Figure 19: Instruction encodings

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

IDEST

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ST220 Core and Instruction Set Architecture Manual

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

318 mullu mulh mulhu mulll mulllu mullh mullhu mulhh mulhhu mulhs cmpeq cmpne cmpge cmpgeu cmpgt cmpgtu cmple cmpleu cmplt cmpltu andl andc or orc xor sxtb sxth bswap zxth clz mullhus max maxu min minu mulhhs mull s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s

00 1 0

00 1 0

00 1 0

00 1 0

00 1 0

00 1 0

00 1 0

00 1 0

00 1 0

00 1 0

00 1 0

00 1 0

00 1 0

00 1 0

00 1 0

00 1 0

00 1 0

00 1 0

00 1 0

00 1 0

00 1 0

00 1 0

00 1 0

00 1 0

00 1 0

00 1 0

11110

11111

00 1 1 0 0000

00 1 1 0 0001

00 1 1 0 0010

00 1 1 0 0011

00 1 1 0 0100

00 1 1 0 0101

10110

10111

11000

11001

11010

11011

11100

11101

00 1 1 0 0110

00 1 1 0 0111

00 1 1 0 1000

00 1 1 0 1001

00 1 1 0 1010

01110

01111

10000

10001

10010

10011

10100

10101

01010

01011

01100

01101

01110

01110

01110

01110

Figure 19: Instruction encodings

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

000000000

000000001

000000010

000000011

000000100

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

STMicroelectronics

ST220 Core and Instruction Set Architecture Manual ADCS 7395369G

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

319 slctf prgins sbrk syscall break ldw ldw.d

ldh norl slct slctf addcg divs imml immr slct ldh.d

ldhu ldhu.d

ldb ldb.d

cmpgtu cmple cmpleu cmplt cmpltu andl nandl orl nandl orl norl cmpeq cmpne cmpge cmpgeu cmpgt s s s s

1

1 s

1 s s s s s s s s s s s s s s s s s s s s s s s s s s s s s

10

10

10

10

10

01

10

10

10

00 1 1 0 1011

00 1 1 0 1100

00 1 1 0 1101

00 1 1 1 0000

00 1 1 1 0001

00 1 1 1 0010

00 1 1 1 0011

00 1 1 1 0100

00 1 1 1 0101

00 1 1 1 0110

00 1 1 1 0111

00 1 1 1 1000

00 1 1 1 1001

00 1 1 1 1010

00 1 1 1 1011

00 1 1 1 1100

00 1 1 1 1101

01 0 000 SCOND

01 0 001 SCOND

01 0010 SCOND BDEST

01

01

0100

01010

SCOND BDEST

01 01011

01 1 000 SCOND

01 1 001 SCOND

01 1111100

01

01

1111101

1111110

1111111

0000

0000

0001

0

1

0

0001 1

0010 0

0010 1

0011 0

0011 1

ISRC

ISRC

2

2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

Figure 19: Instruction encodings

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

DEST

DEST

DEST

DEST

IMM

IMM

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IBDEST

IBDEST

IBDEST

IBDEST

IBDEST

IBDEST

IBDEST

IBDEST

IBDEST

IBDEST

IBDEST

IBDEST

IBDEST

IBDEST

SRC 2

SRC 2

SRC 2

SRC 2

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

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ST220 Core and Instruction Set Architecture Manual

320 asm,5 * asm,6 * asm,7 * asm,8 * asm,9 * asm,10 * asm,11 * asm,12 * asm,13 * asm,14 * asm,15 * asm,0 * asm,1 * asm,2 * asm,3 * asm,4 * asm,5 * asm,6 * asm,7 * asm,8 * asm,9 * ldbu ldbu.d

stw sth stb pft prgadd prgset sync send * recv * asm,0 * asm,1 * asm,2 * asm,3 * asm,4 * s s s s s s s s s s s s s s s s s s s s s s s s s s s

1 s s s s s s s s s

10 1 1

10 1 1

10 1 1

10 1 1

10 1 1

10 1 1

10 1 1

10 1 1

10 1 1

10 1 1

10 1 1

10 1 1

10 1 1

10 1 1

10 1 1

10 1 1

10 1 1

10 1 1

10 1 1

10 1 1

10 1 1

10

10

10

10

10

10

10

10

0100 0

0100 1

01010

01011

01100

01101

01110

01111

10 10000

10 1 0 00100

10 1 0

10 1 1

01000

00000

10 1 1

10 1 1

10 1 1

10 1 1

00001

00010

00011

00100

01101

01110

01111

10000

10001

10010

10011

10100

00101

00110

00111

01000

01001

01010

01011

01100

10101

10110

10111

11000

11001

ISRC

ISRC

ISRC

ISRC

ISRC

ISRC

ISRC

ISRC

2

2

2

2

2

2

2

2

Figure 19: Instruction encodings

ICBUS

ICBUS

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

DEST

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

ISRC 2

IDEST

IDEST

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

IDEST

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

SRC 2

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

STMicroelectronics

ST220 Core and Instruction Set Architecture Manual

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

ADCS 7395369G

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

goto goto rfi br brf asm,10 * asm,11 * asm,12 * asm,13 * asm,14 * asm,15 * call call s s s s s s s s s s s s s

10 1 1

10 1 1

10 1 1

10 1 1

11010

11011

11100

11101

10 1 1

10 1 1

11110

11111

11 0 000 0

11 0 000 1

11 0 001 0

11 0 001 1

11 0 010 0

11 1 0 BCOND

11 1 1 BCOND

ISRC

ISRC

ISRC

ISRC

ISRC

ISRC

2

2

2

2

2

2

Figure 19: Instruction encodings

BTARG

BTARG

BTARG

BTARG

IDEST

IDEST

IDEST

IDEST

IDEST

IDEST

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

SRC 1

321

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STMicroelectronics

ST220 Core and Instruction Set Architecture Manual ADCS 7395369G