Control registers
The ST220 control registers contain processor state which is not commonly accessed by application code. This includes accessing the protection units, PSW , exception registers and breakpoint registers.
Control registers
1
are mapped into the address space, allowing access through normal load and store operations.
All control register accesses are word (32-bit) operations. Byte and half word load and stores to control registers are not supported and will generate
CREG _ ACCESS _ VIOLATION exceptions.
Dismissible loads to control register space always return zero. Control register loads or stores are executed within the LSU without reference to the DPU regions.
9.2 Exceptions
The control register unit generates an exception when a load or store tries to:
•
access a control register that does not exist ( CREG _ NO _ MAPPING ),
•
write to a control register without correct permissions
( CREG _ ACCESS _ VIOLATION ),
1. Control registers can not be accessed via the STBus.
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ST220 Core and Instruction Set Architecture Manual
66 Control register addresses
•
perform a byte and half word accesses to control registers
( CREG _ ACCESS _ VIOLATION ),
•
perform a misaligned word access to a control register (
CREG
_
NO
_
MAPPING
)
For details of the exception cause register see
Section 5.6: Exception types and priorities on page 34
.
PSW
SAVED _ PSW
SAVED _ PC
Below is a table of the control register addresses on the ST220.
The control registers start from a base of 0xFFFF0000, offsets listed in the table are relative to this.
The Access column shows the access rights in user and supervisor mode.
NA No access (protection fault)
RO
RW
CF
Read only
Read/Write
Configurable
Name
HANDLER _ PC
EXCEPT _ CAUSE
Offset
Access
(U/S)
Comment
0xfff8
0xfff0
RO/RW
RO/RW
The Program Status Word.
Saved PSW, written by hardware on exception.
0xffe8
0xffe0
0xffd8
RO/RW
RO/RW
RO/RW
Saved Program Counter, written by hardware on exception.
The address of the exception handler code.
A one hot vector of trap (exception/interrupt) types, indicating the cause of the last trap.
Written by the hardware on a trap.
Table 11: Control Registers - BASE: CREG_BASE
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Control register addresses 67
SCRATCH 1
SCRATCH 2
DPU _ REGION 0
DPU _ ATR 0
DPU _ REGION 1
DPU _ ATR 1
DPU _ REGION 2
DPU _ ATR 2
DPU _ REGION 3
DPU _ ATR 3
DPU _ REGION 4
DPU _ ATR 4
DPU _ REGION 5
DPU _ ATR 5
Name
EXCEPT _ ADDR
ST 200_ VERSION
SAVED _ SAVED _ PSW
SAVED _ SAVED _ PC
PERIPHERAL _ BASE
Offset
Access
(U/S)
Comment
0xffd0
0xffc8
RO/RW
RO/RO
This will be the data effective address in the case of either a DPU, CREG, DBREAK, or
MISALIGNED_TRAP exception. For other exception types this register will be zero.
The version number of the core. For the
ST220 returns 0x01.
0xffc0
0xffb8
0xffb0
RO/RW
RO/RW
RO/RO
PSW saved by debug unit interrupt.
PC saved by debug unit interrupt.
0xffa8
0xffa0
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
Base address of peripheral registers. The top
12 bits of this register are wired to the peripheral base input pins.
Scratch register reserved for use by the interrupt handler.
Scratch register reserved for use by the debug interrupt handler.
DPU region address.
0xff80
0xff78
0xff70
0xff68
0xff60
0xff58
0xff50
0xff48
0xff40
0xff38
0xff30
DPU region attribute.
DPU region address.
DPU region attribute.
DPU region address.
DPU region attribute.
DPU region address.
DPU region attribute.
DPU region address.
DPU region attribute.
DPU region address.
0xff28 RO/RW DPU region attribute.
Table 11: Control Registers - BASE: CREG_BASE
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ST220 Core and Instruction Set Architecture Manual
68 Control register addresses
Name
DPU _ REGION 6
DPU _ ATR 6
DPU _ REGION 7
DPU _ ATR 7
DBREAK _ LOWER
DBREAK _ UPPER
DBREAK _ CONTROL
IPU _ REGION 0
IPU _ ATR 0
IPU _ REGION 1
IPU _ ATR 1
IPU _ REGION 2
IPU _ ATR 2
IPU _ REGION 3
IPU _ ATR 3
IBREAK _ LOWER
IBREAK _ UPPER
IBREAK _ CONTROL
PM _ CR
PM _ CNT 0
PM _ CNT 1
PM _ CNT 2
PM _ CNT 3
PM _ PCLK
Offset
Access
(U/S)
Comment
0xfe38
0xfe30
0xfe28
0xfe20
0xfe18
0xfe10
0xfe08
0xfdd0
0xff20
0xff18
0xff10
0xff08
0xfe80
0xfe78
0xfe70
0xfe40
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
RO/RW
DPU region address.
DPU region attribute.
DPU region address.
DPU region attribute.
Data breakpoint lower address.
Data breakpoint upper address.
Data breakpoint control.
IPU region address.
IPU region attribute.
IPU region address.
IPU region attribute.
IPU region address.
IPU region attribute.
IPU region address.
IPU region attribute.
Instruction breakpoint lower address.
0xfdc8
0xfdc0
0xf800
0xf808
RO/RW
RO/RW
RO/RW
RO/RW
Instruction breakpoint upper address.
Instruction breakpoint control.
Performance monitoring control.
Performance monitor counter 0 value.
0xf810
0xf818
0xf820
0xf828
RO/RW
RO/RW
RO/RW
RO/RO
Performance monitor counter 1 value.
Performance monitor counter 2 value.
Performance monitor counter 3 value.
Performance monitor core cycle counter.
Table 11: Control Registers - BASE: CREG_BASE
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Control register addresses
Name
SDI 0_ DATA
SDI 0_ READY
SDI 0_ CONTROL
SDI 0_ COUNT
SDI 0_ TIMEOUT
SDI 1_ DATA
SDI 1_ READY
SDI 1_ CONTROL
SDI 1_ COUNT
SDI 1_ TIMEOUT
SDI 2_ DATA
SDI 2_ READY
SDI 2_ CONTROL
SDI 2_ COUNT
SDI 2_ TIMEOUT
SDI 3_ DATA
SDI 3_ READY
SDI 3_ CONTROL
SDI 3_ COUNT
SDI 3_ TIMEOUT
Offset
Access
(U/S)
Comment
0xe418
0xe420
0xe800
0xe808
0xe810
0xe818
0xe820
0xec00
0xe000
0xe008
0xe010
0xe018
0xe020
0xe400
0xe408
0xe410
CF/RW
CF/RW
RO/RW
RO/RW
RO/RW
CF/RW
CF/RW
RO/RW
RO/RW
RO/RW
CF/RW
CF/RW
RO/RW
RO/RW
RO/RW
CF/RW
SDI 0 data.
SDI 0 ready.
SDI 0 control.
SDI 0 count.
SDI 0 timeout.
SDI 1 data.
SDI 1 ready.
SDI 1 control.
SDI 1 count.
SDI 1 timeout.
SDI 2 data.
SDI 2 ready.
SDI 2 control.
SDI 2 count.
SDI 2 timeout.
SDI 3 data.
0xec08
0xec10
0xec18
0xec20
CF/RW
RO/RW
RO/RW
RO/RW
SDI 3 ready.
SDI 3 control.
SDI 3 count.
SDI 3 timeout.
Table 11: Control Registers - BASE: CREG_BASE
69
ADCS 7395369G
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual
70 Control register addresses
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
