Peripheral addresses
On the ST220 the interrupt controller, DSU, DSU ROM and the timers are memory mapped peripherals. Under normal usage these peripherals should, with the exception of the DSU ROM, be mapped in an uncacheable region in the DPU.
11.1 Peripheral addresses
Below is a table of the peripheral register addresses on the ST220.
The peripheral registers start from the peripheral base address which can be found by reading the PERIPHERAL _ BASE
register (see Chapter 9: Control registers on page 65
).
The Access column shows the access rights:
RO Read only
RW
CF
Read/write
Configurable
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ST220 Core and Instruction Set Architecture Manual
76 Peripheral addresses
TIMESTART
TIMECNST 0
TIMECNTR 0
TIMECNTL 0
TIMECNST 1
TIMECNTR 1
TIMECNTL 1
TIMECNST 2
TIMECNTR 2
TIMECNTL 2
INTPENDING 0
INTPENDING 1
INTMASK 0
INTMASK 1
INTTEST 0
INTTEST 1
INTCLR 0
INTCLR 1
INTSET 0
INTSET 1
TIMEDIVIDE
INTMASKCLR 0
INTMASKCLR 1
INTMASKSET 0
11.1.1 Interrupt controller & timer registers
The interrupt controller and timer registers start from PERIPHERAL _ BASE + 0x0.
Name Offset
Access
(U/S)
Comment
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RO
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0x40
0x48
0x50
0x58
0x60
0x68
0x70
0x78
0x0
0x8
0x10
0x18
0x20
0x28
0x30
0x38
0x80
0x88
0x90
0x98
0x100
0x108
0x110
0x118
Table 16: Interrupt Controller - BASE: INTCR_BASE
Interrupt pending bits 31:0.
Interrupt pending bits 63:32.
Interrupt mask bits 31:0.
Interrupt mask bits 63:32.
Interrupt test register bits 31:0.
Interrupt test register bits 63:32.
Interrupt clear register bits 31:0.
Interrupt clear register bits 63:32.
Interrupt set register bits 31:0.
Interrupt clear register bits 63:32.
Timer start.
Timer constant.
Timer counter.
Timer control.
Timer constant.
Timer counter.
Timer control.
Timer constant.
Timer counter.
Timer control.
Timer divide.
Interrupt mask clear bits 31:0.
Interrupt mask clear bits 63:32.
Interrupt mask set bits 31:0.
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Peripheral addresses
Name
INTMASKSET 1
Offset
Access
(U/S)
Comment
0x120 RW Interrupt mask set bits 63:32.
Table 16: Interrupt Controller - BASE: INTCR_BASE
DSR 7
DSR 8
DSR 9
DSR 10
DSR 11
DSR 12
DSR 13
DSR 14
DSR 0
DSR 1
DSR 2
DSR 3
DSR 4
DSR 5
DSR 6
DSR 15
DSR 16
DSR 17
DSR 18
11.1.2 DSU registers
The interrupt controller registers start from PERIPHERAL _ BASE + 0x3000
Name Offset
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
RW
RW
RW
RW
RW
RW
Access
(U/S)
Comment
0x38
0x40
0x48
0x50
0x58
0x60
0x68
0x70
0x0
0x8
0x10
0x18
0x20
0x28
0x30
0x78
0x80
0x88
0x90
Table 17: Debug Support Unit - BASE: DSU_BASE
DSU version.
DSU status.
DSU output.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
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78 Peripheral addresses
DSR 19
DSR 20
DSR 21
DSR 22
DSR 23
DSR 24
DSR 25
DSR 26
DSR 27
DSR 28
DSR 29
DSR 30
DSR 31
Name Offset
Access
(U/S)
Comment
0x98
0xa0
0xa8
0xb0
0xb8
0xc0
0xc8
0xd0
0xd8
0xe0
0xe8
0xf0
0xf8
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
DSU communication.
Table 17: Debug Support Unit - BASE: DSU_BASE
11.1.3 DSU ROM
The DSU ROM starts from PERIPHERAL _ BASE + 0x4000 (see
Chapter 13: Debugging support on page 85 ).
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
