Interrupt controller
The ST220 interrupt controller supports up to 64 interrupt sources. The system is programmed via a number of 64-bit memory-mapped control registers.
12.1 Architecture
The structure of the interrupt controller is shown in Figure 8 .
External
Events
‘OR’
64 lines
‘AND’
64 lines
OR
Interrupt Line
To Processor
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64 bits 64 bits
Figure 8: Interrupt controller
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12.2 Operation
An interrupting event takes an interrupt line high. This is then sampled, causing the corresponding bit in the 64-bit
INTPENDING
register to be set. The
INTPENDING register is then parallel AND-ed with the
INTMASK
register. The masked interrupts are then OR-red into a single interrupt line that is presented to the processor core.
This architecture ensures that:
•
all external interrupts will interrupt the processor,
•
interrupts can be individually enabled or disabled.
Setting or clearing bits in the
INTMASK
register enables or disables the corresponding interrupt lines.
12.2.1 Test register
External interrupts are wide OR-ed with the contents of the INTTEST register before being sampled by the INTPENDING register. This allows the programmer to simulate interrupts into the processor for test purposes.
12.3 Interrupt registers
For the addresses of these memory mapped registers see Chapter 11: Peripheral addresses on page 75
.
12.3.1 Interrupt pending register
The 64-bit
INT PENDING
register holds the current interrupt status. Bits in this register are set by external interrupts or the
INTTEST
register.
A number of bits in the
INTPENDING
register are preassigned to ST220 peripherals.
The remaining bits can be assigned to other peripherals or external devices.
Name:
INTPENDING
0[31:0],
INTPENDING
1[63:32 ]
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ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Interrupt registers 81
TIMER 0
TIMER 1
TIMER 2
Reserved
Reserved
Name
0
1
Bit(s)
2
[15:3]
Access
(U/S)
RO/RO
RO/RO
RO/RO
RO/RO
[31:16] RO/RO
Reset
0x0
0x0
0x0
0x0
0x0
Comment
Interrupt is pending from timer 0.
Interrupt is pending from timer 1.
Interrupt is pending from timer 2.
System defined - refer to data sheet.
System defined non-maskable interrupts
- refer to data sheet.
Table 18: INTPENDING0 bit fields
Reserved
Name Bit(s)
[31:0]
Access
(U/S)
RO/RO
Reset Comment
0x0 System defined - refer to data sheet.
Table 19: INTPENDING1 bit fields
12.3.2 Interrupt mask register (INTMASK)
The
INTMASK
register is a 64 bit register whose contents are AND-ed with the
INTPENDING
register. It is used to enable and disable external interrupts.
Name:
Reset Value:
INTMASK
0
0[31:0],
INTMASK
1[63:32]
Interrupts are enabled by setting, and disabled by clearing, the corresponding bits the
INTMASK
register.
Bits 31:16 are fixed set, so that the corresponding interrupt lines are permanently enabled.
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ST220 Core and Instruction Set Architecture Manual
82 Interrupt registers
INTMASKCLR and INTMASKSET
Two 64-bit address locations in the interrupt controller memory space support bit-wise access to the INTMASK register. A store to these locations causes the corresponding bits in the INTMASK register to be cleared or set.
Name:
INTMASKCLR
0[31:0],
INTMASKCLR
1[63:32],
INTMASKSET
0[31:0],
INTMASKSET
1[63:32]
0 Reset Value:
Using this method of accessing the INTMASK register avoids any problems caused by interrupts occuring during a Read-Modify-Write sequence and therefore avoids the need to have interrupts disabled while modifying these registers.
12.3.3 Interrupt test register (INTTEST)
The INT TEST register is a 64-bit register whose contents are OR-ed with external interrupts. It provides a mechanism for simulating interrupts to the processor.
Name:
Reset Value:
INTTEST
0
0[31:0], INTTEST 1[63:32]
Setting bits in the INTTEST register causes the corresponding bits in the INTPENDING register to be set.
INTCLR and INTSET
Two 64-bit address locations in the interrupt controller memory space support bit-wise access to the INTTEST register. A store to these locations causes the corresponding bits in the INTTEST register to be cleared or set.
Name:
Reset Value:
INTCLR
0
0[31:0], INTCLR 1[63:32], INTSET 0[31:0], INTSET 1[63:32]
Using this method of accessing the INTTEST register avoids the overhead in a direct write of having to read, save and restore unaccessed bits.
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ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
Programming 83
12.4 Programming
12.4.1 Enabling/disabling interrupts
Interrupts are enabled and disabled by setting and clearing the appropriate bits in the INTMASK register.
In the ST220 interrupts 31:16 are non-maskable and permanently enabled.
INTMASK register bits 31:16 are tied to high.
The INTMASK register can written to directly as two 32-bit words, or bit-wise using the mask clear and mask set locations, see
INTMASKCLR and INTMASKSET on page 82
.
12.4.2 Test register
Interrupts can be simulated for test purposes by setting bits in the
INTTEST
register.
This register is directly OR-red with the external interrupt signals into the
INT PENDING
register.
The
INTTEST
register can written to directly as two 32-bit words, or bit-wise using the test clear and test set locations, see
INTCLR and INTSET on page 82
.
Note: INTTEST register bits are not reset when the interrupt is taken and must be explicitly cleared by the program.
12.4.3 Interrupt priority
The interrupt handling code is responsible for prioritization of interrupts. No hardware support is provided.
12.4.4 Timer interrupts
The first three bits in the
INTTEST
register are also used in conjunction with the timer. When a timer interrupt occurs the corrisponding bit in the
INTTEST
register is set (timer 0 sets bit 0, timer 1 sets bit 1 and timer 2 sets bit 2). This prevents timer interrupts from being lost. When a timer interrupt is serviced the software should clear the correct bit in the
INTTEST
register.
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STMicroelectronics
ST220 Core and Instruction Set Architecture Manual
84 Programming
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
