Debugging support
13.1 Overview
Debugging support on the ST220 is provided by 4 main components.
•
Core
The ST220 core includes a non maskable debug interrupt, and additional state to support the taking of debug interrupts. The core also contains hardware breakpoint support.
•
DSU
Shared DSU registers and state machine which generates debug interrupts and send responses over debug interface.
•
Debug ROM
Default program run in response to debug interrupt. This program uses the DSU registers to send higher level protocols over the debug interface. This program implements the DSU_PEEK , DSU_POKE , DSU_CALL_OR_RETURN and DSU_FLUSH operations.
•
Host debug interface
The hardware link, using the TAPlink protocol, to any connected host target interface (HTI). Supports peek , poke , peeked and event messages.
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13.2 Core
13.2.1 Debug interrupts
The ST220 can accept and service interrupts from the DSU. Debug interrupts are higher priority than normal interrupts, cannot be masked, and place the ST220 in a debug state.
Debug interrupt handling
A debug interrupt is handled differently to other external interrupts.
Taking a debug interrupt can be summarized as:
NEXT_PC
←
SAVED_SAVED_PSW
←
SAVED_SAVED_PC
←
SAVED_PSW
←
SAVED_PC
←
PSW[USER_MODE]
←
PSW[INT_ENABLE]
←
PSW[IBREAK_ENABLE]
←
PSW[DBREAK_ENABLE]
←
PSW[IPU_ENABLE]
←
PSW[DPU_ENABLE]
←
PSW[DEBUG_MODE]
←
Exiting debug mode
Debug mode is exited, and normal mode re-entered, when the DEBUG _ MODE bit is cleared in the PSW . The only supported method for writing the PSW is via the rfi operation (see
Section 3.3.4: Supported method for changing the PSW ).
Note: Although clearing the DEBUG _ MODE bit causes the ST220 to exit debug mode, attempting to set the DEBUG _ MODE bit when it is not already set does not cause the core to enter debug mode and the DEBUG _ MODE bit remains clear. Debug mode can only be entered by taking a debug interrupt from the DSU.
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13.2.2 Hardware breakpoint support
Breakpoints are supported by:
•
enable bits in the
PSW
,
•
address registers to define memory ranges,
•
control register to specify comparison operations.
The safe way to use the breakpoint registers is to disable the breakpoints and then set the control and address registers before enabling the breakpoints again. This will prevent spurious breaks due to inconsistent control and address registers.
Enable bits
Breakpoints are enabled though the PSW , one bit for instruction breakpoints and another data breakpoints (see
Section 3.3: Program status word (PSW)
).
Address registers
Two 32-bit registers are used to define addresses for the instruction and data breakpoints (
IBREAK
_
LOWER
,
DBREAK
_
LOWER
,
IBREAK
_
UPPER
,
DBREAK
_
UPPER
).
These registers are all reset to the value 0.
Control registers
Bits [3:0] in this register determine the comparison operations performed on the breakpoint addresses. If the comparison is true then a breakpoint exception (
IBREAK or
DBREAK
) is signaled.
For instruction breakpoints the bundle address is used for comparison. For data breakpoints, the data effective address is used for comparison. The following comparison operations are defined.
0
1
2
3
Bit Break point comparison
Address <= Upper && Address >= Lower
Address > Upper || Address < Lower
Address == Upper || Address == Lower
Address & Upper == Lower
Table 20: Breakpoint register comparisons
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13.3 Debug support unit
The DSU allows both software and hardware to be debugged from a host by giving direct access to the ST220 core.
13.3.1 Architecture
The architecture of the DSU is shown in Figure 9
.
Debug Support Unit
WRITEENABLE
Host
Host debug interface
Control block
Shared register bank
Debug
ROM
DEBUG_INTERRUPT
DEBUG_INTERRUPT_TAKEN
STBus port
ST220 core
Figure 9: DSU architecture
The DSU is controlled by a host via the debug interface. The DSU control block interacts directly with the ST220 core via the DEBUG _ INTERRUPT and
DEBUG _ INTERRUPT _ TAKEN signals, and the shared register block.
The shared registers can also be accessed via the STBus port.
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13.3.2 Shared register bank
The 32 shared registers consists of 3 reserved registers ( DSR 0-2) and 29 general purpose registers ( DSR 3-31). These are used to implement communication between the host and the target by the debug handler.
The shared register bank is 32-bits wide and only supports 32-bit STBus operations.
DSU shared registers are listed below.
Register
Name
DSR 0
DSR
DSR
1
2
Description
DSU version register
DSU status register
DSU output register
DSR 3-31
R
RW
Bits 0-5 R, others RW
RW
RW
Comments
Contains ID numbers for DSU, core, and chip version.
Contains DSU control and status bits.
Supports message transfer from target to HTI.
General purpose registers.
The STBus addresses of the DSU registers are detailed in
Chapter 11: Peripheral addresses on page 75
.
Shared access conventions
The DSU shared registers are accesable independently from both the DSU and the
STBus. The ST220 and DSU have no hardware support for synchronizing writes, so software conventions are used to prevent write conflicts.
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13.3.3 DSU control registers
Name
PRODUCT _ ID
CORE _ VERSION
DSU _ VERSION
Bit(s)
[15:0]
Access
(U/S)
RO
[23:16] RO
[31:24] RO
Reset Comment
0x0002 Chip ID.
0x02
0x02
ST220 core version number.
DSU design version number.
Table 21: DSR0 bit fields
DSU status register (DSR1)
The DSU status register contains the DSU status and control bits.
Name
HW _ FLAGS
SW _ FLAGS
DSU version register (DSR0)
The DSU version register is a read-only ID register:
DEBUG _ INTERRUPT _ TAKEN
SUPERVISOR _ WRITE _ ENABLE
USER _ WRITE _ ENABLE
Reserved
OUTPUT _ PENDING
Bit(s)
Access
(U/S)
RO
Reset Comment
0
1
2
[4:3]
5
RW
RW
RO
RO
0x0
0x1
0x0
0x0
0x0
[15:6] RW
[31:16] RW
0x0
0x0
Table 22: DSR1 bit fields
Value of DEBUG_INTERRUPT_TAKEN signal, active high.
STBus writes enabled if the core is in supervisor mode (regardless of debug mode).
STBus writes enabled if the core is in user mode (regardless of debug mode).
Reserved
DSR2 contains a byte to be sent to the
HTI which has not yet been sent.
Reserved for future hardware purposes.
Reserved for future software use.
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DSU output register (DSR2)
The lower 8 bits of the DSU output register are sent to the TAPlink (to any attached host) on being written.
Name
DATA
Reserved
Bit(s)
[7:0]
[31:8]
Access
(U/S)
RW
RO
Reset
0x0
0x0
Table 23: DSR2 bit fields
Comment
Output data.
Always zero.
If OUTPUT _ PENDING is non-zero then the byte most recently written has not yet been sent to the HTI and additional writes to the DSR 2 will not affect the byte being sent even if they change the contents of the register.
Messages sent via the DSR 2 may be delayed if the DSU is busy.
13.4 Debug ROM
The 1024-byte debug ROM is an ST220 peripheral. This contains the debug initialization loop and the default debug handler.
13.4.1 Debug initialization loop
On reset the ST220 starts executing at the beginning of the boot ROM. However, if the
DEBUG
_
ENABLE
signal is asserted execution starts at the debug initialization loop (this is the first word of the debug ROM). This word contains a single syllable bundle which loops back to the same location, allowing the DSU to intervene and configure the core before it executes any code.
Note: Where the
DEBUG
_
ENABLE
signal cannot be asserted, the boot ROM should start with a tight loop, or perhaps just a delay loop, to allow time for the DSU to interrupt the processor before it takes any action.
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13.4.2 Default debug handler
The default debug handler program starts at the second word of the debug ROM. It supports simple host-target debugging and the ability to install a more complex debug handler. The STBus address of the ROM is given in
Chapter 11: Peripheral addresses on page 75
.
Operation
On taking a debug interrupt, the default debug handler is executed. This first tests if a user handler is installed,
DSR
3 non zero, and if so branches to this address.
Otherwise the handler waits in the command loop.
Command loop
The command loop reads and processes commands from a host, delivered via the
TAPlink, to the DSU shared registers. Usage of the designated registers is shown in
Table 24
.
Register name
DSU _ COMMAND
DSU _ ARG 1,2,3
DSU _ RESPONSE
Host use
Set with command
Set with arguments for command, before setting DSU _ COMMAND
Zeroed after being read
Target use
Zeroed when command accepted
Set with response arguments before setting DSU _ RESPONSE
Set to indicate outcome of a command
Table 24: Command register usage
When the command is complete, the default debug handler stores the results in the argument registers and sets a success code in the response register.
Default handler commands
DSU_PEEK (DSU_COMMAND =4)
Reads the 32-bit memory location addressed by
DSU
_
ARG
1 and returns the data in
DSU
_
ARG
1. The address must be word aligned. If the operation is successful
DSU
_
RESPONSE
is set to
DSU
_
PEEKED
(1) and a
TAPLINK
_
EVENT
_
DEFAULT
(reason=7) event is sent to the HTI.
Note: Any code greater than 4 is interpreted as a
DSU
_
PEEK
command.
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DSU_POKE (DSU_COMMAND = 3)
Writes the 32-bit data word in DSU _ ARG 2 to the memory location addressed by
DSU _ ARG 1. The address must be word aligned. If the operation is successful
DSU _ RESPONSE is set to DSU _ POKED (2) and a TAPLINK _ EVENT _ DEFAULT
(reason=7) event is sent to the HTI.
DSU_CALL_OR_RETURN (DSU_COMMAND = 1)
Calls the routine addressed by
DSU
_
ARG
1. If the called routine does not return this is effectively a branch. If
DSU
_
ARG
1 is zero this is a return call. Just before calling the user routine, or returning from a call,
DSU
_
RESPONSE
is set to
DSU
_
RETURNING
(3) and a
TAPLINK
_
EVENT
_
DEFAULT
(reason=7) event is sent to the host.
DSU_FLUSH (DSU_COMMAND = 2)
Flushes the address range delimited by
DSU
_
ARG
1 and
DSU
_
ARG
2 from data and instruction caches.
If a command was successful DSU _ RESPONSE is set to
DSU _ FLUSHED
(4) and a
TAPLINK _ EVENT _ DEFAULT
(reason=7) event is sent to the host.
Trap handler
If a trap occurs while a command is being processed, for example, an invalid address supplied on a peek or poke :
•
the operation in progress is completed by loading the
PC
of the offending bundle, the exception cause, and the exception address into
DSR
_
ARG
1,
DSR
_
ARG
2 and
DSR
_
ARG
3 respectively.
•
DSU
_
RESPONSE
is set to
DSU _ GOT _ EXCEPTION
(Code=5) and a
TAPLINK _ EVENT _ DEFAULT
(Reason=7) event is sent to the HTI.
•
As for all exceptions, the
SAVED
_
PC
and
SAVED
_
PSW
registers will have been updated when the exception occured.
Context restore
Prior to exit the default handler restores any state it has altered.
Note: The context may have been additionally altered by commands issued.
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Default handler register usage
The following DSU registers are defined and used by the default debug handler program:
DSR 14
DSR 15
DSR 16
DSR 17
DSR 18
DSR 19
DSR 20
DSR 21
DSR 22
DSR 23
DSR 24
DSR 25
DSR 26
DSR number
DSR 3
DSR 4-8 a
DSR 9 a
DSR 10 a
DSR
DSR
DSR
11
12
13 a
Designation Comment
DSR _ USER _ DEBUG _ HANDLER Control switches to this address if content is non-zero.
DSU _ ARG 4-8 Not used in current debug handler.
DSU _ ARG 3 Command argument 3.
DSU _ ARG 2 Command argument 2. Used by DSU _ POKE and
DSU _ FLUSH .
Command argument 1. Used by all DSU commands.
DSU _ ARG 1
DSU _ COMMAND
DSU _ RESPONSE
Context saving
Context saving
Context saving
Context saving
Context saving
Context saving
Context saving
Context saving
Context saving
Context saving
Context saving
Context saving
Context saving
Command register. Written by HTI, cleared by target when command accepted.
Response register. Set by target to a completion code, cleared by HTI before issuing next command.
Saves SCR 4_ REG b
Saves SCR 1_ REG b
Saves SCR 2_ REG b
Saves SCR 3_ REG b
Saves the branch bits
Saves LINK _ REG b
Saves HANDLER _ PC
Saves SAVED _ SAVED _ PSW
Saves SAVED _ SAVED _ PC
Saves SAVED _ PSW
Saves SAVED _ PC
Saves EXCAUSE
Saves EXADDRESS
Table 25: DSU command registers
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DSR number
Designation Comment
DSR 27-30 Unused
DSR 31 Context saving
Unused
Saves DSR1
Table 25: DSU command registers a. Argument registers are placed before the command register in the address space so that a command and its arguments can be loaded with a single poke operation.
b. As defined by the ABI (see ST200 Programming Manual )
13.5 Host debug interface
Exchange of information with the host is via a host target interface (HTI) adaptor.
The DSU connects to the HTI via a JTAG interface, and the HTI connects to the host via Ethernet, USB, serial port or parallel port. This is illustrated in
Figure 10 .
All host-target communication is done with peek , poke , peeked and event messages sent between the host and the DSU.
Host
HTI adapter
JTAG
DSU ST220 core
Figure 10: DSU overview
13.5.1 Message format
Commands are sent to the DSU in Taplink message format consisting of a bidirectional byte stream which is interpreted by the DSU as a stream of commands.
Figure 11 shows the DSU commands in Taplink message format.
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HTI Initiated Messages
Poke DSR Address
Peek DSR Address
HTI or Target Initiated Messages
Event
First Data Word Second...
Response Messages
Peeked First Data Word Second Data Word Third...
Header
Byte
2nd
Byte
Figure 11: DSU commands
Note: Messages are transmitted little endian, independent of the endianness of the ST220 core.
Header bytes
Header bytes contain command-specific information such as the range of registers to be accessed. Header byte formats for the 4 DSU commands are illustrated in
Figure 12 .
Poke
Peek
Peeked
Event
7 6 5 4 word count
3 2
7 6 5 4 word count
3 2
7
7
6
6 channel
5 4 word count
3
5
2
4 3 reason
2
Header Byte
1
0
1
0
1
1
1
1
0
1
0
0
0
0
0
1
Figure 12: Header bytes
Subsequent Bytes
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Peek and poke operation
Peek and poke commands read and write the shared DSU registers. Each command uses a 6-bit count and one byte as a register address. The byte address references the first register in the range, and the count indicates how many registers are accessed. Counts greater than 32 are interpreted as 32.
Register addresses wrap, so a peek or poke with an address of 30 and a count of 4 will access registers
DSR
30,
DSR
31,
DSR
0 and
DSR
1, in that order.
The result of a peek command is returned to the host using a peeked message.
Note: Peeked messages are not supported from the host to the target and their behavior is undefined.
13.5.2 Operation
Generating debug interrupts
In order to interrupt the core, the host sends an event with reason=1. The event is decoded by the DSU and a
DEBUG _ INTERRUPT
signal is sent to the ST220. When the
ST220 takes the interrupt (as described in
Debug interrupt handling on page 86 )
the
DEBUG _ INTERRUPT _ TAKEN
signal goes high.
The functionality available to the host is then dependent on the debug handler program running. The default handler uses designated shared registers to provides
the higher level operations detailed in Default handler commands on page 92 .
Core initiated events
The core can also request service from the host by sending it an event message.
This is done by writing the event to the
DSR
2 (the output register). The channel and reason fields of the event message are not examined by the hardware and can be used as desired by the software.
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