®
Cluster
The ST220 cluster consists of the functional units and the two register files; the branch registers and general purpose registers (for register files, refer to
Chapter 3:
Architectural state on page 25 ). The cluster is the core of the processor but does not
include the instruction fetch mechanism, caches or control registers.
This chapter describes the functional units of the ST220 cluster including 4 integer
units, 2 multiply units, a load store unit and a branch unit (refer to Figure 2
).
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ST220 Core and Instruction Set Architecture Manual
20 Integer units
Mul Mul
I-Side
Memory
Subsystem
128 bit wide
Word
Instruction
Buffer
Register
File
(64 registers
8 read
4 write)
Load
Store
Unit
(LSU)
D-Side
Memory
Subsystem
Control
Registers
I-Side
Memory
Subsystem
PC and Branch
Unit
Branch
Register File
IU IU IU IU
Exception
Control
Debug
Support Unit
Figure 2: ST220 cluster
The ST220 has four identical integer units. Each integer unit is capable of executing one operation per cycle. The results of the integer units can be used as operands of the next bundle. This is equivalent to a pipeline depth of one cycle.
Each operation can take up to three operands in the form of two 32-bit values and a single conditional bit. The IU then executes the appropriate operation and produces up to two results in the form of a 32-bit value and a 1-bit conditional value. The
integer operations supported are detailed in the Chapter 17: Instruction set on page 135 .
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Multiply units 21
The ST220 has two identical multiply units. Each multiply unit is pipelined with a depth of three cycles, executing an operation every cycle.
Each multiply units takes two 32-bit operands and produces a single 32-bit result.
The multiply operations supported are detailed in the
Chapter 17: Instruction set on page 135 .
2.3 Load/store unit (LSU)
The ST220 has a single load store unit. The load store unit is pipelined with a depth of three cycles, executing an operation every cycle.
The load store can take up to three 32-bit operands and may produce a single 32-bit result depending on the operation. The load store operations supported are detailed
in the Chapter 17: Instruction set on page 135 .
Memory access protection is implemented by the DPU (data protection unit), this is part of the memory sub-system. The DPU also controls the cache behavior of data accesses,
Chapter 6: Memory access protection units on page 39
.
Uncached accesses or accesses which miss the data cache cause the load store unit to stall the pipeline to ensure correct operation.
2.3.1 Memory access
The ST220 addresses the external memory system via a single address space.
Peripheral devices and control registers are also mapped into the address space.
All cacheable memory transactions are made via the data cache. The data cache then decides if it needs to go to external memory to satisfy the request.
Note: Cacheable memory transactions that miss are written to the write buffer not the data cache.
Uncached accesses are performed directly on the memory system (refer to
Chapter 7 :
Section 7.3.3: Uncached load and stores on page 51
).
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22 Load/store unit (LSU)
2.3.2 Addressing modes
The ST220 supports one addressing mode – the effective address is an immediate
(constant) plus a register.
2.3.3 Alignment
1 All load and store instructions work on data stored on the "natural alignment" of the data type; that is, words on word boundaries, half-word on half word boundaries.
2 Load and store operations with misaligned addresses raise an exception which makes possible the implementation of misaligned loads by trap handlers.
3 For a byte or half-word load , the data from memory is loaded into the least significant part of a register and is either sign-extended or zero extended according to the instruction defintion.
4 For a byte or half-word store , the data stored from the least significant part of a register.
2.3.4 Control registers
The LSU maps a part of the address space that is devoted to control registers (see the Control Registers chapter for details). The LSU control register block intercepts loads and stores to this area of memory so that it can process the operation. No access to the data cache is made for control register operations. Transactions are made across the 32-bit control register bus to those control registers that live outside the LSU.
2.3.5 Cache purging
Cache purging (flush and invalidate) operations are provided on the ST220.
They allow for purging lines and sets from the data cache, and invalidating the entire instruction cache.
2.3.6 Dismissible loads
Dismissible loads are used to support software load speculation. This allows the compiler to schedule a load in advance of a condition that predicates its use.
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Load/store unit (LSU) 23
Dismissible loads are required to return the same value as a normal load if such an operation can be executed without causing an exception. Otherwise dismissible loads return zero.
In the event that misaligned accesses are supported through a software trap handler, the ST220 may be configured to trap non-aligned dismissible loads , see the
Chapter 5: Traps: exceptions and interrupts on page 31
. The data protection unit can be configured to return zero for dismissible loads in cases where they can be executed without exception; this is to support peripherals which have destructive read behavior.
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ST220 Core and Instruction Set Architecture Manual
24 Load/store unit (LSU)
STMicroelectronics
ST220 Core and Instruction Set Architecture Manual ADCS 7395369G
