Illegal opcode reset. STMicroelectronics ST7LITEUS5, 8-bit MCU

ST7LITEUS2, ST7LITEUS5 Instruction set

Table 41.

ST7 instruction set (continued)

Shift and rotates

Unconditional jump or call

Conditional branch

Interruption management

Condition code flag modification

SLL

JRA

SRL

JRT

SRA RLC RRC SWAP SLA

JRF JP CALL CALLR NOP RET

JRxx

TRAP WFI HALT IRET

SIM RIM SCF RCF

Using a prebyte

The instructions are described with 1 to 4 bytes.

In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes modify the meaning of the instruction they precede.

The whole instruction becomes:

PC-2 End of previous instruction

PC-1 Prebyte

PC Opcode

PC+1 Additional word (0 to 2) according to the number of bytes required to compute the effective address

These prebytes enable instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are:

PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent addressing mode by a Y one.

PIX 92 Replace an instruction using direct, direct bit or direct relative addressing mode to an instruction using the corresponding indirect addressing mode.

It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode.

PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one.

In order to provide enhanced robustness to the device against unexpected behavior, a system of illegal opcode detection is implemented. If a code to be executed does not correspond to any opcode or prebyte value, a reset is generated. This, combined with the watchdog, allows the detection and recovery from an unexpected fault or interference.

A valid prebyte associated with a valid opcode forming an unauthorized combination does not generate a reset.

Table 42.

Obsolete Product(s) - Obsolete Product(s)

Mnemo Description Function/example Dst Src H I N Z C

ADC

ADD

AND

BCP

Add with carry

Addition

Logical and

Bit compare A, Memory

A = A + M + C

A = A + M

A = A . M tst (A . M)

A

A

A

A

M

M

M

M

H

H

-

-

-

-

-

-

N

N

N

N

Z

Z

Z

Z

C

C

-

-

89/136

Instruction set

Table 42.

Illegal opcode detection (continued)

Mnemo Description Function/example

CP

CPL

DEC

HALT

IRET

INC

JP

JRA

BRES

BSET

BTJF

Bit Reset

Bit Set

Jump if bit is false (0)

BTJT

CALL

Jump if bit is true (1)

Call subroutine

CALLR Call subroutine relative

CLR Clear

Arithmetic compare

One Complement

Decrement

Halt

Interrupt routine return

Increment

Absolute jump

Jump relative always

JRT

JRF

JRIH

JRIL

JRH

JRNH

Jump relative

Never jump

Jump if ext. interrupt = 1

Jump if ext. interrupt = 0

Jump if H = 1

Jump if H = 0

JRM

JRNM

JRMI

Jump if I = 1

Jump if I = 0

Jump if N = 1 (minus)

JRPL

JREQ

Jump if N = 0 (plus)

Jump if Z = 1 (equal)

JRNE Jump if Z = 0 (not equal)

JRNC

Jump if C = 1

Jump if C = 0 bres Byte, #3 bset Byte, #3 btjf Byte, #3, Jmp1 btjt Byte, #3, Jmp1 tst(Reg - M)

A = FFH-A dec Y

Pop CC, A, X, PC inc X jp [TBL.w] jrf *

H = 1 ?

H = 0 ?

I = 1 ?

I = 0 ?

N = 1 ?

N = 0 ?

Z = 1 ?

Z = 0 ?

C = 1 ?

C = 0 ?

Dst

-

-

-

-

-

-

-

-

-

-

-

-

-

reg reg, M reg, M

-

reg, M

-

-

M

M

M

M

-

reg, M

Src

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

M

-

-

-

-

-

-

-

-

-

-

-

-

JRUGE

JRUGT

JRULE

LD

MUL

Jump if C = 0

Jump if (C + Z = 0)

Jump if (C + Z = 1)

Load

Multiply

ST7LITEUS2, ST7LITEUS5

N

-

-

-

-

-

-

-

-

-

-

-

-

-

-

N

-

N

N

N

N

-

-

-

0

-

-

-

-

-

I

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

0

-

-

I

-

-

-

-

-

-

-

-

-

-

H

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

H

-

-

-

-

-

-

-

-

-

-

C

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

C

1

C

-

-

-

-

-

C

-

-

-

C

Z

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Z

-

Z

Z

Z

Z

-

-

-

1

-

-

-

-

-

Jmp if unsigned

≥

Unsigned >

Unsigned

≤ dst

≤ src

X,A = X * A

-

-

-

-

-

reg, M M, reg

A, X, Y X, Y, A

-

0

-

-

-

-

-

-

-

-

N

-

-

-

-

Z

-

-

-

-

-

0

-

-

-

90/136

ST7LITEUS2, ST7LITEUS5

Table 42.

Illegal opcode detection (continued)

Mnemo

NEG

NOP

OR

POP

SLA

SLL

SRL

SRA

SUB

SWAP

TNZ

TRAP

WFI

XOR

PUSH

RCF

RET

RIM

RLC

RRC

RSP

SBC

SCF

SIM

Description

Negate (2's compl)

No operation

OR operation

Pop from the stack

Push onto the stack

Reset carry flag

Subroutine return

Enable Interrupts

Rotate left true C

Rotate right true C

Reset Stack Pointer

Subtract with carry

Set carry flag

Disable interrupts

Shift left arithmetic

Shift left logic

Shift right logic

Shift right arithmetic

Subtraction

SWAP nibbles

Test for Neg & Zero

S/W trap

Wait for interrupt

Exclusive OR

Function/example Dst neg $10

A = A + M pop reg pop CC push Y

C = 0

I = 0

C

≤

Dst

≤

C

C

≥

Dst

≥

C

S = Max allowed

-

reg, M reg, M

-

A = A - M - C

C = 1

A

-

I = 1

C

≤

Dst

≤

0

C

≤

Dst

≤

0

0

≥

Dst

≥

C

Dst7

≥

Dst

≥

C

reg, M reg, M reg, M reg, M

A = A - M A

Dst[7..4]

≤ ≥

Dst[3..0] reg, M tnz lbl1 -

S/W interrupt -

A = A XOR M

-

A reg, M

-

A reg

CC

M

-

Src

-

-

-

-

-

M

-

-

-

-

M

M

M reg, CC

-

-

M

-

-

-

-

M

-

-

-

H

-

-

-

-

-

-

-

-

-

-

-

H

-

-

-

-

-

-

-

-

-

-

-

-

-

Instruction set

I

-

-

-

0

-

-

-

1

-

-

-

I

-

-

-

-

-

-

-

1

0

-

-

-

-

-

N

N

N

N

-

-

-

N

-

-

-

-

-

N

N

-

N

N

N

N

N

N

N

0

C

C

C

-

-

-

C

1

-

-

0

-

C

C

-

-

C

C

-

-

-

-

-

C

C

C

Z

Z

Z

-

-

-

Z

-

-

-

-

-

Z

Z

-

Z

Z

Z

Z

Z

-

-

Z

Z

Z

Z

Obsolete Product(s) - Obsolete Product(s)

91/136