On-chip peripherals ST7LITEUS2, ST7LITEUS5
10.2.5 Interrupts
Table 28.
Interrupt events
Interrupt event
Overflow event
CMP event
(1)
Event flag
OVF
CMPFx
Enable control bit
OVFIE
CMPIE
Exit from
Wait
Yes
Yes
Exit from
Halt
No
No
Exit from
Active-halt
Yes
(2)
No
1.
The interrupt events are connected to separate interrupt vectors (see Interrupts chapter).
They generate an interrupt if the enable bit is set in the ATCSR register and the interrupt mask in the CC register is reset (RIM instruction).
2.
Only if CK0=1 and CK1=0
Timer control status register (ATCSR)
Reset value: 0000 0000 (00h)
7
0 0 0 CK1
Read/write
CK0 OVF OVFIE
0
CMPIE
Bits 7:5 Reserved, must be kept cleared.
Bits 4:3 CK[1:0] Counter Clock Selection.
These bits are set and cleared by software and cleared by hardware after a reset.
They select the clock frequency of the counter (see Table 29: Counter clock selection
).
Bit 2 OVF Overflow flag.
This bit is set by hardware and cleared by software by reading the ATCSR register.
It indicates the transition of the counter from FFFh to ATR value.
0: No counter overflow occurred
1: Counter overflow occurred
When set, the OVF bit stays high for 1 f
COUNTER
cycle (up to 1ms depending on the clock selection) after it has been cleared by software.
Bit 1 OVFIE Overflow interrupt enable.
This bit is read/write by software and cleared by hardware after a reset.
0: OVF interrupt disabled Obsolete Product(s) - Obsolete Product(s)
Bit 0 CMPIE Compare interrupt enable .
Obsolete Product(s) - Obsolete Product(s) mask the interrupt generation when CMPF bit is set.
0: CMPF interrupt disabled
1: CMPF interrupt enabled
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ST7LITEUS2, ST7LITEUS5 On-chip peripherals
Table 29.
Counter clock selection
Counter clock selection
OFF f
LTIMER
(1 ms timebase @ 8 MHz) f
CPU
Reserved
Counter register high (CNTRH)
Reset value: 0000 0000 (00h)
15
0 0 0 0 CN11
CK1
0
0
1
1
CK0
0
1
0
1
CN10 CN9
Counter register low (CNTRL)
This 12-bit register is read by software and cleared by hardware after a reset. The counter is incremented continuously as soon as a counter clock is selected. To obtain the 12-bit value, software should read the counter value in two consecutive read operations. As there is no latch, it is recommended to read LSB first. In this case, CNTRH can be incremented between the two read operations and to have an accurate result when f timer
= f
CPU
, special care must be taken when
CNTRL values close to FFh are read.
When a counter overflow occurs, the counter restarts from the value specified in the ATR register.
Reset value: 0000 0000 (00h)
Read only
7
CN7 CN6 CN5 CN4 CN3 CN2 CN1
0
CN0
Read only
8
CN8
Bits 15:12 Reserved, must be kept cleared.
Bits 11:0 CNTR[11:0] Counter value .
Auto reload register (ATRH)
Reset value: 0000 0000 (00h)
Obsolete Product(s) - Obsolete Product(s)
0 0 0 0 ATR11 ATR10 ATR9 ATR8
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On-chip peripherals ST7LITEUS2, ST7LITEUS5
Auto reload register (ATRL)
This is a 12-bit register which is written by software. The ATR register value is automatically loaded into the upcounter when an overflow occurs. The register value is used to set the
PWM frequency.
Reset value: 0000 0000 (00h)
7
ATR7 ATR6 ATR5 ATR2 ATR1
0
ATR0 ATR4
Read/Write
ATR3
Bits 15:12 Reserved, must be kept cleared.
Bits 11:0 ATR[11:0] Auto-reload Register.
PWM0 duty cycle register high (DCR0H)
Reset value: 0000 0000 (00h)
15
0 0 0 0 DCR11
Read/Write
DCR10 DCR9
8
DCR8
PWM0 duty cycle register low (DCR0L)
This 12-bit value is written by software. The high register must be written first.
In PWM mode (OE0=1 in the PWMCR register) the DCR[11:0] bits define the duty cycle of the PWM0 output signal (see
Figure 34
). In Output Compare mode, (OE0=0 in the PWMCR register) they define the value to be compared with the 12-bit upcounter value.
Reset value: 0000 0000 (00h)
7
DCR7 DCR6 DCR5 DCR2 DCR1
0
DCR0 DCR4 DCR3
Read/Write
Bits 15:12 Reserved, must be kept cleared.
Bits 11:0 DCR[11:0] PWMx duty cycle value
Obsolete Product(s) - Obsolete Product(s)
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ST7LITEUS2, ST7LITEUS5 On-chip peripherals
PWM0 control/status register (PWM0CSR)
Reset value: 0000 0000 (00h)
7
0 0 0 0 0
Read/Write
0 OP0
0
CMPF0
Bit 7:2 Reserved, must be kept cleared.
Bit 1 OP0 PWM0 output polarity.
This bit is read/write by software and cleared by hardware after a reset. This bit selects the polarity of the PWM0 signal.
0: The PWM0 signal is not inverted.
1: The PWM0 signal is inverted.
Bit 0 CMPF0 PWM0 Compare Flag.
This bit is set by hardware and cleared by software by reading the PWM0CSR register. It indicates that the upcounter value matches the DCR0 register value.
0: Upcounter value does not match DCR value.
1: Upcounter value matches DCR value.
PWM output control register (PWMCR)
Reset value: 0000 0000 (00h)
7
0 0 0 0 0 0 0
0
OE0
Read/Write
Bits 7:1 Reserved, must be kept cleared.
Bit 0 OE0 PWM0 Output enable .
This bit is set and cleared by software.
0: PWM0 output Alternate Function disabled (I/O pin free for general purpose I/O)
1: PWM0 output enabled
Table 30.
Register map and reset values
Address
(Hex.)
Register label
7 6 5
ATCSR
Reset value
0 0 0
4
CK1
0
3 2 1 0
0F
10
Reset value
CNTRL
Reset value
ATRH
Reset value
0
CN7
0
0
0
CN6
0
0
0
CN5
0
0
0
CN4
0
0
CK0
0
CN11
0
CN3
0
ATR11
0
OVF
0
CN10
0
CN2
0
ATR10
0
OVFIE
0
CN9
0
CN1
0
ATR9
0
CMPIE
0
CN8
0
CN0
0
ATR8
0
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On-chip peripherals ST7LITEUS2, ST7LITEUS5
Table 30.
Register map and reset values (continued)
Address
(Hex.)
Register label
7 6 5 4 3
11
12
13
17
18
ATRL
Reset value
PWMCR
Reset value
PWM0CSR
Reset value
DCR0H
Reset value
DCR0L
Reset value
ATR7
0
0
0
0
DCR7
0
ATR6
0
0
0
0
DCR6
0
ATR5
0
0
0
0
DCR5
0
ATR4
0
0
0
0
DCR4
0
ATR3
0
0
0
2
ATR2
0
0
0
DCR11
0
DCR10
0
DCR3
0
DCR2
0
1 0
ATR1
0
0
OP
0
DCR9
0
DCR1
0
ATR0
0
OE0
0
CMPF0
0
DCR8
0
DCR0
0
Obsolete Product(s) - Obsolete Product(s)
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