ST7LITEUS2, ST7LITEUS5
5 Central processing unit
Central processing unit
5.1 Introduction
This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8bit data manipulation.
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63 basic instructions
Fast 8-bit by 8-bit multiply
17 main addressing modes
Two 8-bit index registers
16-bit stack pointer
Low power modes
Maskable hardware interrupts
Non-maskable software interrupt
The six CPU registers shown in Figure 7 are not present in the memory mapping and are
accessed by specific instructions.
The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data.
5.3.2 Index registers (X and Y)
In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The cross-assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the
Y register.)
The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack).
Obsolete Product(s) - Obsolete Product(s)
5.3.3 Program counter (PC) the LSB) and PCH (program counter high which is the MSB).
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