STM8S007C8 Memory and register map
Table 6 lists the boundary addresses for each memory size. The top of the stack is at the
RAM end address in each case.
Table 6. Flash, Data EEPROM and RAM boundary addresses
Memory area Size (byte) Start address End address
Flash program memory
RAM
64 K
6 K
0x00 8000
0x00 0000
0x01 7FFF
0x00 17FF
Data EEPROM 128 0x00 4000 0x00 407F
Address
0x00 5000
0x00 5001
0x00 5002
0x00 5003
0x00 5004
0x00 5005
0x00 5006
0x00 5007
0x00 5008
0x00 5009
0x00 500A
0x00 500B
0x00 500C
0x00 500D
0x00 500E
0x00 500F
0x00 5010
0x00 5011
0x00 5012
0x00 5013
Block
Table 7. I/O port hardware register map
Register label Register name
Port A
Port B
Port C
Port D
PA_ODR
PA_IDR
PA_DDR
PA_CR1
PA_CR2
PB_ODR
PB_IDR
PB_DDR
PB_CR1
PB_CR2
PC_ODR
PB_IDR
PC_DDR
PC_CR1
PC_CR2
PD_ODR
PD_IDR
PD_DDR
PD_CR1
PD_CR2
Port A data output latch register
Port A input pin value register
Port A data direction register
Port A control register 1
Port A control register 2
Port B data output latch register
Port B input pin value register
Port B data direction register
Port B control register 1
Port B control register 2
Port C data output latch register
Port C input pin value register
Port C data direction register
Port C control register 1
Port C control register 2
Port D data output latch register
Port D input pin value register
Port D data direction register
Port D control register 1
Port D control register 2
Reset status
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x02
0x00
DS8633 Rev 6
27/93
37
Memory and register map
Address
0x00 5014
0x00 5015
0x00 5016
0x00 5017
0x00 5018
0x00 5019
0x00 501A
0x00 501B
0x00 501C
0x00 501D
0x00 501E
0x00 501F
0x00 5020
0x00 5021
0x00 5022
0x00 5023
0x00 5024
0x00 5025
0x00 5026
0x00 5027
0x00 5028
0x00 5029
0x00 502A
0x00 502B
0x00 502C
Table 7. I/O port hardware register map (continued)
Block Register label Register name
Port E
Port F
Port G
Port H
Port I
PE_ODR
PE_IDR
PE_DDR
PE_CR1
PE_CR2
PF_ODR
PF_IDR
PF_DDR
PF_CR1
PF_CR2
PG_ODR
PG_IDR
PG_DDR
PG_CR1
PG_CR2
PH_ODR
PH_IDR
PH_DDR
PH_CR1
PH_CR2
PI_ODR
PI_IDR
PI_DDR
PI_CR1
PI_CR2
Port E data output latch register
Port E input pin value register
Port E data direction register
Port E control register 1
Port E control register 2
Port F data output latch register
Port F input pin value register
Port F data direction register
Port F control register 1
Port F control register 2
Port G data output latch register
Port G input pin value register
Port G data direction register
Port G control register 1
Port G control register 2
Port H data output latch register
Port H input pin value register
Port H data direction register
Port H control register 1
Port H control register 2
Port I data output latch register
Port I input pin value register
Port I data direction register
Port I control register 1
Port I control register 2
STM8S007C8
Reset status
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
28/93
DS8633 Rev 6
STM8S007C8
Address
0x00 5050 to
0x00 5059
0x00 505A
0x00 505B
0x00 505C
0x00 505D
0x00 505E
0x00 505F
0x00 5060 to
0x00 5061
0x00 5062
0x00 50C1
0x00 50C2
0x00 50C3
0x00 50C4
0x00 50C5
0x00 50C6
0x00 50C7
0x00 50C8
0x00 50C9
0x00 50CA
0x00 50CB
0x00 5063
0x00 5064
0x00 5065 to
0x00 509F
0x00 50A0
0x00 50A1
0x00 50A2 to
0x00 50B2
0x00 50B3
0x00 50B4 to
0x00 50BF
0x00 50C0
Memory and register map
Block
Flash
Flash
Flash
ITC
RST
CLK
CLK
Table 8. General hardware register map
Register label Register name
Reset status
FLASH_CR1
FLASH_CR2
FLASH_NCR2
FLASH _FPR
FLASH _NFPR
FLASH _IAPSR
Reserved area (10 byte)
Flash control register 1
Flash control register 2
Flash complementary control register 2
Flash protection register
Flash complementary protection register
Flash in-application programming status register
FLASH _PUKR
FLASH _DUKR
EXTI_CR1
EXTI_CR2
Reserved area (2 byte)
Flash Program memory unprotection register
Reserved area (1 byte)
Data EEPROM unprotection register
Reserved area (59 byte)
External interrupt control register 1
External interrupt control register 2
RST_SR
Reserved area (17 byte)
Reset status register
CLK_ICKR
CLK_ECKR
CLK_CMSR
CLK_SWR
CLK_SWCR
CLK_CKDIVR
CLK_PCKENR1
CLK_CSSR
CLK_CCOR
CLK_PCKENR2
Reserved area (12 byte)
Internal clock control register
External clock control register
Reserved area (1 byte)
Clock master status register
Clock master switch register
Clock switch control register
Clock divider register
Peripheral clock gating register 1
Clock security system register
Configurable clock control register
Peripheral clock gating register 2
Reserved area (1 byte)
0x00
0x00
0x00
0x00
0xXX
(1)
0x01
0x00
0xE1
0xE1
0xXX
0x18
0xFF
0x00
0x00
0xFF
0x00
0x00
0xFF
0x00
0xFF
0x00
DS8633 Rev 6
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37
Address
0x00 50CC
0x00 50CD
0x00 50CE to
0x00 50D0
0x00 50D1
0x00 50D2
0x00 50D3 to
0x00 50DF
0x00 50E0
0x00 50E1
0x00 50E2
0x00 50E3 to
0x00 50EF
0x00 50F0
0x00 50F1
0x00 50F2
0x00 50F3
0x00 50F4 to
0x00 50FF
0x00 5200
0x00 5201
0x00 5202
0x00 5203
0x00 5204
0x00 5205
0x00 5206
0x00 5207
0x00 5208 to
0x00 520F
0x00 5210
0x00 5211
0x00 5212
0x00 5213
0x00 5214
0x00 5215
Memory and register map STM8S007C8
Table 8. General hardware register map (continued)
Block
CLK
WWDG
IWDG
AWU
BEEP
SPI
I
2
C
Register label
CLK_HSITRIMR
CLK_SWIMCCR
Register name
HSI clock calibration trimming register
SWIM clock control register
Reset status
0x00
0bXXXX
XXX0
WWDG_CR
WWDG_WR
IWDG_KR
IWDG_PR
IWDG_RLR
AWU_CSR1
AWU_APR
AWU_TBR
BEEP_CSR
SPI_CR1
SPI_CR2
SPI_ICR
SPI_SR
SPI_DR
SPI_CRCPR
SPI_RXCRCR
SPI_TXCRCR
I2C_CR1
I2C_CR2
I2C_FREQR
I2C_OARL
I2C_OARH
Reserved area (3 byte)
WWDG control register
WWDR window register
Reserved area (13 byte)
IWDG key register
IWDG prescaler register
IWDG reload register
Reserved area (13 byte)
AWU control/status register 1
AWU asynchronous prescaler buffer register
AWU timebase selection register
BEEP control/status register
Reserved area (12 byte)
SPI control register 1
SPI control register 2
SPI interrupt control register
SPI status register
SPI data register
SPI CRC polynomial register
SPI Rx CRC register
SPI Tx CRC register
Reserved area (8 byte)
I 2 C control register 1
I
2
C control register 2
I
2
C frequency register
I
2
C own address register low
I
2
C own address register high
Reserved
0x7F
0x7F
0xXX
(2)
0x00
0xFF
0x00
0x3F
0x00
0x1F
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x02
0x00
0x07
0x00
0x00
30/93
DS8633 Rev 6
STM8S007C8
Address
0x00 5237
0x00 5238
0x00 5239
0x00 523A
0x00 523B to
0x00 523F
0x00 5240
0x00 5241
0x00 5242
0x00 5243
0x00 5244
0x00 5245
0x00 5216
0x00 5217
0x00 5218
0x00 5219
0x00 521A
0x00 521B
0x00 521C
0x00 521D
0x00 521E to
0x00 522F
0x00 5230
0x00 5231
0x00 5232
0x00 5233
0x00 5234
0x00 5235
0x00 5236
0x00 5246
0x00 5247
0x00 5248
0x00 5249
0x00 524A to
0x00 524F
Memory and register map
Table 8. General hardware register map (continued)
Block
I
2
C
UART1
UART3
Register label
I2C_DR
I2C_SR1
I2C_SR2
I2C_SR3
I2C_ITR
I2C_CCRL
I2C_CCRH
I2C_TRISER
UART3_CR6
Register name
I 2 C data register
I
2
C status register 1
I
2
C status register 2
I
2
C status register 3
I
2
C interrupt control register
I
2
C clock control register low
I 2 C clock control register high
I
2
C TRISE register
UART1_SR
UART1_DR
UART1_BRR1
UART1_BRR2
UART1_CR1
UART1_CR2
UART1_CR3
UART1_CR4
UART1_CR5
UART1_GTR
UART1_PSCR
Reserved area (18 byte)
UART1 status register
UART1 data register
UART1 baud rate register 1
UART1 baud rate register 2
UART1 control register 1
UART1 control register 2
UART1 control register 3
UART1 control register 4
UART1 control register 5
UART1 guard time register
UART1 prescaler register
Reserved area (5 bytes)
UART3_SR
UART3_DR
UART3_BRR1
UART3_BRR2
UART3_CR1
UART3_CR2
UART3_CR3
UART3_CR4
UART3 status register
UART3 data register
UART3 baud rate register 1
UART3 baud rate register 2
UART3 control register 1
UART3 control register 2
UART3 control register 3
UART3 control register 4
Reserved
UART3 control register 6
Reserved area (6 bytes)
0x00
0xC0
0xXX
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
C0h
0xXX
0x00
0x00
0x00
0x00
0x00
0x00
Reset status
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x02
DS8633 Rev 6
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37
Address
0x00 5261
0x00 5262
0x00 5263
0x00 5264
0x00 5265
0x00 5266
0x00 5267
0x00 5268
0x00 5269
0x00 526A
0x00 526B
0x00 526C
0x00 526D
0x00 526E
0x00 526F
0x00 5270 to
0x00 52FF
0x00 5250
0x00 5251
0x00 5252
0x00 5253
0x00 5254
0x00 5255
0x00 5256
0x00 5257
0x00 5258
0x00 5259
0x00 525A
0x00 525B
0x00 525C
0x00 525D
0x00 525E
0x00 525F
0x00 5260
Memory and register map
Table 8. General hardware register map (continued)
Block Register label Register name
TIM1
TIM1_PSCRL
TIM1_ARRH
TIM1_ARRL
TIM1_RCR
TIM1_CCR1H
TIM1_CCR1L
TIM1_CCR2H
TIM1_CCR2L
TIM1_CCR3H
TIM1_CCR3L
TIM1_CCR4H
TIM1_CCR4L
TIM1_BKR
TIM1_DTR
TIM1_OISR
TIM1_CR1
TIM1_CR2
TIM1_SMCR
TIM1_ETR
TIM1_IER
TIM1_SR1
TIM1_SR2
TIM1_EGR
TIM1_CCMR1
TIM1_CCMR2
TIM1_CCMR3
TIM1_CCMR4
TIM1_CCER1
TIM1_CCER2
TIM1_CNTRH
TIM1_CNTRL
TIM1_PSCRH
TIM1 control register 1
TIM1 control register 2
TIM1 slave mode control register
TIM1 external trigger register
TIM1 Interrupt enable register
TIM1 status register 1
TIM1 status register 2
TIM1 event generation register
TIM1 capture/compare mode register 1
TIM1 capture/compare mode register 2
TIM1 capture/compare mode register 3
TIM1 capture/compare mode register 4
TIM1 capture/compare enable register 1
TIM1 capture/compare enable register 2
TIM1 counter high
TIM1 counter low
TIM1 prescaler register high
TIM1 prescaler register low
TIM1 auto-reload register high
TIM1 auto-reload register low
TIM1 repetition counter register
TIM1 capture/compare register 1 high
TIM1 capture/compare register 1 low
TIM1 capture/compare register 2 high
TIM1 capture/compare register 2 low
TIM1 capture/compare register 3 high
TIM1 capture/compare register 3 low
TIM1 capture/compare register 4 high
TIM1 capture/compare register 4 low
TIM1 break register
TIM1 dead-time register
TIM1 output idle state register
Reserved area (147 byte)
STM8S007C8
Reset status
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
32/93
DS8633 Rev 6
STM8S007C8
Address
0x00 5311
0x00 5312
0x00 5313
0x00 5314
0x00 5315 to
0x00 531F
0x00 5320
0x00 5321
0x00 5322
0x00 5323
0x00 5324
0x00 5325
0x00 5300
0x00 5301
0x00 5302
0x00 5303
0x00 5304
0x00 5305
0x00 5306
0x00 5307
0x00 5308
0x00 5309
0x00 530A
0x00 530B
0x00 530C
0x00 530D
0x00 530E
0x00 530F
0x00 5310
0x00 5326
0x00 5327
0x00 5328
0x00 5329
0x00 532A
Memory and register map
Table 8. General hardware register map (continued)
Block Register label Register name
TIM2
TIM3
TIM2_CR1
TIM2_IER
TIM2_SR1
TIM2_SR2
TIM2_EGR
TIM2_CCMR1
TIM2_CCMR2
TIM2_CCMR3
TIM2_CCER1
TIM2_CCER2
TIM2_CNTRH
TIM2_CNTRL
TIM2_PSCR
TIM2_ARRH
TIM2_ARRL
TIM2_CCR1H
TIM2_CCR1L
TIM2_CCR2H
TIM2_CCR2L
TIM2_CCR3H
TIM2_CCR3L
TIM3_CR1
TIM3_IER
TIM3_SR1
TIM3_SR2
TIM3_EGR
TIM3_CCMR1
TIM3_CCMR2
TIM3_CCER1
TIM3_CNTRH
TIM3_CNTRL
TIM3_PSCR
TIM2 control register 1
TIM2 interrupt enable register
TIM2 status register 1
TIM2 status register 2
TIM2 event generation register
TIM2 capture/compare mode register 1
TIM2 capture/compare mode register 2
TIM2 capture/compare mode register 3
TIM2 capture/compare enable register 1
TIM2 capture/compare enable register 2
TIM2 counter high
TIM2 counter low
TIM2 prescaler register
TIM2 auto-reload register high
TIM2 auto-reload register low
TIM2 capture/compare register 1 high
TIM2 capture/compare register 1 low
TIM2 capture/compare reg. 2 high
TIM2 capture/compare register 2 low
TIM2 capture/compare register 3 high
TIM2 capture/compare register 3 low
Reserved area (11 byte)
TIM3 control register 1
TIM3 interrupt enable register
TIM3 status register 1
TIM3 status register 2
TIM3 event generation register
TIM3 capture/compare mode register 1
TIM3 capture/compare mode register 2
TIM3 capture/compare enable register 1
TIM3 counter high
TIM3 counter low
TIM3 prescaler register
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Reset status
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
DS8633 Rev 6
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37
Memory and register map
Table 8. General hardware register map (continued)
Block Register label Register name Address
0x00 532B
0x00 532C
0x00 532D
0x00 532E
0x00 532F
0x00 5330
0x00 5331 to
0x00 533F
0x00 5340
0x00 5341
0x00 5342
0x00 5343
0x00 5344
0x00 5345
0x00 5346
0x00 5347 to
0x00 53FF
TIM3
TIM4
0x00 5400
0x00 5401
0x00 5402
0x00 5403
0x00 5404
0x00 5405
0x00 5406
0x00 5407
ADC2
0x00 5408 to
0x00 57FF
1. Depends on the previous reset source.
2. Write only register.
TIM3_ARRH
TIM3_ARRL
TIM3_CCR1H
TIM3_CCR1L
TIM3_CCR2H
TIM3_CCR2L
TIM4_CR1
TIM4_IER
TIM4_SR
TIM4_EGR
TIM4_CNTR
TIM4_PSCR
TIM4_ARR
ADC _CSR
ADC_CR1
ADC_CR2
ADC_CR3
ADC_DRH
ADC_DRL
ADC_TDRH
ADC_TDRL
TIM3 auto-reload register high
TIM3 auto-reload register low
TIM3 capture/compare register 1 high
TIM3 capture/compare register 1 low
TIM3 capture/compare register 2 high
TIM3 capture/compare register 2 low
Reserved area (15 bytes)
TIM4 control register 1
TIM4 interrupt enable register
TIM4 status register
TIM4 event generation register
TIM4 counter
TIM4 prescaler register
TIM4 auto-reload register
Reserved area (185 byte)
ADC control/status register
ADC configuration register 1
ADC configuration register 2
ADC configuration register 3
ADC data register high
ADC data register low
ADC Schmitt trigger disable register high
ADC Schmitt trigger disable register low
Reserved area (1016 byte)
STM8S007C8
0x00
0x00
0x00
0x00
0xXX
0xXX
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
Reset status
0xFF
0xFF
0x00
0x00
0x00
0x00
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DS8633 Rev 6
STM8S007C8 Memory and register map
Table 9. CPU/SWIM/debug module/interrupt controller registers
Block Register Label Register Name Address
0x00 7F00
0x00 7F01
0x00 7F02
0x00 7F03
0x00 7F04
0x00 7F05
0x00 7F06
0x00 7F07
0x00 7F08
0x00 7F09
0x00 7F0A
0x00 7F0B to
0x00 7F5F
0x00 7F60
0x00 7F70
0x00 7F71
0x00 7F72
0x00 7F73
0x00 7F74
0x00 7F75
0x00 7F76
0x00 7F77
0x00 7F78 to
0x00 7F79
0x00 7F80
0x00 7F81 to
0x00 7F8F
CPU
(1)
CPU
ITC
SWIM
CFG_GCR
ITC_SPR1
ITC_SPR2
ITC_SPR3
ITC_SPR4
ITC_SPR5
ITC_SPR6
ITC_SPR7
ITC_SPR8
A
PCE
PCH
PCL
XH
XL
YH
YL
SPH
SPL
CCR
SWIM_CSR
Accumulator
Program counter extended
Program counter high
Program counter low
X index register high
X index register low
Y index register high
Y index register low
Stack pointer high
Stack pointer low
Condition code register
Reserved area (85 byte)
Global configuration register
Interrupt software priority register 1
Interrupt software priority register 2
Interrupt software priority register 3
Interrupt software priority register 4
Interrupt software priority register 5
Interrupt software priority register 6
Interrupt software priority register 7
Interrupt software priority register 8
Reserved area (2 byte)
SWIM control status register
Reserved area (15 byte)
0x00
0x00
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
Reset
Status
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x17
(2)
0xFF
0x28
DS8633 Rev 6
35/93
37
Memory and register map STM8S007C8
Address
Table 9. CPU/SWIM/debug module/interrupt controller registers (continued)
Block Register Label Register Name
0x00 7F90
0x00 7F91
0x00 7F92
0x00 7F93
0x00 7F94
0x00 7F95
0x00 7F96
0x00 7F97
0x00 7F98
0x00 7F99
0x00 7F9A
0x00 7F9B to
0x00 7F9F
DM
DM_BK1RE
DM_BK1RH
DM_BK1RL
DM_BK2RE
DM_BK2RH
DM_BK2RL
DM_CR1
DM_CR2
DM_CSR1
DM_CSR2
DM_ENFCTR
1. Accessible by debug module only
2. Product dependent value, see
Figure 4: Memory map
.
DM breakpoint 1 register extended byte
DM breakpoint 1 register high byte
DM breakpoint 1 register low byte
DM breakpoint 2 register extended byte
DM breakpoint 2 register high byte
DM breakpoint 2 register low byte
DM debug module control register 1
DM debug module control register 2
DM debug module control/status register 1
DM debug module control/status register 2
DM enable function register
Reserved area (5 byte)
Reset
Status
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0x00
0x00
0x10
0x00
0xFF
36/93
DS8633 Rev 6
