STM8S007C8
7 Interrupt vector mapping
Interrupt vector mapping
11
20
21
22
23
24
12
13
14
15
16
17
18
19
IRQ no.
3
4
1
2
5
-
-
0
6
7
8
9
10
Source block
Table 10. Interrupt mapping
Description
Wakeup from
Halt mode
Wakeup from
Active-halt mode
RESET Reset
TRAP
TLI
Software interrupt
External top level interrupt
AWU
CLK
EXTI0
EXTI1
EXTI2
EXTI3
EXTI4
-
-
SPI
TIM1
TIM1
TIM2
TIM2
TIM3
TIM3
Auto wake up from halt
Clock controller
Port A external interrupts
Port B external interrupts
Port C external interrupts
TIM2 capture/compare
Update/overflow
Capture/compare
Yes
-
-
-
-
-
-
-
Yes
(1)
Yes
Port D external interrupts
Port E external interrupts
Yes
Yes
Yes
Reserved
Reserved
End of transfer
TIM1 update/overflow/underflow/ trigger/break
TIM1 capture/compare
TIM2 update /overflow
Yes
-
-
-
UART1
UART1
I
2
C
UART3
UART3
ADC2
Tx complete
Receive register DATA FULL
I
2
C interrupt
Tx complete
Receive register DATA FULL
ADC2 end of conversion
TIM4 TIM4 update/overflow
Flash EOP/WR_PG_DIS
-
-
-
-
-
Yes
-
-
Yes
-
Yes
-
-
Yes
-
Yes
(1)
Yes
Yes
Yes
Yes
-
-
-
-
-
-
-
-
-
-
-
-
Yes
Reserved
1. Except PA1
Vector address
0x00 8034
0x00 8038
0x00 803C
0x00 8040
0x00 8044
0x00 8048
0x00 804C
0x00 8050
0x00 8054
0x00 8058
0x00 805C
0x00 8060
0x00 8064
0x00 8000
0x00 8004
0x00 8008
0x00 800C
0x00 8010
0x00 8014
0x00 8018
0x00 801C
0x00 8020
0x00 8024
0x00 8028
0x00 802C
0x00 8030
0x00 806C to
0x00 807C
DS8633 Rev 6
37/93
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