STMicroelectronics STD4NK50Z-1 Datasheet
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STD4NK50Z-1, STD4NK50ZT4
Datasheet
N-channel 500 V, 2.2 Ω typ., 3 A SuperMESH™ Power MOSFETs in
IPAK and DPAK packages
TAB
IPAK 1
2
3
G(1)
D(2, TAB)
S(3)
Product status link
STD4NK50Z-1
STD4NK50ZT4
TAB
DPAK
2
1
3
Features
Order codes V
DS
STD4NK50Z-1
500 V
STD4NK50ZT4
• Extremely high dv/dt capability
• 100% avalanche tested
• Gate charge minimized
• Very low intrinsic capacitance
• Zener-protected
R
DS(on)
max.
2.7 Ω
Applications
• Switching applications
AM01475V1
P
TOT
45 W
Package
IPAK
DPAK
Description
These high-voltage devices are Zener-protected N-channel Power MOSFETs developed using the SuperMESH™ technology by STMicroelectronics, an optimization of the well-established PowerMESH™. In addition to a significant reduction in on-resistance, these devices are designed to ensure a high level of dv/dt capability for the most demanding applications.
DS2913 - Rev 3 - August 2018
For further information contact your local STMicroelectronics sales office.
www.st.com
1
STD4NK50Z-1, STD4NK50ZT4
Electrical ratings
Electrical ratings
Table 1. Absolute maximum ratings
Symbol
V
DS
V
GS
I
D
I
D
I
DM
P
TOT dv/dt
ESD
T j
T stg
Drain-source voltage
Gate-source voltage
Drain current (continuous) at T
C
Drain current (continuous) at T
C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
Parameter
= 25 °C
= 100 °C
Peak diode recovery voltage slope
Gate-source human body model (C = 100 pF, R = 1.5 kΩ)
Operating junction temperature range
Storage temperature range
1. Pulse width limited by safe operating area.
2. I
SD
≤ 3 A, di/dt ≤ 200 A/µs, V
DD
≤ V
(BR)DSS
.
Symbol
Table 2. Thermal data
Parameter
R thj-case
R thj-amb
R thj-pcb
Thermal resistance junction-case
Thermal resistance junction-ambient
Thermal resistance junction-pcb
1. When mounted on an 1-inch² FR-4, 2oz Cu board.
IPAK
Value
DPAK
2.78
100
50
Value
500
±30
3
1.9
12
45
4.5
2.8
-55 to 150
Symbol
I
AR
E
AS
Table 3. Avalanche characteristics
Parameter
Avalanche current, repetitive or not-repetitive
(pulse width limited by T j
max)
Single pulse avalanche energy
(starting T j
= 25 °C, I
D
= I
AR
, V
DD
= 50 V)
Value
3
120
Unit
°C/W
°C/W
°C/W
A
A
A
Unit
V
V
W
V/ns kV
°C
Unit
A mJ
DS2913 - Rev 3 page 2/23
2
STD4NK50Z-1, STD4NK50ZT4
Electrical characteristics
Electrical characteristics
(T
CASE
= 25 °C unless otherwise specified)
Table 4. On/off states
Symbol
V
(BR)DSS
Parameter
Drain-source breakdown voltage
V
GS
Test conditions
= 0 V, I
D
= 1 mA
V
R
I
I
DSS
GSS
GS(th)
DS(on)
Zero gate voltage drain current
Gate-body leakage current
Gate threshold voltage
Static drain-source on resistance
V
GS
= 0 V, V
DS
= 500 V
V
GS
= 0 V, V
DS
= 500 V,
T
C
= 125 °C
V
V
DS
V
DS
GS
1. Defined by design, not subject to production test.
= 0 V, V
= V
GS
GS
, I
D
= 10 V, I
D
= ±20 V
= 50 µA
= 1.5 A
Min.
500
3
Typ.
3.75
2.2
Max.
1
50
±10
4.5
2.7
Table 5. Dynamic
Symbol
C iss
C oss
C rss
C oss eq.
Q g
Q gs
Q gd
Parameter
Input capacitance
Test conditions
Output capacitance
V
DS
= 25 V, f = 1 MHz,
V
GS
= 0 V
Reverse transfer capacitance
Equivalent output capacitance V
GS
= 0 V, V
DS
= 0 V to 400 V
Total gate charge
Gate-source charge
Gate-drain charge
V
DD
= 400 V, I
D
V
GS
= 0 to 10 V
= 3 A,
(see Figure 14. Test circuit for gate charge behavior
)
Min.
-
-
-
Typ.
310
49
10
33
12
3
7
Max.
Unit pF nC
1. C oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C oss
when V
DS increases from 0 to
80% V
DSS
.
Symbol t d(on) t r t d(off) t f
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Table 6. Switching times
Test conditions
V
DD
= 250 V, I
D
= 1.5 A,
R
G
= 4.7 Ω, V
GS
= 10 V
(see Figure 13. Test circuit for resistive load switching times
and
Figure 18. Switching time waveform )
Min.
-
Typ.
10
7
21
11
Max.
Unit ns
µA
µA
V
Ω
Unit
V
µA
DS2913 - Rev 3 page 3/23
DS2913 - Rev 3
STD4NK50Z-1, STD4NK50ZT4
Electrical characteristics
Table 7. Source-drain diode
Symbol
I
SD
I
SDM
V
SD
I t
Q rr rr
RRM
Parameter
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Test conditions
I
SD
= 3 A, V
GS
= 0 V
I
SD
= 3 A, di/dt = 100 A/µs
V
DD
= 40 V, T j
= 150 °C
(see Figure 15. Test circuit for inductive load switching and diode recovery times
)
1. Pulse width limited by safe operating area.
2. Pulsed: Pulse duration = 300 μs, duty cycle 1.5 %.
Min.
-
-
-
-
-
-
Symbol
V
(BR)GSO
Parameter
Gate-source breakdown voltage
Table 8. Gate-source Zener diode
Test conditions Min.
I
GS
= ±1 mA, I
D
= 0 A ±30
260
935
7.2
Typ.
Max.
3
12
1.6
Unit
A
V ns nC
A
Typ.
-
Max.
-
Unit
V
The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device.
The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry.
page 4/23
STD4NK50Z-1, STD4NK50ZT4
Electrical characteristics (curves)
2.1
Electrical characteristics (curves)
Figure 1. Safe operating area
Figure 3. Output characterisics
K
Figure 2. Thermal impedance
GC20460
10 0
10 -1
10 -2
10 -5 10 -4 10 -3 10 -2 10 -1 t p
(s)
Figure 4. Transfer characteristics
Figure 5. Capacitance variations Figure 6. Gate charge vs gate-source voltage
DS2913 - Rev 3 page 5/23
Figure 7. Normalized gate threshold voltage vs temperature
STD4NK50Z-1, STD4NK50ZT4
Electrical characteristics (curves)
Figure 8. Static drain-source on resistance
Figure 9. Source-drain diode forward characteristic Figure 10. Maximum avalanche energy vs temperature
Figure 11. Normalized V
(BR)DSS
vs temperature Figure 12. Normalized on resistance vs temperature
DS2913 - Rev 3 page 6/23
STD4NK50Z-1, STD4NK50ZT4
Test circuits
3
Test circuits
Figure 13. Test circuit for resistive load switching times
V
GS pulse width
V
D
R
G
R
L
+
2200
μF
3.3
μF
D.U.T.
V
DD
AM01468v1
Figure 15. Test circuit for inductive load switching and diode recovery times
Figure 14. Test circuit for gate charge behavior
12 V
V
GS pulse width
2200
μF
+
1 kΩ
I
G
= CONST
2.7 kΩ
47 kΩ
47 kΩ
100 nF
100 Ω
V
DD
1 kΩ
D.U.T.
V
G
AM01469v1
Figure 16. Unclamped inductive load test circuit
G
25 Ω
D
A
D.U.T.
S
B
+
_
R
G
A A fast diode
B
B
G
100 µH
D
D.U.T.
3.3
µF
S
+
1000
µF
V
DD
AM01470v1
Figure 17. Unclamped inductive waveform
V (BR)DSS
V D
I
DM
I D
V DD V DD
AM01472v1
V i pulse width
V
D
L
I
D
+
2200
µF
3.3
µF
V
DD
D.U.T.
AM01471v1
0
Figure 18. Switching time waveform t d(on) t on t r t d(off) t off t f
90% 90%
10%
V
GS
V
DS
90%
10%
0 10%
AM01473v1
DS2913 - Rev 3 page 7/23
4
STD4NK50Z-1, STD4NK50ZT4
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com
. ECOPACK ® is an ST trademark.
DS2913 - Rev 3 page 8/23
4.1
STD4NK50Z-1, STD4NK50ZT4
IPAK (TO-251) type A package information
IPAK (TO-251) type A package information
Figure 19. IPAK (TO-251) type A package outline
DS2913 - Rev 3
0068771_IK_typeA_rev14 page 9/23
DS2913 - Rev 3
Dim.
D
E e c c2 e1
H
L
L1
L2
V1
A
A1 b b2 b4
B5
STD4NK50Z-1, STD4NK50ZT4
IPAK (TO-251) type A package information
Table 9. IPAK (TO-251) type A package mechanical data mm
Typ.
Min.
2.20
0.90
0.64
5.20
0.45
0.48
6.00
6.40
4.40
9.00
0.80
0.30
2.28
16.10
0.80
10°
0.60
0.60
6.20
6.60
4.60
Max.
2.40
1.10
0.90
0.95
5.40
9.40
1.20
1.00
page 10/23
4.2
STD4NK50Z-1, STD4NK50ZT4
IPAK (TO-251) type C package information
IPAK (TO-251) type C package information
Figure 20. IPAK (TO-251) type C package outline
DS2913 - Rev 3
0068771_IK_typeC_rev14 page 11/23
DS2913 - Rev 3
Dim.
c2
D
D1
E
E1 e e1
A
A1 b b2 b4 c
L2
θ1
θ2
H
L
L1
STD4NK50Z-1, STD4NK50ZT4
IPAK (TO-251) type C package information
Table 10. IPAK (TO-251) type C package mechanical data
Min.
2.20
0.90
0.66
mm
Typ.
2.30
1.00
5.20
6.50
4.60
2.20
4.40
5.23
0.46
0.46
6.00
16.18
9.00
0.80
0.90
3°
1°
5.33
6.10
5.37
6.60
4.78
2.25
4.50
16.48
9.30
1.00
1.08
5°
3°
16.78
9.60
1.20
1.25
7°
5°
5.55
6.70
4.95
2.30
4.60
0.90
5.43
0.59
0.59
6.20
Max.
2.35
1.10
0.79
page 12/23
4.3
STD4NK50Z-1, STD4NK50ZT4
DPAK (TO-252) type A package information
DPAK (TO-252) type A package information
Figure 21. DPAK (TO-252) type A package outline
DS2913 - Rev 3
0068772_A_25 page 13/23
DS2913 - Rev 3
Dim.
c2
D
D1
E
E1 e e1
A
A1
A2 b b4 c
L2
L4
R
V2
H
L
(L1)
STD4NK50Z-1, STD4NK50ZT4
DPAK (TO-252) type A package information
Table 11. DPAK (TO-252) type A mechanical data mm
Typ.
9.35
1.00
2.60
0.65
0.60
4.95
6.40
4.60
2.159
4.445
0.64
5.20
0.45
0.48
6.00
Min.
2.20
0.90
0.03
5.10
4.70
2.286
4.572
2.80
0.80
0.20
0°
10.10
1.50
3.00
0.95
1.00
5.25
6.60
4.80
2.413
4.699
0.90
5.40
0.60
0.60
6.20
Max.
2.40
1.10
0.23
8° page 14/23
4.4
STD4NK50Z-1, STD4NK50ZT4
DPAK (TO-252) type C package information
DPAK (TO-252) type C package information
Figure 22. DPAK (TO-252) type C package outline
DS2913 - Rev 3
0068772_C_25 page 15/23
DS2913 - Rev 3
Dim.
L
L1
L2
L3
L4
L6
θ1
θ2
V2 c2
D
D1
E
E1 e
H
A
A1
A2 b b4 c
STD4NK50Z-1, STD4NK50ZT4
DPAK (TO-252) type C package information
Table 12. DPAK (TO-252) type C mechanical data
0.72
5.13
0.47
0.47
6.00
Min.
2.20
0.90
0.00
5.25
6.50
4.70
2.186
9.80
1.40
mm
Typ.
2.30
1.01
5.33
6.10
6.60
2.286
10.10
1.50
2.90 REF
0.90
0.60
5°
5°
0°
0.51 BSC
0.80
1.80 BSC
7°
7°
6.70
2.386
10.40
1.70
1.25
0.85
5.46
0.60
0.60
6.20
Max.
2.38
1.10
0.10
1.00
9°
9°
8° page 16/23
STD4NK50Z-1, STD4NK50ZT4
DPAK (TO-252) type C package information
Figure 23. DPAK (TO-252) recommended footprint (dimensions are in mm)
FP_0068772_25_C
DS2913 - Rev 3 page 17/23
4.5
STD4NK50Z-1, STD4NK50ZT4
DPAK (TO-252) packing information
DPAK (TO-252) packing information
Figure 24. DPAK (TO-252) tape outline
T
Top cover tape
10 pitches cumulative tolerance on tape +/- 0.2 mm
P0 D P2
F
E
W
B1
K0
For machine ref. only including draft and radii concentric around B0
B0
A0 P1
User direction of feed
D1
User direction of feed
R
Bending radius
AM08852v1
DS2913 - Rev 3 page 18/23
DS2913 - Rev 3
Dim.
D1
E
F
K0
P0
A0
B0
B1
D
P1
P2
R
T
W
A
D
B
STD4NK50Z-1, STD4NK50ZT4
DPAK (TO-252) packing information
Figure 25. DPAK (TO-252) reel outline
T
40mm min. access hole at slot location
C
N
G measured at hub
Full radius
Tape slot in core for tape start
2.5mm min.width
AM06038v1
2.55
3.9
7.9
1.9
40
0.25
15.7
1.5
1.5
1.65
7.4
Table 13. DPAK (TO-252) tape and reel mechanical data
Tape Reel mm
Dim.
Min.
6.8
10.4
Max.
7
10.6
12.1
1.6
C
D
A
B
G
N
T
Min.
1.5
12.8
20.2
16.4
50 1.85
7.6
2.75
4.1
8.1
2.1
0.35
16.3
Base qty.
Bulk qty.
mm
Max.
330
13.2
18.4
22.4
2500
2500 page 19/23
5
STD4NK50Z-1, STD4NK50ZT4
Ordering information
Ordering information
Order code
STD4NK50Z-1
STD4NK50ZT4
Table 14. Order codes
Marking
D4NK50Z
Package
IPAK
DPAK
Packing
Tube
Tape and reel
DS2913 - Rev 3 page 20/23
STD4NK50Z-1, STD4NK50ZT4
Revision history
Date
09-Dec-2002
20-Aug-2018
Version
2
3
Table 15. Document revision history
Changes
Updated document.
Removed maturity status indication from cover page. The document status is production data.
The part numbers STP4NK50Z and STP4NK50FP have been moved to a separate datasheet.
Updated Section 1 Electrical ratings ,
Section 2 Electrical characteristics
and
.
Added
Section 5 Ordering information
.
Minor text changes.
DS2913 - Rev 3 page 21/23
STD4NK50Z-1, STD4NK50ZT4
Contents
Contents
DS2913 - Rev 3 page 22/23
STD4NK50Z-1, STD4NK50ZT4
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
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ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2018 STMicroelectronics – All rights reserved
DS2913 - Rev 3 page 23/23
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