- Computers & electronics
- Computer components
- System components
- Server/workstation motherboards
- HP (Hewlett-Packard)
- PCI-9111DG/HR
- User's Guide
A/D Trigger Source Control. HP (Hewlett-Packard) NuDAQ PCI-9111HR, PCI-9111DG/HR
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Signal Range
The proper signal range is important for data acquisition. The input signal may be saturated if the A/D gain is too large. Sometimes, the resolution may be not enough if the signal is small. The maximum A/D signal range of PCI-9111 is +/- 10 volts when the A/D gain value is 1. The A/D gain control register controls the maximum signal input range. The signal gain is programmable with 5 levels (1, 2, 4, 8, 16). The signal range of the 16 channels will be identical all the time even if the channel number is scanning.
The available signal polarity on PCI-9111 is bi-polar but no uni-polar configuration. However, the bi-polar input range still covers the uni-polar applications. In addition the high resolution of the PCI-9111HR can cover the normal industry applications. Therefore, PCI-9111 is suitable for full range of applications.
4.1.3 A/D Trigger Source Control
The A/D conversion is starting by a trigger source, and then the A/D converter will start to convert the signal to a digital value. In the PCI-9111,
A/D conversion can be triggered by the Internal or External trigger source.
The EITS bit of A/D control register is used to handle the internal or external trigger, please refer to section 3.8 for details. Whenever the external source is set, the internal sources are disabled.
If the internal trigger is selected, two internal sources can be selected: the software trigger or the timer pacer trigger. The A/D operation mode is controlled by A/D mode bits (EITS, TPST) of A/D mode register. Total three trigger sources are provided in the PCI-9111. The different trigger conditions are specified as follows:
Software trigger (EITS=0, TPST=0)
The trigger source is software controllable in this mode. That is, the A/D conversion is starting when any value is written into the software trigger register. This trigger mode is suitable for low speed A/D conversion.
Under this mode, the timing of the A/D conversion is fully controlled by software. However, it is difficult to control the fixed A/D conversion rate unless another timer interrupt service routine is used to generate a fixed rate trigger. Refer to interrupt control section for fixed rate timer interrupt.
Timer Pacer Trigger (EITS=0, TPST=1)
An on-board timer / counter chip 8254 is used to provide a trigger source for A/D conversion at a fixed rate. Two counters of the 8254 chip are cascaded together to generate trigger pulse with precise period. Please
Operation Theorem • 25
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Table of contents
- 11 Features
- 12 Applications
- 12 Specifications
- 14 Software Supporting
- 14 Programming Library
- 15 Driver
- 15 PCIS-VEE: HP-VEE Driver
- 15 : ActiveX Controls
- 15 driver
- 16 Driver
- 16 PCIS-OPC: OPC Server
- 17 What You Have
- 17 Unpacking
- 18 PCI-9111's Layout
- 19 Jumper Descriptions
- 19 Hardware Installation Outline
- 20 Device Installation for Windows Systems
- 20 Connectors Pin Assignment
- 22 Daughter Board Connection
- 22 Connect with ACLD
- 22 Connect with ACLD-9138 and ACLD
- 23 PCI PnP Registers
- 24 I/O Address Map
- 24 A/D Data Registers
- 25 A/D Channel Control Register
- 26 A/D Channel Read Back Register
- 26 A/D Input Signal Range Control Register
- 27 A/D Range and Status Readback Register
- 27 A/D Trigger Mode Control Register
- 28 Software Trigger Register
- 28 Interrupt Control Register
- 29 Hardware Interrupt Clear Register
- 29 A/D Mode & Interrupt Control Read Back Register
- 30 Extended I/O Ports
- 30 Digital I/O register
- 31 D/A Output Register
- 31 Timer/Counter Register
- 32 A/D Conversion
- 33 A/D Conversion Procedure
- 33 A/D Signal Source Control
- 35 A/D Trigger Source Control
- 36 A/D Data Transfer Modes
- 38 Pre-Trigger Control
- 40 A/D Data Format
- 41 Interrupt Control
- 41 System Architecture
- 41 IRQ Level Setting
- 41 Dual Interrupt System
- 42 Interrupt Source Control
- 42 Extended Digital I/O Port
- 43 D/A Conversion
- 44 Digital Input and Output
- 44 Timer/Counter Operation
- 44 Introduction
- 45 Pacer Trigger Source
- 45 Pre-Trigger Counter
- 45 I/O Address
- 46 Libraries Installation
- 47 Programming Guide
- 47 Naming Convention
- 47 Data Types
- 48 _9111_Initial
- 48 _9111_DO
- 49 _9111_DO_Channel
- 49 _9111_DI
- 50 _9111_DI_Channel
- 50 _9111_EDI
- 51 _9111_EDO
- 51 _9111_EDO_Read_Back
- 52 _9111_Set_EDO_Function
- 53 _9111_DA
- 53 _9111_AD_Read_Data
- 54 _9111_AD_Read_Data_Repeat
- 54 _9111_AD_Set_Channel
- 55 _9111_AD_Get_Channel
- 56 _9111_AD_Set_Range
- 57 _9111_AD_Get_Range
- 57 _9111_AD_Get_Status
- 58 _9111_AD_Set_Mode
- 59 _9111_AD_Get_Mode
- 59 _9111_INT_Set_Reg
- 60 _9111_INT_Get_Reg
- 60 _9111_Reset_FIFO
- 61 _9111_AD_Soft_Trigger
- 61 _9111_Set
- 62 _9111_Get
- 62 _9111_AD_Timer
- 63 _9111_Counter_Start
- 63 _9111_Counter_Read
- 64 _9111_Counter_Stop
- 65 _9111_INT_Source_Control
- 66 _9111_CLR_IRQ
- 66 _9111_Get_IRQ_Channel
- 67 _9111_Get_IRQ_Status
- 67 _9111_AD_FFHF_Polling
- 68 _9111_AD_Aquire
- 68 _9111_AD_HR_Aquire
- 69 _9111_AD_INT_Start
- 70 _9111_AD_FFHF_INT_Start
- 72 _9111_AD_INT_Status
- 72 _9111_AD_FFHF_INT_Status
- 73 _9111_AD_FFHF_INT_Restart
- 74 _9111_AD_INT_Stop
- 75 What do you need
- 76 VR Assignment
- 76 A/D Adjustment
- 77 D/A Adjustment
- 77 Unipolar Analog Output
- 77 Bipolar Analog Output
- 78 9111util
- 78 Running 9111util.exe
- 79 System Configuration
- 80 Calibration
- 81 Functional Testing
- 82 I_EEPROM