A/D Data Transfer Modes. HP (Hewlett-Packard) NuDAQ PCI-9111HR, PCI-9111DG/HR

refer to section 4.6 for timer/counter operation. This mode is ideal for high speed A/D conversion. It can be combined with the FIFO half full interrupt or EOC interrupt to transfer data. It is also possible to use software FIFO polling to transfer data. The A/D trigger, A/D data transfer and Interrupt can be set independently, most of the complex applications can thus be covered.

It's recommend to use this mode if your applications need a fixed and precise A/D sampling rate.

External Trigger (EITS=1, TPST=don‘t care)

Through the pin-16 of CN3 (ExtTrig), the A/D conversion also can be triggered by an external signal. The A/D conversion starts as ExtTrig changes from high to low. The conversion rate of this mode is more flexible than the previous two modes, because the users can handle the external signal by the outside device. The external trigger can be also combined with the FIFO half interrupt, EOC interrupt or program FIFO polling to transfer data.

4.1.4 A/D Data Transfer Modes

The A/D data are buffered in the FIFO memory. The FIFO size on

PCI-9111 is 1024 (1K) words. If the sampling rate is 100 KHz, the FIFO can buffer 10.24 ms analog signal. After the FIFO is full, the lasting coming data will be lost. The software must read out the FIFO data before it becomes full.

The data must be transferred to host memory after the date is ready and before the FIFO is full. On the PCI-9111, many data transfer modes can be used. The different transfer modes are specified as follows:

Software Data Polling

The software data polling is the easiest way to transfer A/D data. This mode can be used with software A/D trigger mode. After the A/D conversion is triggered by software, the software should poll the FF_EF bit of the A/D status register until it becomes low level.

If the FIFO is empty before the A/D start, the FF_EF bit will be low. After the A/D is completed, the A/D data is written to FIFO immediately, therefore the FF_EF becomes high. You can consider the FF_EF bit as converted data ready status. That is, FF_EF is high means the data is ready. Note that, while A/D is converted, the ADBUSY bit is low. After A/D conversion, the ADBUSY become high to indicate not busy. Please do

NOT use this bit to poll the AD data.

26 • Operation Theorem

It is possible to read A/D converted data without polling. The A/D conversion time will not exceed 8.5

µ s on PCI-9111 card. Hence, after software trigger, the software can wait for a t least 8.5

µ s then read the A/D register without polling.

The data polling transferring is very suitable for the application need to process AD data in real time. Especially when combining with the timer interrupt generation, the timer interrupt service routine can use the data polling method to get multi-channel A/D data in real time and under fixed data sampling rate.

FIFO Half-Full Polling

The FIFO half-full polling mode is the most powerful AD data transfer mode. The 1 K words FIFO can store up to 10.2 4 ms analog data under

100 KHz sampling rate (10.024ms = 1024/100 KHz). Theoretically, the software can poll the FIFO every 10 ms without taking care how to trigger

A/D or transfer A/D data.

ADLINK recommend user to check your system to find out the user software‘s priority in the special application. If the application software is at the highest priority, to poll the FIFO every 10 ms is suitable. However, the user‘s program must check the FIFO is full or empty every time reading data.

To avoid this problem, the half-full polling method is used. If the A/D trigger rate is 100KHz, the FIFO will be half-full (512 words) in 5.12 ms. If the user‘s software checks the FIFO half full signal every 5 ms. When the

FIFO is not half-full, the software does not read data, because it is difficult to know how much A/D data is stored in the FIFO and user must check the FIFO empty bit every time reading data. When the FIFO is full, the

AD FIFO is overrun. This means the sampling rate is higher than users expect or the polling rate is too slow, it is also possible due to your system occupy the CPU resource thus reducing the polling rate. When the FIFO is half-full and not full, the software can read one “block” (512 words) A/D data without check the FIFO status. This method is very convenient to read A/D in size of a “block” and it is benefit to software programming.

Usually, the timer trigger is used under this mode, therefore the sampling rate is fixed. The method also utilizes the minimum CPU resources because it is not necessary to be highest priority. The other benefit is this method will not use hardware interrupt resource. Therefore, the interrupt is reserved for system clock or emergency external interrupt request. The

FIFO half-full polling method is the most powerful A/D data transfer mode.

Operation Theorem • 27