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- AT80571RG0601ML
- Data Sheet
Reserved, Unused, and TESTHI Signals. Intel AT80571RG0601ML, AT80571RG0561ML
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2.4
2.5
Electrical Specifications
Reserved, Unused, and TESTHI Signals
All RESERVED lands must remain unconnected. Connection of these lands to V
V
TT, processor and the location of all RESERVED lands.
CC
, V
SS
,
or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See
Chapter 4 for a land listing of the
In a system level design, on-die termination has been included by the processor to allow signals to be terminated within the processor silicon. Most unused GTL+ inputs should be left as no connects as GTL+ termination is provided on the processor silicon.
for details on GTL+ signals that do not include on-die termination.
Unused active high inputs, should be connected through a resistor to ground (V
SS
).
Unused outputs can be left unconnected, however this may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying bidirectional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for system testability. Resistor values should be within ± 20% of the impedance of the motherboard trace for front side bus signals. For unused GTL+ input or I/O signals, use pull-up resistors of the same value as the on-die termination resistors (R
TT
). For details see
TAP and CMOS signals do not include on-die termination. Inputs and utilized outputs must be terminated on the motherboard. Unused outputs may be terminated on the motherboard or left unconnected. Note that leaving unused outputs unterminated may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing.
All TESTHI[12,10:0] lands should be individually connected to V
TT resistor which matches the nominal trace impedance.
using a pull-up
The TESTHI signals may use individual pull-up resistors or be grouped together as detailed below. A matched resistor must be used for each group:
• TESTHI[1:0]
• TESTHI[7:2]
• TESTHI8/FC42 – cannot be grouped with other TESTHI signals
• TESTHI9/FC43 – cannot be grouped with other TESTHI signals
• TESTHI10 – cannot be grouped with other TESTHI signals
• TESTHI12/FC44 – cannot be grouped with other TESTHI signals
Terminating multiple TESTHI pins together with a single pull-up resistor is not recommended for designs supporting boundary scan for proper Boundary Scan testing of the TESTHI signals. For optimum noise margin, all pull-up resistor values used for
TESTHI[12,10:0] lands should have a resistance value within ± 20% of the impedance of the board transmission line traces. For example, if the nominal trace impedance is
50
Ω
, then a value between 40 Ω and 60 Ω should be used.
Power Segment Identifier (PSID)
Power Segment Identifier (PSID) is a mechanism to prevent booting under mismatched power requirement situations. The PSID mechanism enables BIOS to detect if the processor in use requires more power than the platform voltage regulator (VR) is capable of supplying. For example, a 130 W TDP processor installed in a board with a
65 W or 95 W TDP capable VR may draw too much power and cause a potential VR issue.
16 Datasheet
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Key Features
- IntelĀ® CeleronĀ® E3200 2.4 GHz
- 1 MB L2 LGA 775 (Socket T)
- Processor cores: 2 45 nm 64-bit 65 W
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Table of contents
- 9 Introduction
- 9 Terminology
- 10 Processor Terminology Definitions
- 11 References
- 13 Electrical Specifications
- 13 Power and Ground Lands
- 13 Decoupling Guidelines
- 13 VCC Decoupling
- 13 VTT Decoupling
- 14 FSB Decoupling
- 14 Voltage Identification
- 16 Reserved, Unused, and TESTHI Signals
- 16 Power Segment Identifier (PSID)
- 17 Voltage and Current Specification
- 17 Absolute Maximum and Minimum Ratings
- 18 DC Voltage and Current Specification
- 20 VCC Overshoot
- 21 Die Voltage Validation
- 21 Signaling Specifications
- 22 FSB Signal Groups
- 23 CMOS and Open Drain Signals
- 24 Processor DC Specifications
- 25 Platform Environment Control Interface (PECI) DC Specifications
- 26 GTL+ Front Side Bus Specifications
- 27 Clock Specifications
- 27 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking
- 28 FSB Frequency Select Signals (BSEL[2:0])
- 29 Phase Lock Loop (PLL) and Filter
- 29 BCLK[1:0] Specifications
- 33 Package Mechanical Specifications
- 33 Package Mechanical Drawing
- 37 Processor Component Keep-Out Zones
- 37 Package Loading Specifications
- 37 Package Handling Guidelines
- 38 Package Insertion Specifications
- 38 Processor Mass Specification
- 38 Processor Materials
- 38 Processor Markings
- 39 Processor Land Coordinates
- 41 Land Listing and Signal Descriptions
- 41 Processor Land Assignments
- 64 Alphabetical Signals Reference
- 75 Thermal Specifications and Design Considerations
- 75 Processor Thermal Specifications
- 75 Thermal Specifications
- 78 Thermal Metrology
- 78 Processor Thermal Features
- 78 Thermal Monitor
- 80 On-Demand Mode
- 81 PROCHOT# Signal
- 81 THERMTRIP# Signal
- 82 Platform Environment Control Interface (PECI)
- 82 Introduction
- 82 TCONTROL and TCC activation on PECI-Based Systems
- 83 PECI Specifications
- 83 PECI Device Address
- 83 PECI Command Support
- 83 PECI Fault Handling Requirements
- 83 PECI GetTemp0() Error Code Support
- 85 Features
- 85 Power-On Configuration Options
- 85 Clock Control and Low Power States
- 86 Normal State
- 86 HALT and Extended HALT Powerdown States
- 86 HALT Powerdown State
- 87 Extended HALT Powerdown State
- 87 Stop Grant and Extended Stop Grant States
- 87 Stop-Grant State
- 88 Extended Stop Grant State
- 88 Stop Grant Snoop State, and Stop Grant Snoop State
- 88 HALT Snoop State, Stop Grant Snoop State
- 88 Extended HALT Snoop State, Extended Stop Grant Snoop State
- 88 Sleep State
- 89 Deep Sleep State
- 89 Deeper Sleep State
- 90 Technology
- 90 Processor Power Status Indicator (PSI) Signal
- 91 Boxed Processor Specifications
- 91 Introduction
- 92 Mechanical Specifications
- 92 Boxed Processor Cooling Solution Dimensions
- 93 Boxed Processor Fan Heatsink Weight
- 93 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly
- 93 Electrical Requirements
- 93 Fan Heatsink Power Supply
- 95 Thermal Specifications
- 95 Boxed Processor Cooling Requirements
- 97 Variable Speed Fan
- 99 Debug Tools Specifications
- 99 Logic Analyzer Interface (LAI)
- 99 Mechanical Considerations
- 99 Electrical Considerations