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- AT80571RG0601ML
- Data Sheet
Processor Component Keep-Out Zones. Intel AT80571RG0601ML, AT80571RG0561ML
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Package Mechanical Specifications
3.2
3.3
.
Table 19.
3.4
Table 20.
Processor Component Keep-Out Zones
The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate. See
and
for keep-out zones. The location and quantity of package capacitors may change due to manufacturing efficiencies but will remain within the component keep-in.
Package Loading Specifications
provides dynamic and static load specifications for the processor package.
These mechanical maximum load limits should not be exceeded during heatsink assembly, shipping conditions, or standard use condition. Also, any mechanical system or component testing should not exceed the maximum limits. The processor package substrate should not be used as a mechanical reference or load-bearing surface for thermal and mechanical solution. The minimum loading specification must be maintained by any thermal and mechanical solutions.
Processor Loading Specifications
Parameter Minimum Maximum Notes
Static
Dynamic
80 N [17 lbf]
-
311 N [70 lbf]
756 N [170 lbf]
1, 2, 3
1, 3, 4
NOTES:
1.
2.
These specifications apply to uniform compressive loading in a direction normal to the processor IHS.
This is the maximum force that can be applied by a heatsink retention clip. The clip must
3.
4.
also provide the minimum specified load on the processor package.
These specifications are based on limited testing for design characterization. Loading limits are for the package only and do not include the limits of the processor socket.
Dynamic loading is defined as an 11 ms duration average load superimposed on the static load requirement.
Package Handling Guidelines
includes a list of guidelines on package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate. These package handling loads may be experienced during heatsink removal.
Package Handling Guidelines
Parameter Maximum Recommended Notes
Shear
Tensile
Torque
311 N [70 lbf]
111 N [25 lbf]
3.95 N-m [35 lbf-in]
1, 4
2, 4
3, 4
NOTES:
1.
A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface.
2.
3.
4.
A tensile load is defined as a pulling load applied to the IHS in a direction normal to the
IHS surface.
A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top surface.
These guidelines are based on limited testing for design characterization.
Datasheet 37
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Key Features
- IntelĀ® CeleronĀ® E3200 2.4 GHz
- 1 MB L2 LGA 775 (Socket T)
- Processor cores: 2 45 nm 64-bit 65 W
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Table of contents
- 9 Introduction
- 9 Terminology
- 10 Processor Terminology Definitions
- 11 References
- 13 Electrical Specifications
- 13 Power and Ground Lands
- 13 Decoupling Guidelines
- 13 VCC Decoupling
- 13 VTT Decoupling
- 14 FSB Decoupling
- 14 Voltage Identification
- 16 Reserved, Unused, and TESTHI Signals
- 16 Power Segment Identifier (PSID)
- 17 Voltage and Current Specification
- 17 Absolute Maximum and Minimum Ratings
- 18 DC Voltage and Current Specification
- 20 VCC Overshoot
- 21 Die Voltage Validation
- 21 Signaling Specifications
- 22 FSB Signal Groups
- 23 CMOS and Open Drain Signals
- 24 Processor DC Specifications
- 25 Platform Environment Control Interface (PECI) DC Specifications
- 26 GTL+ Front Side Bus Specifications
- 27 Clock Specifications
- 27 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking
- 28 FSB Frequency Select Signals (BSEL[2:0])
- 29 Phase Lock Loop (PLL) and Filter
- 29 BCLK[1:0] Specifications
- 33 Package Mechanical Specifications
- 33 Package Mechanical Drawing
- 37 Processor Component Keep-Out Zones
- 37 Package Loading Specifications
- 37 Package Handling Guidelines
- 38 Package Insertion Specifications
- 38 Processor Mass Specification
- 38 Processor Materials
- 38 Processor Markings
- 39 Processor Land Coordinates
- 41 Land Listing and Signal Descriptions
- 41 Processor Land Assignments
- 64 Alphabetical Signals Reference
- 75 Thermal Specifications and Design Considerations
- 75 Processor Thermal Specifications
- 75 Thermal Specifications
- 78 Thermal Metrology
- 78 Processor Thermal Features
- 78 Thermal Monitor
- 80 On-Demand Mode
- 81 PROCHOT# Signal
- 81 THERMTRIP# Signal
- 82 Platform Environment Control Interface (PECI)
- 82 Introduction
- 82 TCONTROL and TCC activation on PECI-Based Systems
- 83 PECI Specifications
- 83 PECI Device Address
- 83 PECI Command Support
- 83 PECI Fault Handling Requirements
- 83 PECI GetTemp0() Error Code Support
- 85 Features
- 85 Power-On Configuration Options
- 85 Clock Control and Low Power States
- 86 Normal State
- 86 HALT and Extended HALT Powerdown States
- 86 HALT Powerdown State
- 87 Extended HALT Powerdown State
- 87 Stop Grant and Extended Stop Grant States
- 87 Stop-Grant State
- 88 Extended Stop Grant State
- 88 Stop Grant Snoop State, and Stop Grant Snoop State
- 88 HALT Snoop State, Stop Grant Snoop State
- 88 Extended HALT Snoop State, Extended Stop Grant Snoop State
- 88 Sleep State
- 89 Deep Sleep State
- 89 Deeper Sleep State
- 90 Technology
- 90 Processor Power Status Indicator (PSI) Signal
- 91 Boxed Processor Specifications
- 91 Introduction
- 92 Mechanical Specifications
- 92 Boxed Processor Cooling Solution Dimensions
- 93 Boxed Processor Fan Heatsink Weight
- 93 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly
- 93 Electrical Requirements
- 93 Fan Heatsink Power Supply
- 95 Thermal Specifications
- 95 Boxed Processor Cooling Requirements
- 97 Variable Speed Fan
- 99 Debug Tools Specifications
- 99 Logic Analyzer Interface (LAI)
- 99 Mechanical Considerations
- 99 Electrical Considerations