Clock Specifications. Intel AT80571RG0601ML, AT80571RG0561ML

Electrical Specifications

Table 14.

2.8

2.8.1

GTL+ Bus Voltage Definitions

Symbol

GTLREF_PU

GTLREF_PD

R

TT

COMP[3:0]

COMP8

Parameter

GTLREF pull up on Intel ®

3 Series Chipset family boards

GTLREF pull down on

Intel ® 3 Series Chipset family boards

Termination Resistance

COMP Resistance

COMP Resistance

Min

57.6 * 0.99

100 * 0.99

45

49.40

24.65

Typ

57.6

100

Max

57.6 * 1.01

100 * 1.01

Units Notes 1

Ω

Ω

2

2

50

49.90

24.90

55

50.40

25.15

Ω

Ω

Ω

3

4

4

NOTES:

1.

2.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

GTLREF is to be generated from V

TT

by a voltage divider of 1% resistors. If an Adjustable

GTLREF circuit is used on the board (for Quad-Core processors compatibility) the two

3.

4.

GTLREF lands connected to the Adjustable GTLREF circuit require the following:

GTLREF_PU = 50 Ω, GTLREF_PD = 100 Ω.

R

TT

is the on-die termination resistance measured at V

TT

/3 of the GTL+ output driver.

COMP resistance must be provided on the system board with 1% resistors. COMP[3:0] and

COMP8 resistors are to V

SS

.

Clock Specifications

Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous generation processors, the processor’s core frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its default ratio during manufacturing. The processor supports Half Ratios between 7.5 and 13.5, refer to

Table 15 for the processor supported ratios.

The processor uses a differential clocking implementation. For more information on the processor clocking, contact your Intel field representative.

Datasheet 27