- Computers & electronics
- Computer components
- System components
- Processors
- Intel
- AT80571RG0601ML
- Data Sheet
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Electrical Specifications
Figure 2.
V
CC
Overshoot Example Waveform
Example Overshoot Waveform
V
OS
VID + 0.050
VID - 0.000
2.6.4
2.7
0 5
T
OS
10
Time [us]
15
T
OS
: Overshoot time above VID
V
OS
: Overshoot above VID
20 25
NOTES:
1.
2.
V
OS
T
OS
is measured overshoot voltage.
is measured time duration above VID.
Die Voltage Validation
Overshoot events on processor must meet the specifications in
across the VCC_SENSE and VSS_SENSE lands. Overshoot events that are < 10 ns in duration may be ignored. These measurements of processor die level overshoot must be taken with a bandwidth limited oscilloscope set to a greater than or equal to 100
MHz bandwidth limit.
Signaling Specifications
Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling technology. This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates.
Platforms implement a termination voltage level for GTL+ signals defined as V
TT
. Because platforms implement separate power planes for each processor (and chipset), separate V
CC
and V
TT supplies are necessary. This configuration allows for improved noise tolerance as processor frequency increases. Speed enhancements to data and address busses have caused signal integrity considerations and platform design methods to become even more critical than with previous processor families.
The GTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the
motherboard (see Table 14 for GTLREF specifications). Termination resistors (R
GTL+ signals are provided on the processor silicon and are terminated to V
TT
TT
) for
. Intel chipsets will also provide on-die termination, thus eliminating the need to terminate the bus on the motherboard for most GTL+ signals.
Datasheet 21
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Key Features
- IntelĀ® CeleronĀ® E3200 2.4 GHz
- 1 MB L2 LGA 775 (Socket T)
- Processor cores: 2 45 nm 64-bit 65 W
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Table of contents
- 9 Introduction
- 9 Terminology
- 10 Processor Terminology Definitions
- 11 References
- 13 Electrical Specifications
- 13 Power and Ground Lands
- 13 Decoupling Guidelines
- 13 VCC Decoupling
- 13 VTT Decoupling
- 14 FSB Decoupling
- 14 Voltage Identification
- 16 Reserved, Unused, and TESTHI Signals
- 16 Power Segment Identifier (PSID)
- 17 Voltage and Current Specification
- 17 Absolute Maximum and Minimum Ratings
- 18 DC Voltage and Current Specification
- 20 VCC Overshoot
- 21 Die Voltage Validation
- 21 Signaling Specifications
- 22 FSB Signal Groups
- 23 CMOS and Open Drain Signals
- 24 Processor DC Specifications
- 25 Platform Environment Control Interface (PECI) DC Specifications
- 26 GTL+ Front Side Bus Specifications
- 27 Clock Specifications
- 27 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking
- 28 FSB Frequency Select Signals (BSEL[2:0])
- 29 Phase Lock Loop (PLL) and Filter
- 29 BCLK[1:0] Specifications
- 33 Package Mechanical Specifications
- 33 Package Mechanical Drawing
- 37 Processor Component Keep-Out Zones
- 37 Package Loading Specifications
- 37 Package Handling Guidelines
- 38 Package Insertion Specifications
- 38 Processor Mass Specification
- 38 Processor Materials
- 38 Processor Markings
- 39 Processor Land Coordinates
- 41 Land Listing and Signal Descriptions
- 41 Processor Land Assignments
- 64 Alphabetical Signals Reference
- 75 Thermal Specifications and Design Considerations
- 75 Processor Thermal Specifications
- 75 Thermal Specifications
- 78 Thermal Metrology
- 78 Processor Thermal Features
- 78 Thermal Monitor
- 80 On-Demand Mode
- 81 PROCHOT# Signal
- 81 THERMTRIP# Signal
- 82 Platform Environment Control Interface (PECI)
- 82 Introduction
- 82 TCONTROL and TCC activation on PECI-Based Systems
- 83 PECI Specifications
- 83 PECI Device Address
- 83 PECI Command Support
- 83 PECI Fault Handling Requirements
- 83 PECI GetTemp0() Error Code Support
- 85 Features
- 85 Power-On Configuration Options
- 85 Clock Control and Low Power States
- 86 Normal State
- 86 HALT and Extended HALT Powerdown States
- 86 HALT Powerdown State
- 87 Extended HALT Powerdown State
- 87 Stop Grant and Extended Stop Grant States
- 87 Stop-Grant State
- 88 Extended Stop Grant State
- 88 Stop Grant Snoop State, and Stop Grant Snoop State
- 88 HALT Snoop State, Stop Grant Snoop State
- 88 Extended HALT Snoop State, Extended Stop Grant Snoop State
- 88 Sleep State
- 89 Deep Sleep State
- 89 Deeper Sleep State
- 90 Technology
- 90 Processor Power Status Indicator (PSI) Signal
- 91 Boxed Processor Specifications
- 91 Introduction
- 92 Mechanical Specifications
- 92 Boxed Processor Cooling Solution Dimensions
- 93 Boxed Processor Fan Heatsink Weight
- 93 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly
- 93 Electrical Requirements
- 93 Fan Heatsink Power Supply
- 95 Thermal Specifications
- 95 Boxed Processor Cooling Requirements
- 97 Variable Speed Fan
- 99 Debug Tools Specifications
- 99 Logic Analyzer Interface (LAI)
- 99 Mechanical Considerations
- 99 Electrical Considerations