RM0349 Device configuration
Table 34. SMPU_0 logical bus master assignments
SMPU logical bus master number Bus master
0
1
2
CPU
DMA
CPU Debug
On this device, the SMPU (SMPU_0) is attached to the slave side of XBAR_0.
The SMPU port allocation is shown in Table 35
.
Slave port number
0
1
2
3
4
Table 35. SMPU port allocation
IP
Flash controller port 0
Flash controller port 1
RAM controller
PBRIDGE_0
PBRIDGE_1
7.3.3.1.2 Number of region descriptors supported by SMPU_0
This instance of the SMPU module supports up to eight region descriptors.
7.3.3.1.3 RGD_WORD2 formats supported by SMPU_0
For RGD_WORD2, this instance of the SMPU module supports only the FMT0 format. The
RGD_WORD3[FMT] field is read-only with a fixed value of 0 and only RGD_WORD2_FMT0 applies.
7.3.3.1.4 Master Access permissions for SMPU_0
The only master allowed to access the SMPU_0 registers is Core_0. It is also required that the core be in supervisor mode.
This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
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