Dual PLL Digital Interface (PLLDIG) RM0349
As an example, suppose the following configuration:
• Input frequency: 40 MHz
• Loop divider (PLL n CR[MFD]): 20
• Input divider: 1
• Output divider RFD: 5
• VCO frequency: 40 MHz × 20 = 800 MHz
• PLL output frequency: 800 MHz / 2*RFD = 800 MHz / 10 = 80 MHz
• Center spread (PLL1FM[MODSEL] = 0)
• Modulation frequency: 200 kHz
• Modulation depth: ± 1.9% (3.8% peak-to-peak)
• PLL1FM[MODPRD] = Round[(40 × 10 6 ) / (4 × 200 × 10 3 )] = Round[50] = 50
• PLL1FM[INCSTP] = Round[((2
15 − 1) × 1.9× 20) / (100 × 5 × 50)] = Round[49.8] = 50
• PLL1FM[MODPRD] × PLL1FM[INCSTP] = 50 × 50 = 2500 (which is less than 2 15 )
• MD (quantized) = ((50 × 50 × 100 × 5) / ((2
15 − 1) × 20) = 1.90740%
In this example, the modulation error is 0.00740%.
The FM parameters do not get reset when PLL0 looses its lock. These parameters get reset on destructive reset. Whenever PLL0 gets relocked FM modulation starts with the previous values.
The sequence for reprogramming the FM is:
1.
Power down PLL1 (l)
2. Program the PLL1FM while PLL1 is powered down
PLL1 (m)
Coming out of reset PLL0 and PLL1 are enabled. The recommended procedure to program the PLLs and enter normal mode is:
1.
Program PLL0DV[PREDIV], PLL0DV[RFDPHI1], PLL0DV[MFD] and
PLL0DV[RFDPHI].
2. Power up PLL0 (controlled by configuring the appropriate MC_ME_ <mode> _MC register).
3. Poll PLL0SR[LOCK] until it asserts.
5. If required, program the PLL1FM register with the desired frequency modulation parameters and enable FM modulation, PLL1FM[MODEN] = 1. The PLL1FM register must not be written after PLL1 is enabled and operating in normal mode.
6. Power up PLL1 (controlled by configuring the appropriate MC_ME_ <mode> _MC register).
7. Poll PLL1SR[LOCK] until it asserts.
492/1658 l.
By writing MC_ME_< mode >_MC[PLL1ON] = 0b.
m. By writing MC_ME_< mode >_MC[PLL1ON] = 1b.
DocID024507 Rev 6
RM0349 Dual PLL Digital Interface (PLLDIG)
At this point, the PLL is configured and is generating a output clock; however, the PLL is not the system clock until it is configured in the Mode Entry Module (MC_ME) and a mode
change has taken place. See Chapter 48: Mode Entry Module (MC_ME)
for more details.
DocID024507 Rev 6 493/1658
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