Interrupt Controller (INTC)
18.7 Initialization/application information
RM0349
After exiting reset, all of the PRI n and PRC_SEL n fields in INTC_PSR n are zero, and PRI in the INTC_CPR0 registers is 31. These reset values will prevent the INTC from asserting the interrupt request to the processor. The enable or mask bits in the peripherals are reset such that the peripheral interrupt requests are negated. An initialization sequence for allowing the peripheral and software-settable interrupt requests to cause an interrupt request to the processor is:
• Interrupt_request_initialization:
– Configure HVEN0 in INTC_BCR.
– Configure VTBA in INTC_IACKR0 .
– Raise the PRI n fields and set the PRC_SEL n fields to the desired processor in
INTC_PSR n .
– Set the enable bits or clear the mask bits for the peripheral interrupt requests.
– Lower PRI in INTC_CPR0 to zero.
– Enable processor recognition of interrupts.
These example interrupt exception handlers excerpts use Power Architecture assembly code.
18.7.2.1 Software vector mode
In software vector mode for Power Architecture, there are 16 bytes of vector space available at the single ISR entry point.
interrupt_exception_handler: b interrupt_exception_handler_continued
# 16 bytes available, branch to continue interrupt_exception_handler_continued: code to create stack frame, save working register, and save SRR0 and SRR1
(Power Architecture Save/Restore registers) (not shown) lis lwz r3,INTC_IACKR0@ha # form adjusted upper half of INTC_IACKR0
# address r3,INTC_IACKR0@l(r3) # load INTC_IACKR0, which clears request to
# processor lwz r3,0x0(r3) wrteei 1
# load address of ISR from vector table
# enable processor recognition of interrupts code to save rest of context required by Power Architecture EABI (Embedded
Binary Application Interface) (not shown) mtlr blrl r3 # move the INTC_IACKR0 address into the link register
# branch to ISR; link register updated with epilog
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