Initialization/Application information. STMicroelectronics SPC570S40E3, SPC570Sx 32-bit Power Architecture® microcontroller, SPC570S40E1, SPC570S50E1, SPC570S50E3

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RM0349 DMA channel multiplexer (DMACHMUX) can either be a new software activation, or a transfer request from the DMACHMUX. The options for doing this are:

• Transfer all data in a single minor loop. By configuring the DMA to transfer all of the data in a single minor loop (i.e., major loop counter = 1), no reactivation of the channel is necessary. The disadvantage to this option is the reduced granularity in determining the load that the DMA transfer will incur on the system. For this option, the DMA channel should be disabled in the DMACHMUX.

• Use explicit software reactivation. In this option, the DMA is configured to transfer the data using both minor and major loops, but the processor is required to reactivate the channel (by writing to the DMA registers) after every minor loop . For this option, the

DMA channel should be disabled in the DMACHMUX.

• Use a “always enabled” DMA source. In this option, the DMA is configured to transfer the data using both minor and major loops, and the DMACHMUX does the channel reactivation. For this option, the DMA channel should be enabled and pointing to an

“always enabled” source. Note that the reactivation of the channel can be continuous

(DMA triggering is disabled) or can use the DMA triggering capability. In this manner, it is possible to execute periodic transfers of packets of data from one source to another, without processor intervention.

20.5 Initialization/Application information

20.5.1 Reset

The reset state of each individual bit is shown within the Register Description section (See

Section 20.3.1: Register descriptions

). In summary, after reset, all channels are disabled and must be explicitly enabled before use.

Note:

To enable a source with periodic triggering:

Determine with which DMA channel the source will be associated. Note that only the first 2 DMA channels have periodic triggering capability.

2. Clear the CHCFG[ENBL] and CHCFG[TRIG] fields of the DMA channel.

3. Ensure that the DMA channel is properly configured in the DMA. The DMA channel may be enabled at this point.

4. Configure the corresponding timer.

5. Select the source to be routed to the DMA channel. Write to the corresponding CHCFG register, ensuring that the CHCFG[ENBL] and CHCFG[TRIG] fields are set.

The following is an example. See the chip configuration details for the number of this device’s DMA channels that have triggering capability.

Example 1 Configure source #5 Transmit for use with DMA Channel 2, with periodic triggering capability

Write 0x00 to CHCFG2 (Base Address + 0x02)

2. Configure Channel 2 in the DMA, including enabling the channel

3. Configure a timer for the desired trigger interval

4. Write 0xC5 to CHCFG2 (Base Address + 0x02)

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DMA channel multiplexer (DMACHMUX)

The following code example illustrates steps #1 and #4 above:

In file registers.h:

#define DMAMUX_BASE_ADDR 0xFC084000/* Example only ! */

/* Following example assumes char is 8-bits */ volatile unsigned char *CHCFG0 = (volatile unsigned char *)

(DMAMUX_BASE_ADDR+0x0000); volatile unsigned char *CHCFG1 = (volatile unsigned char *)

(DMAMUX_BASE_ADDR+0x0001); volatile unsigned char *CHCFG2 = (volatile unsigned char *)

(DMAMUX_BASE_ADDR+0x0002); volatile unsigned char *CHCFG3 = (volatile unsigned char *)

(DMAMUX_BASE_ADDR+0x0003); volatile unsigned char *CHCFG4 = (volatile unsigned char *)

(DMAMUX_BASE_ADDR+0x0004); volatile unsigned char *CHCFG5 = (volatile unsigned char *)

(DMAMUX_BASE_ADDR+0x0005); volatile unsigned char *CHCFG6 = (volatile unsigned char *)

(DMAMUX_BASE_ADDR+0x0006); volatile unsigned char *CHCFG7 = (volatile unsigned char *)

(DMAMUX_BASE_ADDR+0x0007); volatile unsigned char *CHCFG8 = (volatile unsigned char *)

(DMAMUX_BASE_ADDR+0x0008); volatile unsigned char *CHCFG9 = (volatile unsigned char *)

(DMAMUX_BASE_ADDR+0x0009); volatile unsigned char *CHCFG10= (volatile unsigned char *)

(DMAMUX_BASE_ADDR+0x000A); volatile unsigned char *CHCFG11= (volatile unsigned char *)

(DMAMUX_BASE_ADDR+0x000B); volatile unsigned char *CHCFG12= (volatile unsigned char *)

(DMAMUX_BASE_ADDR+0x000C); volatile unsigned char *CHCFG13= (volatile unsigned char *)

(DMAMUX_BASE_ADDR+0x000D); volatile unsigned char *CHCFG14= (volatile unsigned char *)

(DMAMUX_BASE_ADDR+0x000E); volatile unsigned char *CHCFG15= (volatile unsigned char *)

(DMAMUX_BASE_ADDR+0x000F);

In File main.c:

#include "registers.h"

*CHCFG2 = 0x00;

*CHCFG2 = 0xC5;

RM0349

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RM0349

Note:

DMA channel multiplexer (DMACHMUX)

To enable a source without periodic triggering:

Determine with which DMA channel the source will be associated. Note that only the first 4 DMA channels have periodic triggering capability.

2. Clear the CHCFG[ENBL] and CHCFG[TRIG] fields of the DMA channel.

3. Ensure that the DMA channel is properly configured in the DMA. The DMA channel may be enabled at this point.

4. Select the source to be routed to the DMA channel. Write to the corresponding CHCFG register, ensuring that CHCFG[ENBL] is set while CHCFG[TRIG] is cleared.

The following is an example. See the chip configuration details for the number of this device's DMA channels that have triggering capability.

Example 2 Configure source #5 Transmit for use with DMA Channel 2, with no periodic triggering capability.

Write 0x00 to CHCFG2 (Base Address + 0x02)

2. Configure Channel 2 in the DMA, including enabling the channel

3. Write 0x85 to CHCFG2 (Base Address + 0x02)

The following code example illustrates steps #1 and #3 above:

In File registers.h: