Device configuration
Table 61. SSCM startup information addresses
Description
The location at which the SSCM will look for the UTEST DCF records
(UTEST_OFFSET)
Location of the Boot Assist code in Flash (BAF)
RM0349
Value
0040_0000h
0040_4000h
7.9.3
The SSCM registers are protected by a register protection module. After software has activated the protection for a register, writes can only be performed in supervisor mode until the protection is either deactivated by software or the device undergoes reset.
See the Register Protection chapter (
Chapter 62: Register Protection (REG_PROT)
) for a detailed description of the register protection mechanism.
Self-Test Control Unit (STCU2) configuration
Offline selftest is supported to work in the following configurations:
• no BIST (default)
• STCU bypass
• offline sequential LBIST
• offline parallel MBIST
• offline sequential LBIST + offline parallel MBIST
For LBIST run, RC clock (16 MHz) is to be used and for MBIST run, PLL clock (80MHz) is to be used.
Other BIST configurations are not supported.
7.10.1 CRC – Number of contexts
Table 62 lists the number of contexts available for the current CRC computation of multiple
data streams of CRC.
Signal name
Table 62. CRC contexts
Description
CRC_CNTX_NUM (N) Number of contexts available for the current CRC computation of multiple data streams: 1
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