RM0349 Wakeup unit (WKPU)
Non-maskable Interrupt support with
• up to 4 NMI sources
• up to 4 analog glitch filters
• independent CPU exceptions destination: non-maskable interrupt, critical interrupt, or machine check request
• edge detection
• configurable system wakeup triggering from all NMI sources
21.2 Memory Map and Register Description
This section provides a detailed description of all registers accessible in the WKPU module.
Table 219
gives an overview on the WKPU registers implemented.
Table 219. WKPU Memory Map
Address Offset Registers
Supported
Access
Sizes
32/16/8 0x0000
0x0004 - 0x0007
0x0008
0x000C - 0x03FF
NMI Status Flag Register (NSR)
Reserved
NMI Configuration Register (NCR)
Reserved
32/16/8
Location
Section 21.2.2.1
Section 21.2.2.2
Note: Reserved registers will read as 0, writes will have no effect. If supported and enabled by the
SoC, a transfer error will be issued when trying to access completely reserved register space.
This section describes in address order all the Wakeup unit registers.
21.2.2.1 NMI Status Flag Register (NSR)
This register holds the non-maskable interrupt status flags.
Offset: 0x0000 Access: User read/write (write 1 to clear)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 155. NMI Status Flag Register (NSR)
DocID024507 Rev 6 455/1658
460
Wakeup unit (WKPU) RM0349
Field
0
NIF0
1
NOVF0
8
NIF1
9
NOVF1
16
NIF2
17
NOVF2
Table 220. NSR Field Descriptions
Description
NMI Status Flag 0. This flag can be cleared only by writing a 1. Writing a 0 has no effect. If enabled (NREE0 or NFEE0 set), NIF0 causes an exception to the associated
CPU, as configured within the NDSS bit of the NCR register. In addition this event can also be configured to trigger a system wakeup.
1 An event as defined by NREE0 and NFEE0 has occurred
0 No event has occurred on the pad
NMI Overrun Status Flag 0. This flag can be cleared only by writing a 1. Writing a 0 has no effect. It will be a copy of the current NIF0 value whenever a NMI event occurs, thereby indicating to the software that a NMI occurred while the last one was not yet serviced. If enabled (NREE0 or NFEE0 set), NOVF0 causes an interrupt request.
1 An overrun has occurred on NMI input 0
0 No overrun has occurred on NMI input 0
NMI Status Flag 1. This flag can be cleared only by writing a 1. Writing a 0 has no effect. If enabled (NREE1 or NFEE1 set), NIF1 causes an exception to the associated
CPU, as configured within the NDSS bit of the NCR register. In addition this event can also be configured to trigger a system wakeup.
1 An event as defined by NREE1 and NFEE1 has occurred
0 No event has occurred on the pad
NMI Overrun Status Flag 1. This flag can be cleared only by writing a 1. Writing a 0 has no effect. It will be a copy of the current NIF1 value whenever a NMI event occurs, thereby indicating to the software that a NMI occurred while the last one was not yet serviced. If enabled (NREE1 or NFEE1 set), NOVF1 causes an interrupt request.
1 An overrun has occurred on NMI input 1
0 No overrun has occurred on NMI input 1
NMI Status Flag 2. This flag can be cleared only by writing a 1. Writing a 0 has no effect. If enabled (NREE2 or NFEE2 set), NIF2 causes an exception to the associated
CPU, as configured within the NDSS bit of the NCR register. In addition this event can also be configured to trigger a system wakeup.
1 An event as defined by NREE2 and NFEE2 has occurred
0 No event has occurred on the pad
NMI Overrun Status Flag 2. This flag can be cleared only by writing a 1. Writing a 0 has no effect. It will be a copy of the current NIF2 value whenever a NMI event occurs, thereby indicating to the software that a NMI occurred while the last one was not yet serviced. If enabled (NREE2 or NFEE2 set), NOVF2 causes an interrupt request.
1 An overrun has occurred on NMI input 2
0 No overrun has occurred on NMI input 2
456/1658 DocID024507 Rev 6
RM0349 Wakeup unit (WKPU)
Field
24
RIF
25
ROVF
Table 220. NSR Field Descriptions(Continued)
Description
Reset status Flag
This flag can be cleared only by writing a 1. Writing a 0 has no effect. If enabled (i.e., if
RREE or RFEE is set), RIF status bit is set and will cause a functional reset request to RGM if RDSS[1:0] of NCR is
‘00’. This bit is automatically cleared if the F_WAKEUP reset request is configured in the
MC_RGM to generate a long or short “functional” reset.
1 An event as defined by RREE and RFEE has occurred
0 No event has occurred on the pad
Reset overrun status flag
This flag can be cleared only by writing a 1. Writing a 0 has no effect. It will be a copy of the current
RIF value whenever a NMI event occurs, thereby indicating to the software that an NMI occurred while the last one was not yet serviced. If enabled (RREE or RFEE set),
ROVF can cause a reset request to MC_RGM if RDSS[1:0] of NCR is ‘00’. This bit is automatically cleared if the F_WAKEUP reset request is configured in the MC_RGM to generate a long or short “functional” reset.
1 An overrun has occurred on NMI input
0 No overrun has occurred on NMI input
Note: Refer to the device configuration chapter to see how the
NMI Status Flag Register (NSR) is
used in the device.
21.2.2.2 NMI Configuration Register (NCR)
This register holds the configuration bits for the non-maskable interrupt settings.
Offset: 0x0008 Access: User read/write
R
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 0 1 0 2 0
E 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0
0
(1)
Figure 156. NMI Configuration Register (NCR)
1. Writing this bit has no functional impact.
DocID024507 Rev 6 457/1658
460
Wakeup unit (WKPU) RM0349
Field
0
NLOCK0
1:2
NDSS0
3
NWRE0
5
NREE0
6
NFEE0
7
NFE0
8
NLOCK1
9:10
NDSS1
11
NWRE1
13
NREE1
14
NFEE1
15
NFE1
16
NLOCK2
Table 221. NCR Field Descriptions
Description
NMI Configuration Lock Register 0. Writing a 1 to this bit locks the configuration for the
NMI until it is unlocked by a system reset. Writing a 0 has no effect.
NMI Destination Source Select 0. This value is reset on system reset.
00 non-maskable interrupt
01 critical interrupt
10 machine check request
11 reset request
NMI Wakeup Request Enable 0.
1 A set NIF0 bit or set NOVF0 bit causes a system wakeup request
0 System wakeup requests from the corresponding NIF0 bit are disabled
NMI Rising-edge Events Enable 0.
1 Rising-edge event is enabled
0 Rising-edge event is disabled
NMI Falling-edge Events Enable 0.
1 Falling-edge event is enabled
0 Falling-edge event is disabled
NMI Filter Enable 0.
Enable analog glitch filter on the NMI pad input.
1 Filter is enabled
0 Filter is disabled
NMI Configuration Lock Register 1. Writing a 1 to this bit locks the configuration for the
NMI until it is unlocked by a system reset. Writing a 0 has no effect.
NMI Destination Source Select 1. This value is reset on system reset.
00 non-maskable interrupt
01 critical interrupt
10 machine check request
11 reset request
NMI Wakeup Request Enable 1.
1 A set NIF1 bit or set NOVF1 bit causes a system wakeup request
0 System wakeup requests from the corresponding NIF1 bit are disabled
NMI Rising-edge Events Enable 1.
1 Rising-edge event is enabled
0 Rising-edge event is disabled
NMI Falling-edge Events Enable 1.
1 Falling-edge event is enabled
0 Falling-edge event is disabled
NMI Filter Enable 1.
Enable analog glitch filter on the NMI pad input.
1 Filter is enabled
0 Filter is disabled
NMI Configuration Lock Register 2. Writing a 1 to this bit locks the configuration for the
NMI until it is unlocked by a system reset. Writing a 0 has no effect.
458/1658 DocID024507 Rev 6
RM0349
Note:
Note:
Wakeup unit (WKPU)
Field
17:18
NDSS2
19
NWRE2
21
NREE2
22
NFEE2
23
NFE2
24
RLOCK
25:26
RDSS
27
RWRE
29
RREE
30
RFEE
31
RFE
Table 221. NCR Field Descriptions(Continued)
Description
NMI Destination Source Select 2. This value is reset on system reset.
00 non-maskable interrupt
01 critical interrupt
10 machine check request
11 reset request
NMI Wakeup Request Enable 2.
1 A set NIF2 bit or set NOVF2 bit causes a system wakeup request
0 System wakeup requests from the corresponding NIF2 bit are disabled
NMI Rising-edge Events Enable 2.
1 Rising-edge event is enabled
0 Rising-edge event is disabled
NMI Falling-edge Events Enable 2.
1 Falling-edge event is enabled
0 Falling-edge event is disabled
NMI Filter Enable 2.
Enable analog glitch filter on the NMI pad input.
1 Filter is enabled
0 Filter is disabled
Reset Configuration Lock Register. Writing a 1 to this bit locks the configuration for the reset until it is unlocked by a system reset. Writing a 0 has no effect.
Reset Destination Source Select. This value is reset on system reset.
00 Reset request to RGM
01 No reaction
10 No reaction
11 No reaction
Reset Wakeup Request Enable.
1 A set RIF bit or set ROVF bit causes a system wakeup request
0 System wakeup requests from the corresponding RIF bit are disabled
Reset Rising-edge Events Enable.
1 Rising-edge event is enabled
0 Rising-edge event is disabled
Reset Falling-edge Events Enable.
1 Falling-edge event is enabled
0 Falling-edge event is disabled
Reset Filter Enable.
Enable analog glitch filter on the NMI pad input.
1 Filter is enabled
0 Filter is disabled
Refer to the device configuration chapter to see how the
NMI Configuration Register (NCR)
is used in the device.
Writing a ‘0’ to both NREEx and NFEEx disables the NMI functionality completely (no system wakeup or interrupt will be generated on any pad activity)!
DocID024507 Rev 6 459/1658
460
