Memory map and register definitions. STMicroelectronics SPC570S40E3, SPC570Sx 32-bit Power Architecture® microcontroller, SPC570S40E1, SPC570S50E1, SPC570S50E3

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Flash memory controller (PFLASH Controller) RM0349

Figure 231. Platform-centric block diagram with flash memory controller e200zX

Core0 m0 m1

AMBA-AHB s0

AXBS s1

PFlash

P1 s2 System

RAM

Flash

Memory

30.4 Memory map and register definitions

30.4.1 Overview

The flash memory controller module provides an IPS programming model mapped to a standard 16 KB on-platform peripheral slot. The programming model consists of flash access configuration .

The programming model can only be referenced using a 32-bit (word) access. Attempted references using different access sizes or to undefined (reserved) addresses or in user mode generates an IPS error termination. The flash controller allows access to the programming model by all system bus masters.

The programming model can only be accessed in supervisor mode.

Attempted updates to the programming model while the flash memory controller module is in the middle of an operation results in non-deterministic behavior.

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Table 293. Flash memory controller memory map

Address offset

Register

0x000

0x004

0x008

0x00C

0x010–0x017

0x018–0x0FF

(0x100 + n *0xF)–

(0x10B + n *0xF)

( n =0 to 31)

(0x10C + n *0xF)–

(0x10F + n *0xF)

( n =0 to 31)

0x300–0x3FFF

Platform Flash Configuration Register 1 (PFCR1)

Platform Flash Configuration Register 2 (PFCR2)

Platform Flash Configuration Register 3 (PFCR3)

Platform Flash Access Protection Register (PFAPR)

Reserved

(1)

1. Access to this address space will not terminate in an error.

2. Access to this address space will terminate in an error.

Reserved

(2)

Location

30.4.1.1 Platform Flash Configuration Register 1 (PFCR1)

The PFlash Configuration Register 1 (PFCR1) is used to specify operation Port p0 of the flash memory controller.

Offset: 0x000

1 2 3 4 5 6 7 8 9 10

Access: Supervisor Read/Write

11 12 13 14 15

Reset 0

R 0

RWSC

P0_PFLIM

Reset 0 0 0 0 0 1 1 0 0 0 0 0 0

Figure 232. Platform Flash Configuration Register 1 (PFCR1)

0 0 1

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Field

P0_M15PFE

P0_M14PFE

P0_M13PFE

P0_M12PFE

P0_M11PFE

P0_M10PFE

P0_M9PFE

P0_M8PFE

P0_M7PFE

P0_M6PFE

P0_M5PFE

Table 294. PFCR1 field descriptions

Description

Port0 Master 15 Prefetch enable. This bit controls whether prefetching may be triggered by AHB master 15. This bit is cleared by hardware reset.

0 No prefetching may be triggered by this master

1 Prefetching may be triggered by this master

Port0 Master 14 Prefetch enable. This bit controls whether prefetching may be triggered by AHB master 14. This bit is cleared by hardware reset.

0 No prefetching may be triggered by this master

1 Prefetching may be triggered by this master

Port0 Master 13 Prefetch enable. This bit controls whether prefetching may be triggered by AHB master 13. This bit is cleared by hardware reset.

0 No prefetching may be triggered by this master

1 Prefetching may be triggered by this master

Port0 Master 12 Prefetch enable. This bit controls whether prefetching may be triggered by AHB master 12. This bit is cleared by hardware reset.

0 No prefetching may be triggered by this master

1 Prefetching may be triggered by this master

Port0 Master 11 Prefetch enable. This bit controls whether prefetching may be triggered by AHB master 11. This bit is cleared by hardware reset.

0 No prefetching may be triggered by this master

1 Prefetching may be triggered by this master

Port0 Master 10 Prefetch enable. This bit controls whether prefetching may be triggered by AHB master 10. This bit is cleared by hardware reset.

0 No prefetching may be triggered by this master

1 Prefetching may be triggered by this master

Port0 Master 9 Prefetch enable. This bit controls whether prefetching may be triggered by AHB master 9. This bit is cleared by hardware reset.

0 No prefetching may be triggered by this master

1 Prefetching may be triggered by this master

Port0 Master 8 Prefetch enable. This bit controls whether prefetching may be triggered by AHB master 8. This bit is cleared by hardware reset.

0 No prefetching may be triggered by this master

1 Prefetching may be triggered by this master

Port0 Master 7 Prefetch enable. This bit controls whether prefetching may be triggered by AHB master 7. This bit is cleared by hardware reset.

0 No prefetching may be triggered by this master

1 Prefetching may be triggered by this master

Port0 Master 6 Prefetch enable. This bit controls whether prefetching may be triggered by AHB master 6. This bit is cleared by hardware reset.

0 No prefetching may be triggered by this master

1 Prefetching may be triggered by this master

Port0 Master 5 Prefetch enable. This bit controls whether prefetching may be triggered by AHB master 5. This bit is cleared by hardware reset.

0 No prefetching may be triggered by this master

1 Prefetching may be triggered by this master

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Field

P0_M4PFE

P0_M3PFE

P0_M2PFE

P0_M1PFE

P0_M0PFE

19:23

RWSC

P0_DPFEN

P0_IPFEN

Flash memory controller (PFLASH Controller)

Table 294. PFCR1 field descriptions(Continued)

Description

Port0 Master 4 Prefetch enable. This bit controls whether prefetching may be triggered by AHB master 4. This bit is cleared by hardware reset.

0 No prefetching may be triggered by this master

1 Prefetching may be triggered by this master

Port0 Master 3 Prefetch enable. This bit controls whether prefetching may be triggered by AHB master 3. This bit is cleared by hardware reset.

0 No prefetching may be triggered by this master

1 Prefetching may be triggered by this master

Port0 Master 2 Prefetch enable. This bit controls whether prefetching may be triggered by AHB master 2. This bit is cleared by hardware reset.

0 No prefetching may be triggered by this master

1 Prefetching may be triggered by this master

Port0 Master 1 Prefetch enable. This bit controls whether prefetching may be triggered by AHB master 1. This bit is cleared by hardware reset.

0 No prefetching may be triggered by this master

1 Prefetching may be triggered by this master

Port0 Master 0 Prefetch enable. This bit controls whether prefetching may be triggered by AHB master 0. This bit is cleared by hardware reset.

0 No prefetching may be triggered by this master

1 Prefetching may be triggered by this master

Read Wait State Control.

This field controls the number of wait-states to be added to the best-case flash array access time for reads. The best-case flash array access time for reads is one cycle.

This field must be set to a value corresponding to the operating frequency of the flash memory controller and the actual read access time of the flash memory controller. The required settings are documented in the SoC specification.

Higher operating frequencies require non-zero settings for this field for proper flash operation.

This field applies to the configuration of Port0 and Port1.

00000 No additional wait-states are added

00001 One additional wait-state is added

...

11111 Thirty-one additional wait-states are added

Port0 Data Prefetch Enable. This field enables or disables prefetching initiated by a data read access. This field is cleared by hardware reset.

0 No prefetching is triggered by a data read access

1 Prefetching may be triggered by any data read access

Port0 Instruction Prefetch Enable. This bit enables or disables prefetching initiated by an instruction read access. This field is cleared by hardware reset.

0 No prefetching is triggered by an instruction read access

1 Prefetching may be triggered by any instruction read access

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Field

29:30

P0_PFLIM

P0_BFEN

RM0349

Table 294. PFCR1 field descriptions(Continued)

Description

Port0 PFlash Prefetch Limit. This field controls the prefetch algorithm used by the prefetch controller. This field defines a limit on the maximum number of sequential prefetches which will be attempted between buffer misses. In all situations when enabled, only a single prefetch is initiated on each buffer miss or hit.

This field is cleared by hardware reset.

00 No prefetching or buffering is performed.

01 The referenced line is prefetched on a buffer miss, that is, prefetch on miss.

10 The referenced line is prefetched on a buffer miss, or the next sequential line is prefetched on a buffer hit (if not already present), that is, prefetch on miss or hit.

11 The referenced line is prefetched on a buffer miss, or the next sequential line is prefetched on a buffer hit (if not already present), that is, prefetch on miss or hit.

Port0 PFlash Line Read Buffers Enable. This bit enables or disables line read buffer hits. It is also used to invalidate the buffers. This bit can only be updated while PFCR3[BAF_DIS] = 0. After execution of the boot code, as indicated by

PFCR3[BAF_DIS] = 1, this bit becomes read-only until the next hardware reset.

0 The line read buffers are disabled from satisfying read requests, and all buffer valid bits are cleared.

1 The line read buffers are enabled to satisfy read requests on hits. Buffer valid bits may be set when the buffers are successfully filled.

30.4.1.2 Platform Flash Configuration Register 2 (PFCR2)

The PFlash Configuration Register 2 (PFCR2) is used to specify operation Port1 of the flash memory controller.

Offset: 0x004

1 2 3 4 5 6 7 8 9 10

Access: Supervisor Read/Write

11 12 13 14 15

Reset 0

R 0

P1_PFLIM

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 233. Platform Flash Configuration Register 2 (PFCR2)

0 0 1

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Field

P1_M15PFE

P1_M14PFE

P1_M13PFE

P1_M12PFE

P1_M11PFE

P1_M10PFE

P1_M9PFE

P1_M8PFE

P1_M7PFE

P1_M6PFE

P1_M5PFE

Table 295. PFCR2 field descriptions

Description

Port1 Master 15 Prefetch enable. This bit controls whether prefetching may be triggered by AHB master 15. This bit is cleared by hardware reset.

0 No prefetching may be triggered by this master

1 Prefetching may be triggered by this master

Port1 Master 14 Prefetch enable. This bit controls whether prefetching may be triggered by AHB master 14. This bit is cleared by hardware reset.

0 No prefetching may be triggered by this master

1 Prefetching may be triggered by this master

Port1 Master 13 Prefetch enable. This bit controls whether prefetching may be triggered by AHB master 13. This bit is cleared by hardware reset.

0 No prefetching may be triggered by this master

1 Prefetching may be triggered by this master

Port1 Master 12 Prefetch enable. This bit controls whether prefetching may be triggered by AHB master 12. This bit is cleared by hardware reset.

0 No prefetching may be triggered by this master

1 Prefetching may be triggered by this master

Port1 Master 11 Prefetch enable. This bit controls whether prefetching may be triggered by AHB master 11. This bit is cleared by hardware reset.

0 No prefetching may be triggered by this master

1 Prefetching may be triggered by this master

Port1 Master 10 Prefetch enable. This bit controls whether prefetching may be triggered by AHB master 10. This bit is cleared by hardware reset.

0 No prefetching may be triggered by this master

1 Prefetching may be triggered by this master

Port1 Master 9 Prefetch enable. This bit controls whether prefetching may be triggered by AHB master 9. This bit is cleared by hardware reset.

0 No prefetching may be triggered by this master

1 Prefetching may be triggered by this master

Port1 Master 8 Prefetch enable. This bit controls whether prefetching may be triggered by AHB master 8. This bit is cleared by hardware reset.

0 No prefetching may be triggered by this master

1 Prefetching may be triggered by this master

Port1 Master 7 Prefetch enable. This bit controls whether prefetching may be triggered by AHB master 7. This bit is cleared by hardware reset.

0 No prefetching may be triggered by this master

1 Prefetching may be triggered by this master

Port1 Master 6 Prefetch enable. This bit controls whether prefetching may be triggered by AHB master 6. This bit is cleared by hardware reset.

0 No prefetching may be triggered by this master

1 Prefetching may be triggered by this master

Port1 Master 5 Prefetch enable. This bit controls whether prefetching may be triggered by AHB master 5. This bit is cleared by hardware reset.

0 No prefetching may be triggered by this master

1 Prefetching may be triggered by this master

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Field

P1_M4PFE

P1_M3PFE

P1_M2PFE

P1_M1PFE

P1_M0PFE

P1_DPFEN

P1_IPFEN

29:30

P1_PFLIM

P1_BFEN

RM0349

Table 295. PFCR2 field descriptions(Continued)

Description

Port1 Master 4 Prefetch enable. This bit controls whether prefetching may be triggered by AHB master 4. This bit is cleared by hardware reset.

0 No prefetching may be triggered by this master

1 Prefetching may be triggered by this master

Port1 Master 3 Prefetch enable. This bit controls whether prefetching may be triggered by AHB master 3. This bit is cleared by hardware reset.

0 No prefetching may be triggered by this master

1 Prefetching may be triggered by this master

Port1 Master 2 Prefetch enable. This bit controls whether prefetching may be triggered by AHB master 2. This bit is cleared by hardware reset.

0 No prefetching may be triggered by this master

1 Prefetching may be triggered by this master

Port1 Master 1 Prefetch enable. This bit controls whether prefetching may be triggered by AHB master 1. This bit is cleared by hardware reset.

0 No prefetching may be triggered by this master

1 Prefetching may be triggered by this master

Port1 Master 0 Prefetch enable. This bit controls whether prefetching may be triggered by AHB master 0. This bit is cleared by hardware reset.

0 No prefetching may be triggered by this master

1 Prefetching may be triggered by this master

Port1 Data Prefetch Enable. This field enables or disables prefetching initiated by a data read access. This field is cleared by hardware reset.

0 No prefetching is triggered by a data read access

1 Prefetching may be triggered by any data read access

Port1 Instruction Prefetch Enable. This bit enables or disables prefetching initiated by an instruction read access. This field is cleared by hardware reset.

0 No prefetching is triggered by an instruction read access

1 Prefetching may be triggered by any instruction read access

Port1 PFlash Prefetch Limit. This field controls the prefetch algorithm used by the prefetch controller. This field defines a limit on the maximum number of sequential prefetches which will be attempted between buffer misses. In all situations when enabled, only a single prefetch is initiated on each buffer miss or hit. This field is cleared by hardware reset.

00 No prefetching or buffering is performed.

01 The referenced line is prefetched on a buffer miss, that is, prefetch on miss.

1x The referenced line is prefetched on a buffer miss, or the next sequential line is prefetched on a buffer hit (if not already present), that is, prefetch on miss or hit.

Port1 PFlash Line Read Buffers Enable. This bit enables or disables line read buffer hits. It is also used to invalidate the buffers. This bit can only be updated while PFCR3[BAF_DIS]=0. After execution of the boot code, as indicated by

PFCR3[BAF_DIS] = 1, this bit becomes read-only until the next hardware reset.

0 The line read buffers are disabled from satisfying read requests, and all buffer valid bits are cleared.

1 The line read buffers are enabled to satisfy read requests on hits. Buffer valid bits may be set when the buffers are successfully filled.

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30.4.1.3 Platform Flash Configuration Register 3 (PFCR3)

Offset: 0x008

1 2 3

P0_WCFG P1_WCFG

Access: Supervisor Read/Write

11 12

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0

16 17

ARBM

Reset 0

0 0 0 0 0 0

This bit can be programmed but it has no functionality.

Figure 234. Platform Flash Configuration Register 3 (PFCR3)

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Field

0:1

P0_WCFG

2:3

P1_WCFG

RM0349

Table 296. PFCR3 field descriptions

Description

Port0 Way Configuration. This field controls the configuration of the line buffers for a given set across all four ways in the controller cache. The indexed set can be organized as a “pool” of available resources, or with a fixed partition between instruction and data buffers.

In all cases, when a buffer miss occurs, the flash page is assigned a location within the controller cache. Within the indexed set, the way is selected using a least-recently-used replacement policy, and the entry is then marked as mostrecently-used for that set. If the flash access is for the next-sequential line

(prefetch), the buffer is not marked as most-recently-used until the given address produces a buffer hit.

This field is initialized by hardware reset.

00 All four buffers in an indexed set are available for any flash access, that is, there is no partitioning of the buffers based on the access type.

01 Reserved

10 The buffers in an indexed set are partitioned into two groups with way 0 and

1 allocated for instruction fetches and way 2 and 3 for data accesses.

11 Reserved

Port1 Line Buffer Configuration. This field controls the configuration of the line buffers for a given set across all four ways in the controller cache. The indexed set can be organized as a “pool” of available resources, or with a fixed partition between instruction and data buffers.

(prefetch), the buffer is not marked as most-recently-used until the given address produces a buffer hit.

This field is initialized by hardware reset.

00 All four buffers are available for any flash access, that is, there is no partitioning of the buffers based on the access type.

01 Reserved

10 The buffers are partitioned into two groups with buffers 0 and 1 allocated for instruction fetches and buffers 2 and 3 for data accesses.

11 Reserved

Reserved

This is a Read only bit. It can be programmed but it has no functionality.

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Field

BAF_DIS

16:17

ARBM

Flash memory controller (PFLASH Controller)

Table 296. PFCR3 field descriptions(Continued)

Description

BAF Disable. This field controls executable access to the BAF (Boot Assist

Flash) region of the flash, where the access type is detected by evaluating

{p0,p1}_hprot[0]. Once this field is set, attempted instruction access attempts targeting the BAF region are aborted and terminated with a system bus error.

The affect of this field applies to system bus transfers through Port0 and Port1.

Data-type accesses to the BAF region are not affected by this field.

Once this field is set, it becomes a read-only field and can only be cleared by hardware reset. Once this field is set, any subsequent write attempts to modify this field are ignored with an error-free data transfer termination.

This field is initialized by hardware reset.

0 Executable access to the BAF flash region is allowed.

1 Executable access to the BAF flash region is prohibited.

Arbitration Mode. This 2-bit field controls the arbitration of concurrent flash access requests from the two AHB ports of the flash memory controller. In both fixed priority or round-robin modes, write requests are prioritized higher than read requests, and read requests are prioritized higher than speculative prefetch requests whenever both ports issue concurrent requests.

This field is initialized by hardware reset.

00 Fixed priority arbitration with AHB p0>p1

01 Fixed priority arbitration with AHB p1>p0

1x Round-robin arbitration

30.4.1.4 Platform Flash Access Protection Register (PFAPR)

The PFlash Access Protection Register (PFAPR) is used to control read and write accesses to the flash array.

Offset: 0x00C

0 1

Reset 1

M0AP

M1AP

M2AP

M3AP

M4AP

Access: Supervisor Read/Write

11 12 13 14 15

M5AP

1 1

M6AP

16 17

Reset 1

M8AP

M9AP

19 20 21

M10AP

22 23

M11AP

24 25

M12AP

26 27

M13AP

1 1 1 1 1 1 1 1 1 1 1

Figure 235. Platform Flash Access Protection Register (PFAPR)

M14AP

30 31

M15AP

M7AP

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Field

0:1

M0AP

2:3

M1AP

4:5

M2AP

6:7

M3AP

8:9

M4AP

10:11

M5AP

12:13

M6AP

RM0349

Table 297. PFAPR field descriptions

Description

Master 0 Access Protection. This field controls whether read and write accesses to the flash are allowed based on the master ID of a requesting master. These fields are initialized by hardware reset.

00 No accesses may be performed by this master

01 Only read accesses may be performed by this master

10 Only write accesses may be performed by this master

11 Both read and write accesses may be performed by this master

Master 1 Access Protection. This field controls whether read and write accesses to the flash are allowed based on the master ID of a requesting master. These fields are initialized by hardware reset.

00 No accesses may be performed by this master

01 Only read accesses may be performed by this master

10 Only write accesses may be performed by this master

11 Both read and write accesses may be performed by this master

Master 2 Access Protection. This field controls whether read and write accesses to the flash are allowed based on the master ID of a requesting master. These fields are initialized by hardware reset.

00 No accesses may be performed by this master

01 Only read accesses may be performed by this master

10 Only write accesses may be performed by this master

11 Both read and write accesses may be performed by this master

Master 3 Access Protection. This field controls whether read and write accesses to the flash are allowed based on the master ID of a requesting master. These fields are initialized by hardware reset.

00 No accesses may be performed by this master

01 Only read accesses may be performed by this master

10 Only write accesses may be performed by this master

11 Both read and write accesses may be performed by this master

Master 4 Access Protection. This field controls whether read and write accesses to the flash are allowed based on the master ID of a requesting master. These fields are initialized by hardware reset.

00 No accesses may be performed by this master

01 Only read accesses may be performed by this master

10 Only write accesses may be performed by this master

11 Both read and write accesses may be performed by this master

Master 5 Access Protection. This field controls whether read and write accesses to the flash are allowed based on the master ID of a requesting master. These fields are initialized by hardware reset.

00 No accesses may be performed by this master

01 Only read accesses may be performed by this master

10 Only write accesses may be performed by this master

11 Both read and write accesses may be performed by this master

Master 6 Access Protection. This field controls whether read and write accesses to the flash are allowed based on the master ID of a requesting master. These fields are initialized by hardware reset.

00 No accesses may be performed by this master

01 Only read accesses may be performed by this master

10 Only write accesses may be performed by this master

11 Both read and write accesses may be performed by this master

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Field