RM0349 Enhanced direct memory access (eDMA)
Field
0
ELINK
1:15
BITER
Table 204. DMA_TCD n _BITER_ELINKNO field descriptions
Description
Enables channel-to-channel linking on minor loop complete
As the channel completes the minor loop, this flag enables the linking to another channel, defined by BITER[LINKCH]. The link target channel initiates a channel service request via an internal mechanism that sets the TCD n _CSR[START] bit of the specified channel. If channel linking disables, the BITER value extends to 15 bits in place of a link channel number. If the major loop is exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel linking.
Note: When the software loads the TCD, this field must be set equal to the corresponding CITER field. Otherwise, a configuration error is reported. As the major iteration count is exhausted, the contents of this field is reloaded into the CITER field.
0 The channel-to-channel linking is disabled
1 The channel-to-channel linking is enabled
Starting major iteration count
As the transfer control descriptor is first loaded by software, this 9-bit (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER field. As the major iteration count is exhausted, the contents of this field are reloaded into the
CITER field.
Note: When the software loads the TCD, this field must be set equal to the corresponding CITER field. Otherwise, a configuration error is reported. As the major iteration count is exhausted, the contents of this field is reloaded into the CITER field. If the channel is configured to execute a single service request, the initial values of BITER and CITER should be 0x0001.
19.3.32 TCD Control and Status (DMA_TCD
n
_CSR)
Offset: 0x101E + n * 0x20 (n = 0 to 15)
0 1 2 3 4
R
5 6 7 8 9 10
BWC MAJORLINKCH
W
11
ESG
Access: User read/write
12 13 14 15
Reset
(1)
x x x x
1. x = Undefined at reset x x x x x x x x
Figure 143. TCD Control and Status (DMA_TCD n _CSR) x x x x
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Enhanced direct memory access (eDMA) RM0349
Field
Table 205. DMA_TCD n _CSR field descriptions
Description
0:1
BWC
2:7
MAJORLINKCH
Bandwidth control
Throttles the amount of bus bandwidth consumed by the eDMA. In general, as the eDMA processes the minor loop, it continuously generates read/write sequences until the minor count is exhausted. This field forces the eDMA to stall after the completion of each read/write access to control the bus request bandwidth seen by the crossbar switch (XBS).
Note: If the source and destination sizes are equal, this field is ignored between the first and second transfers and after the last write of each minor loop. This behavior is a side effect of reducing start-up latency.
00 No eDMA engine stalls
01 Reserved
10 eDMA engine stalls for 4 cycles after each r/w
11 eDMA engine stalls for 8 cycles after each r/w
Link channel number
If (MAJORELINK = 0) then
– No channel-to-channel linking (or chaining) is performed after the major loop counter is exhausted.
else
– After the major loop counter is exhausted, the eDMA engine initiates a channel service request at the channel defined by these six bits by setting that channel’s
TCD n _CSR[START] bit.
8
DONE
9
ACTIVE
10
MAJORELINK
Channel done
This flag indicates the eDMA has completed the major loop. The eDMA engine sets it as the CITER count reaches zero; The software clears it, or the hardware when the channel is activated.
Note: This bit must be cleared to write the MAJORELINK or ESG bits.
This bit resets to zero.
Channel active
This flag signals the channel is currently in execution. It is set when channel service begins, and the eDMA clears it as the minor loop completes or if any error condition is detected.
Enable channel-to-channel linking on major loop complete
As the channel completes the major loop, this flag enables the linking to another channel, defined by MAJORLINKCH. The link target channel initiates a channel service request via an internal mechanism that sets the TCD n _CSR[START] bit of the specified channel.
Note: To support the dynamic linking coherency model, this field is forced to zero when written to while the TCD n _CSR[DONE] bit is set.
0 The channel-to-channel linking is disabled
1 The channel-to-channel linking is enabled
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