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C8051F060/1/2/3/4/5/6/7
13.2.6.3.SFR Page Stack Example
The following is an example that shows the operation of the SFR Page Stack during interrupts.
In this example, the SFR Page Control is left in the default enabled state (i.e., SFRPGEN = 1), and the
CIP-51 is executing in-line code that is writing values to Port 5 (SFR “P5”, located at address 0xD8 on SFR
Page 0x0F). The device is also using the Programmable Counter Array (PCA) and the 10-bit ADC (ADC2) window comparator to monitor a voltage. The PCA is timing a critical control function in its interrupt service routine (ISR), so its interrupt is enabled and is set to high priority. The ADC2 is monitoring a voltage that is less important, but to minimize the software overhead its window comparator is being used with an associated ISR that is set to low priority. At this point, the SFR page is set to access the Port 5 SFR (SFRPAGE =
Figure 13.4. SFR Page Stack While Using SFR Page 0x0F To Access Port 5
SFR Page
Stack SFR's
0x0F
SFRPAGE
(Port 5)
SFRNEXT
SFRLAST
134 Rev. 1.2
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While CIP-51 executes in-line code (writing values to Port 5 in this example), ADC2 Window Comparator
Interrupt occurs. The CIP-51 vectors to the ADC2 Window Comparator ISR and pushes the current SFR
Page value (SFR Page 0x0F) into SFRNEXT in the SFR Page Stack. The SFR page needed to access
ADC2’s SFRs is then automatically placed in the SFRPAGE register (SFR Page 0x02). SFRPAGE is considered the “top” of the SFR Page Stack. Software can now access the ADC2 SFRs. Software may switch to any SFR Page by writing a new value to the SFRPAGE register at any time during the ADC2 ISR to
access SFRs that are not on SFR Page 0x02. See Figure 13.5 below.
Figure 13.5. SFR Page Stack After ADC2 Window Comparator Interrupt Occurs
SFR Page 0x02
Automatically pushed on stack in
SFRPAGE on ADC2 interrupt
0x02
SFRPAGE
(ADC2)
SFRPAGE pushed to
SFRNEXT
0x0F
SFRNEXT
(Port 5)
SFRLAST
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While in the ADC2 ISR, a PCA interrupt occurs. Recall the PCA interrupt is configured as a high priority interrupt, while the ADC2 interrupt is configured as a low priority interrupt. Thus, the CIP-51 will now vector to the high priority PCA ISR. Upon doing so, the CIP-51 will automatically place the SFR page needed to access the PCA’s special function registers into the SFRPAGE register, SFR Page 0x00. The value that was in the SFRPAGE register before the PCA interrupt (SFR Page 2 for ADC2) is pushed down the stack into SFRNEXT. Likewise, the value that was in the SFRNEXT register before the PCA interrupt (in this case SFR Page 0x0F for Port 5) is pushed down to the SFRLAST register, the “bottom” of the stack. Note that a value stored in SFRLAST (via a previous software write to the SFRLAST register) will be overwritten.
Figure 13.6. SFR Page Stack Upon PCA Interrupt Occurring During an ADC2 ISR
SFR Page 0x00
Automatically pushed on stack in
SFRPAGE on PCA interrupt
0x00
SFRPAGE
SFRPAGE pushed to
SFRNEXT
(PCA)
0x02
SFRNEXT
SFRNEXT pushed to
SFRLAST
(ADC2)
0x0F
SFRLAST
(Port 5)
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On exit from the PCA interrupt service routine, the CIP-51 will return to the ADC2 Window Comparator
ISR. On execution of the RETI instruction, SFR Page 0x00 used to access the PCA registers will be automatically popped off of the SFR Page Stack, and the contents of the SFRNEXT register will be moved to the SFRPAGE register. Software in the ADC2 ISR can continue to access SFRs as it did prior to the PCA interrupt. Likewise, the contents of SFRLAST are moved to the SFRNEXT register. Recall this was the
SFR Page value 0x0F being used to access Port 5 before the ADC2 interrupt occurred. See Figure 13.7
below.
Figure 13.7. SFR Page Stack Upon Return From PCA Interrupt
SFR Page 0x00
Automatically popped off of the stack on return from interrupt
0x02
SFRPAGE
SFRNEXT popped to
SFRPAGE
(ADC2)
0x0F
SFRNEXT
(Port 5)
SFRLAST popped to
SFRNEXT
SFRLAST
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On the execution of the RETI instruction in the ADC2 Window Comparator ISR, the value in SFRPAGE register is overwritten with the contents of SFRNEXT. The CIP-51 may now access the Port 5 SFR bits as
it did prior to the interrupts occurring. See Figure 13.8 below.
Figure 13.8. SFR Page Stack Upon Return From ADC2 Window Interrupt
SFR Page 0x02
Automatically popped off of the stack on return from interrupt
0x0F
SFRPAGE
(Port 5)
SFRNEXT popped to
SFRPAGE
SFRNEXT
SFRLAST
Note that in the above example, all three bytes in the SFR Page Stack are accessible via the SFRPAGE,
SFRNEXT, and SFRLAST special function registers. If the stack is altered while servicing an interrupt, it is possible to return to a different SFR Page upon interrupt exit than selected prior to the interrupt call. Direct access to the SFR Page stack can be useful to enable real-time operating systems to control and manage context switching between multiple tasks.
Push operations on the SFR Page Stack only occur on interrupt service, and pop operations only occur on interrupt exit (execution on the RETI instruction). The automatic switching of the SFRPAGE and operation of the SFR Page Stack as described above can be disabled in software by clearing the SFR Automatic
Page Enable Bit (SFRPGEN) in the SFR Page Control Register (SFRPGCN). See Figure 13.9.
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Figure 13.9. SFRPGCN: SFR Page Control Register
R/W
-
Bit7
R/W
-
Bit6
R/W
-
Bit5
R/W
-
Bit4
R/W
-
Bit3
R/W
-
Bit2
R/W
-
Bit1
R/W Reset Value
SFRPGEN 00000001
Bit0
SFR Address: 0x96
SFR Page: F
Bits7-1: Reserved.
Bit0: SFRPGEN: SFR Automatic Page Control Enable.
Upon interrupt, the C8051 Core will vector to the specified interrupt service routine and automatically switch the SFR page to the corresponding peripheral or function’s SFR page.
This bit is used to control this autopaging function.
0: SFR Automatic Paging disabled. C8051 core will not automatically change to the appropriate SFR page (i.e., the SFR page that contains the SFRs for the peripheral/function that was the source of the interrupt).
1: SFR Automatic Paging enabled. Upon interrupt, the C8051 will switch the SFR page to the page that contains the SFRs for the peripheral or function that is the source of the interrupt.
Figure 13.10. SFRPAGE: SFR Page Register
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W Reset Value
00000000
Bit0
SFR Address: 0x84
SFR Page: All Pages
Bits7-0: SFR Page Bits: Byte Represents the SFR Page the C8051 MCU uses when reading or modifying SFRs.
Write: Sets the SFR Page.
Read: Byte is the SFR page the C8051 MCU is using.
When enabled in the SFR Page Control Register (SFRPGCN), the C8051 will automatically switch to the SFR Page that contains the SFRs of the corresponding peripheral/function that caused the interrupt, and return to the previous SFR page upon return from interrupt (unless
SFR Stack was altered before a returning from the interrupt).
SFRPAGE is the top byte of the SFR Page Stack, and push/pop events of this stack are caused by interrupts (and not by reading/writing to the SFRPAGE register)
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Figure 13.11. SFRNEXT: SFR Next Register
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W Reset Value
00000000
Bit0
SFR Address: 0x85
SFR Page: All Pages
Bits7-0: SFR Page Stack Bits: SFR page context is retained upon interrupts/return from interrupts in a 3 byte SFR Page Stack: SFRPAGE is the first entry, SFRNEXT is the second, and SFR-
LAST is the third entry. The SFR stack bytes may be used to alter the context in the SFR
Page Stack, and will not cause the stack to ‘push’ or ‘pop’. Only interrupts and return from interrupt cause push and pop the SFR Page Stack.
Write: Sets the SFR Page contained in the second byte of the SFR Stack. This will cause the SFRPAGE SFR to have this SFR page value upon a return from interrupt.
Read: Returns the value of the SFR page contained in the second byte of the SFR stack.
This is the value that will go to the SFR Page register upon a return from interrupt.
Figure 13.12. SFRLAST: SFR Last Register
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W Reset Value
00000000
Bit0
SFR Address: 0x86
SFR Page: All Pages
Bits7-0: SFR Page Stack Bits: SFR page context is retained upon interrupts/return from interrupts in a 3 byte SFR Page Stack: SFRPAGE is the first entry, SFRNEXT is the second, and SFR-
LAST is the third entry. The SFR stack bytes may be used to alter the context in the SFR
Page Stack, and will not cause the stack to ‘push’ or ‘pop’. Only interrupts and return from interrupt cause push and pop the SFR Page Stack.
Write:
Sets the SFR Page in the last entry of the SFR Stack. This will cause the SFRNEXT SFR to have this SFR page value upon a return from interrupt.
Read:
Returns the value of the SFR page contained in the last entry of the SFR stack.
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Table 13.2. Special Function Register (SFR) Memory Map
E
S
S
A
D
D
R
SFR
P
A
G
E
F8
F0
E8
E0
D8
D0
C8
C0
B8
2
3
F
0
1
3
F
0
1
2
3
F
0
1
2
2
3
F
0
1
3
F
0
1
2
2
3
F
0
1
3
F
0
1
2
3
F
0
1
2
2
3
F
0
1
0(8)
SPI0CN
CAN0CN
DMA0CF
P7
B
(ALL PAGES)
ADC0CN
ADC1CN
ADC2CN
P6
ACC
(ALL PAGES)
PCA0CN
CAN0DATL
DMA0CN
P5
PSW
(ALL PAGES)
TMR2CN
TMR3CN
TMR4CN
P4
SMB0CN
CAN0STA
IP
(ALL PAGES)
0(8)
1(9)
PCA0L
DMA0CTL
PCA0CPL5
2(A)
PCA0H
DMA0CTH
PCA0CPH5
ADC0CPT
2(A)
3(B)
PCA0CPL0
DMA0CSL
ADC0CCF
3(B)
4(C)
PCA0CPH0
DMA0CSH
5(D)
PCA0CPL1
DMA0BND
6(E)
PCA0CPH1
DMA0ISW
7(F)
EIP1
(ALL PAGES)
EIP2
(ALL PAGES)
PCA0CPL2 PCA0CPH2 PCA0CPL3 PCA0CPH3 PCA0CPL4 PCA0CPH4 RSTSRC
EIE1
(ALL PAGES)
EIE2
(ALL PAGES)
XBR0
PCA0MD
CAN0DATH
XBR1
PCA0CPM0
CAN0ADR
XBR2
PCA0CPM1
CAN0TST
XBR3
PCA0CPM2 PCA0CPM3 PCA0CPM4 PCA0CPM5
DMA0DAL
REF0CN
REF1CN
REF2CN
TMR2CF
TMR3CF
TMR4CF
SMB0STA
SADEN0
1(9)
DMA0DAH
DAC0L
DAC1L
RCAP2L
RCAP3L
RCAP4L
SMB0DAT
AMX2CF
DMA0DSL
DAC0H
DAC1H
RCAP2H
RCAP3H
RCAP4H
SMB0ADR
AMX0SL
AMX2SL
DMA0DSH
DAC0CN
DAC1CN
TMR2L
TMR3L
TMR4L
ADC0GTL
ADC2GTL
ADC0CF
ADC1CF
ADC2CF
4(C)
DMA0IPT
TMR2H
TMR3H
TMR4H
ADC0GTH
ADC2GTH
5(D)
DMA0IDT
ADC0LTL
ADC2LTL
ADC0L
ADC1L
ADC2L
6(E)
WDTCN
(ALL PAGES)
SMB0CR
ADC0LTH
ADC2LTH
ADC0H
ADC1H
ADC2H
7(F)
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Table 13.2. Special Function Register (SFR) Memory Map
B0
A8
A0
98
90
88
80
2
3
F
0
1
3
F
0
1
2
3
F
0
1
2
3
F
0
1
2
3
F
0
1
2
2
3
F
0
1
3
F
0
1
2
P3
(ALL PAGES)
IE
(ALL PAGES)
P2
(ALL PAGES)
SCON0
SCON1
P1
(ALL PAGES)
TCON
CPT0CN
CPT1CN
CPT2CN
SADDR0
EMI0TC
SBUF0
SBUF1
SSTA0
TMOD
CPT0MD
CPT1MD
CPT2MD
EMI0CN
SPI0CFG
TL0
OSCICN
EMI0CF
SPI0DAT
TL1
OSCICL
P0MDOUT
P4MDOUT
TH0
OSCXCN
P1MDIN
P1MDOUT
SPI0CKR
P5MDOUT
TH1
P2MDIN
P2MDOUT
P6MDOUT
SFRPGCN
CKCON
FLSCL
FLACL
P3MDOUT
P7MDOUT
CLKSEL
PSCTL
P0
(ALL PAGES)
SP
(ALL PAGES)
DPL
(ALL PAGES)
DPH
(ALL PAGES)
SFRPAGE
(ALL PAGES)
SFRNEXT
(ALL PAGES)
SFRLAST
(ALL PAGES)
PCON
(ALL PAGES)
0(8) 1(9) 2(A) 3(B) 4(C) 5(D) 6(E) 7(F)
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Table 13.3. Special Function Registers
CAN0ADR
CAN0CN
CAN0DATH
CAN0DATL
CAN0STA
CAN0TST
CKCON
CLKSEL
CPT0CN
CPT0MD
CPT1CN
CPT1MD
CPT2CN
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
Register
B
Address
0xF0
SFR Page Description
All Pages B Register
ACC
ADC0CCF
ADC0CF
ADC0CN
0xE0
0xBB
0xBC
0xE8
All Pages Accumulator
F
0
0
ADC0 Calibration Coefficient
ADC0 Configuration
ADC0 Control
ADC0CPT
ADC0GTH
ADC0GTL
ADC0H
ADC0L
ADC0LTH
ADC0LTL
ADC1CF
ADC1CN
ADC1H
ADC1L
0xBA
0xC5
0xC4
0xBF
0xBE
0xC7
0xC6
0xBC
0xE8
0xBF
0xBE
F
0
0
0
0
0
0
1
1
1
1
ADC0 Calibration Pointer
ADC0 Greater-Than High
ADC0 Greater-Than Low
ADC0 Data Word High
ADC0 Data Word Low
ADC0 Less-Than High
ADC0 Less-Than Low
ADC1 Configuration
ADC1 Control
ADC1 Data Word High
ADC1 Data Word Low
ADC2CF 0xBC 2 ADC2 Configuration
ADC2CN
ADC2GTH
0xE8
0xC5
2
2
ADC2 Control
ADC2 Greater-Than High
ADC2GTL
ADC2H
ADC2L
ADC2LTH
ADC2LTL
AMX0SL
AMX2CF
AMX2SL
0xC4
0xBF
0xBE
0xC7
0xC6
0xBB
0xBA
0xBB
2
2
2
2
2
0
2
2
ADC2 Greater-Than Low
ADC2 Data Word High
ADC2 Data Word Low
ADC2 Less-Than High
ADC2 Less-Than Low
ADC0 Multiplexer Channel Select
ADC2 Analog Multiplexer Configuration
ADC2 Analog Multiplexer Channel Select
0xDA
0xF8
0xD9
0xD8
0xC0
0xDB
0x8E
0x97
0x88
0x89
0x88
0x89
0x88
1
1
1
1
1
1
2
2
3
1
1
0
F
CAN0 Address
CAN0 Control
CAN0 Data High
CAN0 Data Low
CAN0 Status
CAN0 Test
Clock Control
Oscillator Clock Selection Register
Comparator 0 Control
Comparator 0 Configuration
Comparator 1 Control
Comparator 1 Configuration
Comparator 2 Control
Rev. 1.2
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Table 13.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
Register
CPT2MD
Address
0x89
SFR Page Description
3 Comparator 2 Configuration
DAC0CN 0xD4 0 DAC0 Control
DAC0H 0xD3 0 DAC0 High
DAC0L
DAC1CN
0xD2
0xD4
0
1
DAC0 Low
DAC1 Control
0xD3
0xD2
0xD9
0xDC
0xDB
0xDE
0xDD
0xFE
0x83
0x82
0xFD
0xF8
0xD8
0xFC
0xFB
0xFA
0xF9
0xDA
0xE6
0xE7
0xF6
0xF7
0xA3
0xA2
0xA1
0xB7
0xB7
0xA8
0xB8
0x8B
0x8A
0x8C
0x80
0xA4
0x90
0xAD
0xA5
0xA0
DAC1H
DAC1L
DMA0BND
DMA0CF
DMA0CN
DMA0CSH
DMA0CSL
DMA0CTH
DMA0CTL
DMA0DAH
DMA0DAL
DMA0DSH
DMA0DSL
DMA0IDT
DMA0IPT
DMA0ISW
DPH
DPL
EIE1
EIE2
EIP1
EIP2
EMI0CF
EMI0CN
EMI0TC
FLACL
FLSCL
IE
IP
OSCICL
OSCICN
OSCXCN
P0
P0MDOUT
P1
P1MDIN
P1MDOUT
P2
1
1
0
0
DAC1 High
DAC1 Low
3
3
3
3
3
3
3
3
DMA0 Instruction Boundary
DMA0 Configuration
DMA0 Control
DMA0 Repeat Counter Status High Byte
DMA0 Repeat Counter Status Low Byte
DMA0 Repeat Counter Limit High Byte
DMA0 Repeat Counter Limit Low Byte
DMA0 Data Address Beginning High Byte
3
3
3
3
DMA0 Data Address Beginning Low Byte
DMA0 Data Address Pointer High Byte
DMA0 Data Address Pointer Low Byte
DMA0 Instruction Write Data
3
3
DMA0 Instruction Write Address
DMA0 Instruction Status
All Pages Data Pointer High
All Pages Data Pointer Low
All Pages Extended Interrupt Enable 1
All Pages Extended Interrupt Enable 2
All Pages Extended Interrupt Priority 1
All Pages Extended Interrupt Priority 2
0 EMIF Configuration
EMIF Control
EMIF Timing Control
F Flash Access Limit
0 Flash Scale
All Pages Interrupt Enable
All Pages Interrupt Priority
F Internal Oscillator Calibration
F
F
Internal Oscillator Control
External Oscillator Control
All Pages Port 0 Latch
F Port 0 Output Mode Configuration
All Pages Port 1 Latch
F Port 1 Input Mode
F Port 1 Output Mode Configuration
All Pages Port 2 Latch
Page No.
page 85 page 85 page 85 page 85
page 84 page 84 page 84 page 84
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Table 13.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
Register
P2MDIN
P2MDOUT
Address
0xAE
0xA6
SFR Page Description
F
F
Port 2 Input Mode
Port 2 Output Mode Configuration
P3 0xB0 All Pages Port 3 Latch
P3MDOUT
P4
0xA7
0xC8
F
F
Port 3 Output Mode Configuration
Port 4 Latch
P4MDOUT
P5
P5MDOUT
P6
0x9C
0xD8
0x9D
0xE8
F
F
F
F
Port 4 Output Mode Configuration
Port 5 Latch
Port 5 Output Mode Configuration
Port 6 Latch
P6MDOUT
P7
P7MDOUT
PCA0CPM2
PCA0CPM3
PCA0CPM4
PCA0CPM5
PCA0H
PCA0L
PCA0MD
PCON
PSCTL
PSW
RCAP2H
RCAP2L
RCAP3H
RCAP3L
RCAP4H
RCAP4L
PCA0CN
PCA0CPH0
PCA0CPH1
PCA0CPH2
PCA0CPH3
PCA0CPH4
PCA0CPH5
PCA0CPL0
PCA0CPL1
PCA0CPL2
PCA0CPL3
PCA0CPL4
PCA0CPL5
PCA0CPM0
PCA0CPM1
0x9E
0xF8
0x9F
0x8F
0xD0
0xCB
0xCA
0xCB
0xCA
0xCB
0xCA
0xDC
0xDD
0xDE
0xDF
0xFA
0xF9
0xD9
0x87
0xFB
0xFD
0xE9
0xEB
0xED
0xE1
0xDA
0xDB
0xD8
0xFC
0xFE
0xEA
0xEC
0xEE
0xE2
F
F
Port 6 Output Mode Configuration
Port 7 Latch
F Port 7 Output Mode Configuration
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PCA Control
PCA Capture 0 High
PCA Capture 1 High
PCA Capture 2 High
PCA Capture 3 High
PCA Capture 4 High
PCA Capture 5 High
PCA Capture 0 Low
PCA Capture 1 Low
PCA Capture 2 Low
PCA Capture 3 Low
PCA Capture 4 Low
PCA Capture 5 Low
PCA Module 0 Mode Register
PCA Module 1 Mode Register
0
0
0
0
PCA Module 2 Mode Register
PCA Module 3 Mode Register
PCA Module 4 Mode Register
PCA Module 5 Mode Register
0
0
PCA Counter High
PCA Counter Low
0 PCA Mode
All Pages Power Control
0 Program Store R/W Control
All Pages Program Status Word
0
0
Timer/Counter 2 Capture/Reload High
Timer/Counter 2 Capture/Reload Low
2
2
1
1
Timer/Counter 3 Capture/Reload High
Timer/Counter 3 Capture/Reload Low
Timer/Counter 4 Capture/Reload High
Timer/Counter 4 Capture/Reload Low
page 316 page 316 page 316 page 316 page 316 page 316 page 316 page 316
page 314 page 314 page 314 page 314 page 314 page 314
page 301 page 301 page 301 page 301 page 301 page 301
Page No.
page 316 page 316 page 316 page 316
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Table 13.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
Register
REF0CN
REF1CN
Address
0xD1
0xD1
SFR Page Description
0
1
Voltage Reference Control 0
Voltage Reference Control 1
REF2CN 0xD1 2 Voltage Reference Control 2
SP
SPI0CFG
SPI0CKR
SPI0CN
SPI0DAT
SSTA0
TCON
TH0
TH1
TL0
TL1
TMOD
TMR2CF
TMR2CN
TMR2H
TMR2L
RSTSRC
SADDR0
SADEN0
SBUF0
SBUF1
SCON0
SCON1
SFRLAST
SFRNEXT
SFRPAGE
SFRPGCN
SMB0ADR
SMB0CN
SMB0CR
SMB0DAT
SMB0STA
TMR3CF
TMR3CN
TMR3H
TMR3L
TMR4CF
TMR4CN
TMR4H
0x8D
0x8A
0x8B
0x89
0xC9
0xC8
0xCD
0xCC
0x81
0x9A
0x9D
0xF8
0x9B
0x91
0x88
0x8C
0xC9
0xC8
0xCD
0xCC
0xC9
0xC8
0xCD
0x85
0x84
0x96
0xC3
0xC0
0xCF
0xC2
0xC1
0xEF
0xA9
0xB9
0x99
0x99
0x98
0x98
0x86
2
2
2
1
1
1
1
0
0
0
0
Reset Source
UART 0 Slave Address
UART 0 Slave Address Enable
UART 0 Data Buffer
1
0
UART 1 Data Buffer
UART 0 Control
1 UART 1 Control
All Pages SFR Page Stack Access Register
All Pages SFR Page Register
All Pages SFR Page Register
F
0
SFR Page Control Register
SMBus Slave Address
0
0
0
0
SMBus Control
SMBus Clock Rate
SMBus Data
SMBus Status
0
0
0
0
0
0
0
0
All Pages Stack Pointer
0 SPI Configuration
0
0
SPI Clock Rate Control
SPI Control
0
0
0
0
SPI Data
UART 0 Status
Timer/Counter Control
Timer/Counter 0 High
Timer/Counter 1 High
Timer/Counter 0 Low
Timer/Counter 1 Low
Timer/Counter Mode
Timer/Counter 2 Configuration
Timer/Counter 2 Control
Timer/Counter 2 High
Timer/Counter 2 Low
Timer/Counter 3 Configuration
Timer/Counter 3 Control
Timer/Counter 3 High
Timer/Counter 3 Low
Timer/Counter 4 Configuration
Timer/Counter 4 Control
Timer/Counter 4 High
146 Rev. 1.2
Page No.
*2
,
*3
,
*5
C8051F060/1/2/3/4/5/6/7
Table 13.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
Register
TMR4L
Address
0xCC
SFR Page Description
2 Timer/Counter 4 Low
WDTCN
XBR0
XBR1
XBR2
0xFF
0xE1
0xE2
0xE3
All Pages Watchdog Timer Control
F
F
F
Port I/O Crossbar Control 0
Port I/O Crossbar Control 1
Port I/O Crossbar Control 2
XBR3 0xE4 F Port I/O Crossbar Control 3
*1
Refers to a register in the C8051F060/2/4/6 only.
*2
Refers to a register in the C8051F060/2 only.
*3
Refers to a register in the C8051F061/3 only.
*4
Refers to a register in the C8051F060/1/2/3 only.
*5
Refers to a register in the C8051F064/5/6/7 only.
Page No.
Rev. 1.2
147
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