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C8051F060/1/2/3/4/5/6/7
24.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)
In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The counter/ timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0, GATE0 and
TF0. TL0 can use either the system clock or an external input signal as its timebase. The TH0 register is restricted to a timer function sourced by the system clock or prescaled clock. TH0 is enabled using the
Timer 1 run control bit TR1. TH0 sets the Timer 1 overflow flag TF1 on overflow and thus controls the
Timer 1 interrupt.
Timer 1 is inactive in Mode 3. When Timer 0 is operating in Mode 3, Timer 1 can be operated in Modes 0,
1 or 2, but cannot be clocked by external signals nor set the TF1 flag and generate an interrupt. However, the Timer 1 overflow can be used to generate baud rates for the SMBus and/or UART, and/or initiate ADC conversions. While Timer 0 is operating in Mode 3, Timer 1 run control is handled through its mode settings. To run Timer 1 while Timer 0 is in Mode 3, set the Timer 1 Mode as 0, 1, or 2. To disable Timer 1, configure it for Mode 3.
Pre-scaled Clock
SYSCLK
Figure 24.3. T0 Mode 3 Block Diagram
CKCON
T T
1
M
0
M
C
A
1
S S
C
A
0
TMOD
G
A
T
E
1
C
/
T
1
T
1
T
1
M
1
M
0
G
A
T
E
0
C
/
T
0
T
0
T
0
M
1
M
0
0
TR1
TH0
(8 bits)
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Interrupt
Interrupt
1
T0
TL0
(8 bits)
TR0
Crossbar
GATE0
/INT0
290 Rev. 1.2
C8051F060/1/2/3/4/5/6/7
Figure 24.4. TCON: Timer Control Register
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
R/W
TF1
Bit7
R/W
TR1
Bit6
R/W
TF0
Bit5
R/W
TR0
Bit4
R/W
IE1
Bit3
R/W
IT1
Bit2
R/W
IE0
Bit1
R/W
IT0
Reset Value
00000000
Bit0
Bit
Addressable
SFR Address:
0x88
SFR Page: 0
TF1: Timer 1 Overflow Flag.
Set by hardware when Timer 1 overflows. This flag can be cleared by software but is automatically cleared when the CPU vectors to the Timer 1 interrupt service routine.
0: No Timer 1 overflow detected.
1: Timer 1 has overflowed.
TR1: Timer 1 Run Control.
0: Timer 1 disabled.
1: Timer 1 enabled.
TF0: Timer 0 Overflow Flag.
Set by hardware when Timer 0 overflows. This flag can be cleared by software but is automatically cleared when the CPU vectors to the Timer 0 interrupt service routine.
0: No Timer 0 overflow detected.
1: Timer 0 has overflowed.
TR0: Timer 0 Run Control.
0: Timer 0 disabled.
1: Timer 0 enabled.
IE1: External Interrupt 1.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It can be cleared by software but is automatically cleared when the CPU vectors to the External Interrupt 1 service routine if IT1 = 1. This flag is the inverse of the /INT1 signal.
IT1: Interrupt 1 Type Select.
This bit selects whether the configured /INT1 interrupt will be falling-edge sensitive or active-low.
0: /INT1 is level triggered, active-low.
1: /INT1 is edge triggered, falling-edge.
IE0: External Interrupt 0.
This flag is set by hardware when an edge/level of type defined by IT0 is detected. It can be cleared by software but is automatically cleared when the CPU vectors to the External Interrupt 0 service routine if IT0 = 1. This flag is the inverse of the /INT0 signal.
IT0: Interrupt 0 Type Select.
This bit selects whether the configured /INT0 interrupt will be falling-edge sensitive or active-low.
0: /INT0 is level triggered, active logic-low.
1: /INT0 is edge triggered, falling-edge.
Rev. 1.2
291
C8051F060/1/2/3/4/5/6/7
Figure 24.5. TMOD: Timer Mode Register
R/W
GATE1
Bit7
R/W
C/T1
Bit6
R/W
T1M1
Bit5
R/W
T1M0
Bit4
R/W
GATE0
Bit3
R/W
C/T0
Bit2
R/W
T0M1
Bit1
R/W
T0M0
Bit0
Reset Value
00000000
SFR Address:
0x89
SFR Page: 0
Bit7:
Bit6:
GATE1: Timer 1 Gate Control.
0: Timer 1 enabled when TR1 = 1 irrespective of /INT1 logic level.
1: Timer 1 enabled only when TR1 = 1 AND /INT1 = logic 1.
C/T1: Counter/Timer 1 Select.
0: Timer Function: Timer 1 incremented by clock defined by T1M bit (CKCON.4).
1: Counter Function: Timer 1 incremented by high-to-low transitions on external input pin
(T1).
Bits5-4: T1M1-T1M0: Timer 1 Mode Select.
These bits select the Timer 1 operation mode.
T1M1
0
0
1
1
T1M0
0
1
0
1
Mode
Mode 0: 13-bit counter/timer
Mode 1: 16-bit counter/timer
Mode 2: 8-bit counter/timer with autoreload
Mode 3: Timer 1 inactive
Bit3:
Bit2:
GATE0: Timer 0 Gate Control.
0: Timer 0 enabled when TR0 = 1 irrespective of /INT0 logic level.
1: Timer 0 enabled only when TR0 = 1 AND /INT0 = logic 1.
C/T0: Counter/Timer Select.
0: Timer Function: Timer 0 incremented by clock defined by T0M bit (CKCON.3).
1: Counter Function: Timer 0 incremented by high-to-low transitions on external input pin
(T0).
Bits1-0: T0M1-T0M0: Timer 0 Mode Select.
These bits select the Timer 0 operation mode.
T0M1
0
0
1
1
T0M0
0
1
0
1
Mode
Mode 0: 13-bit counter/timer
Mode 1: 16-bit counter/timer
Mode 2: 8-bit counter/timer with autoreload
Mode 3: Two 8-bit counter/timers
292 Rev. 1.2
C8051F060/1/2/3/4/5/6/7
Figure 24.6. CKCON: Clock Control Register
R/W
-
Bit7
R/W
-
Bit6
R/W
-
Bit5
R/W
T1M
Bit4
R/W
T0M
Bit3
R/W
-
Bit2
R/W
SCA1
Bit1
R/W
SCA0
Reset Value
00000000
Bit0
SFR Address:
0x8E
SFR Page: 0
Bits7-5: UNUSED. Read = 000b, Write = don’t care.
Bit4: T1M: Timer 1 Clock Select.
This select the clock source supplied to Timer 1. T1M is ignored when C/T1 is set to logic 1.
0: Timer 1 uses the clock defined by the prescale bits, SCA1-SCA0.
Bit3:
1: Timer 1 uses the system clock.
T0M: Timer 0 Clock Select.
This bit selects the clock source supplied to Timer 0. T0M is ignored when C/T0 is set to logic 1.
0: Counter/Timer 0 uses the clock defined by the prescale bits, SCA1-SCA0.
1: Counter/Timer 0 uses the system clock.
Bit2: UNUSED. Read = 0b, Write = don’t care.
Bits1-0: SCA1-SCA0: Timer 0/1 Prescale Bits
These bits control the division of the clock supplied to Timer 0 and/or Timer 1 if configured to use prescaled clock inputs.
SCA1
0
0
1
1
SCA0
0
1
0
1
Prescaled Clock
System clock divided by 12
System clock divided by 4
System clock divided by 48
External clock divided by 8†
†Note: External clock divided by 8 is synchronized with the system clock, and external clock must be less than or equal to the system clock frequency to operate the timer in this mode.
Rev. 1.2
293
C8051F060/1/2/3/4/5/6/7
R/W
Bit7
R/W
Bit6
R/W
Bit5
Figure 24.7. TL0: Timer 0 Low Byte
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W Reset Value
00000000
Bit0
SFR Address:
0x8A
SFR Page: 0
Bits 7-0: TL0: Timer 0 Low Byte.
The TL0 register is the low byte of the 16-bit Timer 0
R/W
Bit7
R/W
Bit6
R/W
Bit5
Figure 24.8. TL1: Timer 1 Low Byte
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W Reset Value
00000000
Bit0
SFR Address:
0x8B
SFR Page: 0
Bits 7-0: TL1: Timer 1 Low Byte.
The TL1 register is the low byte of the 16-bit Timer 1.
Figure 24.9. TH0: Timer 0 High Byte
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
Bits 7-0: TH0: Timer 0 High Byte.
The TH0 register is the high byte of the 16-bit Timer 0.
Figure 24.10. TH1: Timer 1 High Byte
R/W
Bit1
R/W Reset Value
00000000
Bit0
SFR Address:
0x8C
SFR Page: 0
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W Reset Value
00000000
Bit0
SFR Address:
0x8D
SFR Page: 0
Bits 7-0: TH1: Timer 1 High Byte.
The TH1 register is the high byte of the 16-bit Timer 1.
294 Rev. 1.2
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