C8051F060/1/2/3/4/5/6/7

C8051F060/1/2/3/4/5/6/7

20.4.2. Clock Rate Register

Figure 20.9. SMB0CR: SMBus0 Clock Rate Register

R/W

Bit7

R/W

Bit6

R/W

Bit5

R/W

Bit4

R/W

Bit3

R/W

Bit2

R/W

Bit1

R/W Reset Value

00000000

Bit0

SFR Address: 0xCF

SFR Page: 0

Bits7-0: SMB0CR.[7:0]: SMBus0 Clock Rate Preset.

The SMB0CR Clock Rate register controls the frequency of the serial clock SCL in master mode. The 8-bit word stored in the SMB0CR Register preloads a dedicated 8-bit timer. The timer counts up, and when it rolls over to 0x00, the SCL logic state toggles.

The SMB0CR setting should be bounded by the following equation , where SMB0CR is the unsigned 8-bit value in register SMB0CR, and SYSCLK is the system clock frequency in Hz:

SMB0CR

< ( (

288 – 0.85

⋅

SYSCLK

⁄ (

6

) )

The resulting SCL signal high and low times are given by the following equations:

T

LOW

=

(

256 –

SMB0CR

T

HIGH

≅ (

258 –

SMB0CR

+ 625ns

Using the same value of SMB0CR from above, the Bus Free Timeout period is given in the following equation:

T

BFT

≅

10

×

(

256 –

SMB0CR

SYSCLK

) 1

244 Rev. 1.2