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C8051F060/1/2/3/4/5/6/7
19.1. Bosch CAN Controller Operation
The CAN Controller featured in the C8051F060/1/2/3 devices is a full implementation of Bosch’s full CAN module and fully complies with CAN specification 2.0B.
The function and use of the CAN Controller is detailed in the Bosch CAN User’s Guide. The User’s Guide should be used as a reference to configure and use the CAN controller. This Silicon Labs datasheet describes how to access the CAN controller.
The CAN Control Register (CAN0CN), CAN Test Register (CAN0TST), and CAN Status Register
(CAN0STA) in the CAN controller can be accessed directly or indirectly via CIP-51 SFRs. All other CAN
registers must be accessed via an indirect indexing method. See “Using CAN0ADR, CAN0DATH, and
CANDATL To Access CAN Registers” on page 229.
Rev. 1.2
227
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Table of contents
- 7 C8051F
- 19 1. System Overview
- 25 1.1. CIP-51™ Microcontroller Core
- 25 1.1.1. Fully 8051 Compatible
- 25 1.1.2. Improved Throughput
- 26 1.1.3. Additional Features
- 27 1.2. On-Chip Memory
- 28 1.3. JTAG Debug and Boundary Scan
- 29 1.4. Programmable Digital I/O and Crossbar
- 30 1.5. Programmable Counter Array
- 31 1.6. Controller Area Network
- 32 1.7. Serial Ports
- 33 1.8. 16-Bit Analog to Digital Converters
- 34 1.9. 10-Bit Analog to Digital Converter
- 35 1.10.12-bit Digital to Analog Converters
- 36 1.11.Analog Comparators
- 37 2. Absolute Maximum Ratings
- 38 3. Global DC Electrical Characteristics
- 39 4. Pinout and Package Definitions
- 51 5. 16-Bit ADCs (ADC0 and ADC1)
- 52 5.1. Single-Ended or Differential Operation
- 52 5.1.1. Pseudo-Differential Inputs
- 53 5.2. Voltage Reference
- 54 5.3. ADC Modes of Operation
- 54 5.3.1. Starting a Conversion
- 54 5.3.2. Tracking Modes
- 56 5.3.3. Settling Time Requirements
- 66 5.4. Calibration
- 69 5.5. ADC0 Programmable Window Detector
- 75 6. Direct Memory Access Interface (DMA0)
- 75 6.1. Writing to the Instruction Buffer
- 76 6.2. DMA0 Instruction Format
- 76 6.3. XRAM Addressing and Setup
- 77 6.4. Instruction Execution in Mode
- 78 6.5. Instruction Execution in Mode
- 79 6.6. Interrupt Sources
- 79 6.7. Data Buffer Overflow Warnings and Errors
- 87 7. 10-Bit ADC (ADC2, C8051F060/1/2/3)
- 88 7.1. Analog Multiplexer
- 89 7.2. Modes of Operation
- 89 7.2.1. Starting a Conversion
- 90 7.2.2. Tracking Modes
- 91 7.2.3. Settling Time Requirements
- 7 C8051F
- 97 7.3. Programmable Window Detector
- 99 7.3.1. Window Detector In Single-Ended Mode
- 100 7.3.2. Window Detector In Differential Mode
- 103 8. DACs, 12-Bit Voltage Mode (DAC0 and DAC1, C8051F060/1/2/3)
- 104 8.1. DAC Output Scheduling
- 104 8.1.1. Update Output On-Demand
- 104 8.1.2. Update Output Based on Timer Overflow
- 104 8.2. DAC Output Scaling/Justification
- 111 9. Voltage Reference 2 (C8051F060/2)
- 113 10. Voltage Reference 2 (C8051F061/3)
- 115 11. Voltage Reference 2 (C8051F064/5/6/7)
- 117 12. Comparators
- 119 12.1.Comparator Inputs
- 123 13. CIP-51 Microcontroller
- 125 13.1.Instruction Set
- 125 13.1.1.Instruction and CPU Timing
- 125 13.1.2.MOVX Instruction and Program Memory
- 130 13.2.Memory Organization
- 130 13.2.1.Program Memory
- 131 13.2.2.Data Memory
- 131 13.2.3.General Purpose Registers
- 131 13.2.4.Bit Addressable Locations
- 131 13.2.5.Stack
- 132 13.2.6.Special Function Registers
- 132 13.2.6.1.SFR Paging
- 132 13.2.6.2.Interrupts and SFR Paging
- 134 13.2.6.3.SFR Page Stack Example
- 148 13.2.7.Register Descriptions
- 151 13.3.Interrupt Handler
- 151 13.3.1.MCU Interrupt Sources and Vectors
- 151 13.3.2.External Interrupts
- 153 13.3.3.Interrupt Priorities
- 153 13.3.4.Interrupt Latency
- 154 13.3.5.Interrupt Register Descriptions
- 160 13.4.Power Management Modes
- 160 13.4.1.Idle Mode
- 161 13.4.2.Stop Mode
- 163 14. Reset Sources
- 164 14.1.Power-on Reset
- 164 14.2.Power-fail Reset
- 164 14.3.External Reset
- 165 14.4.Missing Clock Detector Reset
- 165 14.5.Comparator0 Reset
- 165 14.6.External CNVSTR2 Pin Reset
- 165 14.7.Watchdog Timer Reset
- 7 C8051F
- 166 14.7.1.Enable/Reset WDT
- 166 14.7.2.Disable WDT
- 166 14.7.3.Disable WDT Lockout
- 166 14.7.4.Setting WDT Interval
- 171 15. Oscillators
- 171 15.1.Programmable Internal Oscillator
- 173 15.2.External Oscillator Drive Circuit
- 173 15.3.System Clock Selection
- 175 15.4.External Crystal Example
- 175 15.5.External RC Example
- 175 15.6.External Capacitor Example
- 177 16. Flash Memory
- 177 16.1.Programming The Flash Memory
- 178 16.2.Non-volatile Data Storage
- 179 16.3.Security Options
- 183 16.3.1.Summary of Flash Security Options
- 187 17. External Data Memory Interface and On-Chip XRAM
- 187 17.1.Accessing XRAM
- 187 17.1.1.16-Bit MOVX Example
- 187 17.1.2.8-Bit MOVX Example
- 188 17.2.Configuring the External Memory Interface
- 188 17.3.Port Selection and Configuration
- 190 17.4.Multiplexed and Non-multiplexed Selection
- 190 17.4.1.Multiplexed Configuration
- 191 17.4.2.Non-multiplexed Configuration
- 192 17.5.Memory Mode Selection
- 192 17.5.1.Internal XRAM Only
- 192 17.5.2.Split Mode without Bank Select
- 193 17.5.3.Split Mode with Bank Select
- 193 17.5.4.External Only
- 194 17.6.Timing
- 196 17.6.1.Non-multiplexed Mode
- 196 17.6.1.1.16-bit MOVX: EMI0CF[4:2] = ‘101’, ‘110’, or
- 197 17.6.1.2.8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘101’ or
- 198 17.6.1.3.8-bit MOVX with Bank Select: EMI0CF[4:2]
- 199 17.6.2.Multiplexed Mode
- 199 17.6.2.1.16-bit MOVX: EMI0CF[4:2] = ‘001’, ‘010’, or
- 200 17.6.2.2.8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘001’ or
- 201 17.6.2.3.8-bit MOVX with Bank Select: EMI0CF[4:2]
- 203 18. Port Input/Output
- 205 18.1.Ports 0 through 3 and the Priority Crossbar Decoder
- 205 18.1.1.Crossbar Pin Assignment and Allocation
- 206 18.1.2.Configuring the Output Modes of the Port Pins
- 207 18.1.3.Configuring Port Pins as Digital Inputs
- 207 18.1.4.Weak Pull-ups
- 7 C8051F
- 207 18.1.5.Configuring Port 1 and 2 pins as Analog Inputs
- 208 18.1.6.Crossbar Pin Assignment Example
- 219 18.2.Ports 4 through 7 (C8051F060/2/4/6 only)
- 219 18.2.1.Configuring Ports which are not Pinned Out
- 219 18.2.2.Configuring the Output Modes of the Port Pins
- 219 18.2.3.Configuring Port Pins as Digital Inputs
- 219 18.2.4.Weak Pull-ups
- 220 18.2.5.External Memory Interface
- 225 19. Controller Area Network (CAN0, C8051F060/1/2/3)
- 227 19.1.Bosch CAN Controller Operation
- 228 19.2.CAN Registers
- 228 19.2.1.CAN Controller Protocol Registers
- 228 19.2.2.Message Object Interface Registers
- 228 19.2.3.Message Handler Registers
- 229 19.2.4.CIP-51 MCU Special Function Registers
- 229 19.2.6.CAN0ADR Autoincrement Feature
- 235 20. System Management BUS / I2C BUS (SMBUS0)
- 236 20.1.Supporting Documents
- 236 20.2.SMBus Protocol
- 237 20.2.1.Arbitration
- 237 20.2.2.Clock Low Extension
- 237 20.2.3.SCL Low Timeout
- 237 20.2.4.SCL High (SMBus Free) Timeout
- 238 20.3.SMBus Transfer Modes
- 238 20.3.1.Master Transmitter Mode
- 238 20.3.2.Master Receiver Mode
- 239 20.3.3.Slave Transmitter Mode
- 239 20.3.4.Slave Receiver Mode
- 241 20.4.SMBus Special Function Registers
- 241 20.4.1.Control Register
- 244 20.4.2.Clock Rate Register
- 245 20.4.3.Data Register
- 245 20.4.4.Address Register
- 246 20.4.5.Status Register
- 251 21. Enhanced Serial Peripheral Interface (SPI0)
- 252 21.1.Signal Descriptions
- 252 21.1.1.Master Out, Slave In (MOSI)
- 252 21.1.2.Master In, Slave Out (MISO)
- 252 21.1.3.Serial Clock (SCK)
- 252 21.1.4.Slave Select (NSS)
- 253 21.2.SPI0 Master Mode Operation
- 255 21.3.SPI0 Slave Mode Operation
- 255 21.4.SPI0 Interrupt Sources
- 7 C8051F
- 256 21.5.Serial Clock Timing
- 258 21.6.SPI Special Function Registers
- 265 22. UART
- 266 22.1.UART0 Operational Modes
- 266 22.1.1.Mode 0: Synchronous Mode
- 267 22.1.2.Mode 1: 8-Bit UART, Variable Baud Rate
- 269 22.1.3.Mode 2: 9-Bit UART, Fixed Baud Rate
- 270 22.1.4.Mode 3: 9-Bit UART, Variable Baud Rate
- 271 22.2.Multiprocessor Communications
- 271 22.2.1.Configuration of a Masked Address
- 271 22.2.2.Broadcast Addressing
- 272 22.3.Frame and Transmission Error Detection
- 277 23. UART
- 278 23.1.Enhanced Baud Rate Generation
- 279 23.2.Operational Modes
- 279 23.2.1.8-Bit UART
- 280 23.2.2.9-Bit UART
- 281 23.3.Multiprocessor Communications
- 287 24. Timers
- 287 24.1.Timer 0 and Timer
- 287 24.1.1.Mode 0: 13-bit Counter/Timer
- 289 24.1.2.Mode 1: 16-bit Counter/Timer
- 289 24.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload
- 290 24.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)
- 295 24.2.Timer 2, Timer 3, and Timer
- 295 24.2.1.Configuring Timer 2, 3, and 4 to Count Down
- 296 24.2.2.Capture Mode
- 297 24.2.3.Auto-Reload Mode
- 298 24.2.4.Toggle Output Mode
- 303 25. Programmable Counter Array
- 304 25.1.PCA Counter/Timer
- 305 25.2.Capture/Compare Modules
- 306 25.2.1.Edge-triggered Capture Mode
- 307 25.2.2.Software Timer (Compare) Mode
- 308 25.2.3.High Speed Output Mode
- 309 25.2.4.Frequency Output Mode
- 310 25.2.5.8-Bit Pulse Width Modulator Mode
- 311 25.2.6.16-Bit Pulse Width Modulator Mode
- 312 25.3.Register Descriptions for PCA
- 317 26. JTAG (IEEE 1149.1)
- 318 26.1.Boundary Scan
- 321 26.1.1.EXTEST Instruction
- 321 26.1.2.SAMPLE Instruction
- 321 26.1.3.BYPASS Instruction
- 321 26.1.4.IDCODE Instruction
- 318 C8051F
- 318 C8051F