C8051F060/1/2/3/4/5/6/7

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C8051F060/1/2/3/4/5/6/7 | Manualzz

C8051F060/1/2/3/4/5/6/7

25.1. PCA Counter/Timer

The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte

(MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” register.

Reading the PCA0L Register first guarantees an accurate reading of the entire 16-bit PCA0 counter. Reading PCA0H or PCA0L does not disturb the counter operation. The CPS2-CPS0 bits in the PCA0MD regis-

ter select the timebase for the counter/timer as shown in Table 25.1.

When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is set to logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in

PCA0MD to logic 1 enables the CF flag to generate an interrupt request. The CF bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by software (Note: PCA0 interrupts must be globally enabled before CF interrupts are recognized. PCA0 interrupts are globally enabled by setting the EA bit (IE.7) and the EPCA0 bit in EIE1 to logic 1). Clearing the

CIDL bit in the PCA0MD register allows the PCA to continue normal operation while the CPU is in Idle mode.

CPS2

0

0

0

0

1

1

CPS1

0

0

1

1

0

0

Table 25.1. PCA Timebase Input Options

CPS0 Timebase

0

1

0

System clock divided by 12

System clock divided by 4

1

Timer 0 overflow

High-to-low transitions on ECI (max rate = system clock divided by 4)

0

1

System clock

External oscillator source divided by 8 (synchronized with system clock)

Figure 25.2. PCA Counter/Timer Block Diagram

IDLE

304

PCA0MD

C

I

D

L

T

E

W

D

W

D

L

C

K

C

P

S

2

C

P

C

P

S

1

S

0

E

C

F

PCA0CN

C

F

C

R

C

C

F

5

C

C

F

4

C

C

F

3

C

C

F

2

C

C

C

C

F

1

F

0

SYSCLK/12

SYSCLK/4

Timer 0 Overflow

ECI

SYSCLK

External Clock/8

000

001

010

011

100

101

To SFR Bus

0

1

PCA0L read

Snapshot

Register

PCA0H PCA0L

Overflow

CF

To PCA Interrupt System

To PCA Modules

Rev. 1.2

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