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C8051F060/1/2/3/4/5/6/7
16.3. Security Options
The CIP-51 provides security options to protect the Flash memory from inadvertent modification by software as well as prevent the viewing of proprietary program code and constants. The Program Store Write
Enable (PSCTL.0) and the Program Store Erase Enable (PSCTL.1) bits protect the Flash memory from accidental modification by software. These bits must be explicitly set to logic 1 before software can write or erase the Flash memory. Additional security features prevent proprietary program code and data constants from being read or altered across the JTAG interface or by software running on the system controller.
A set of security lock bytes protect the Flash program memory from being read or altered across the JTAG interface. Each bit in a security lock-byte protects one 8k-byte block of memory. Clearing a bit to logic 0 in a Read Lock Byte prevents the corresponding block of Flash memory from being read across the JTAG interface. Clearing a bit in the Write/Erase Lock Byte protects the block from JTAG erasures and/or writes.
The Scratchpad area is read or write/erase locked when all bits in the corresponding security byte are cleared to logic 0.
On the C8051F060/1/2/3/4/5, the security lock bytes are located at 0xFBFE (Write/Erase Lock) and
0x7FFE (Write/Erase Lock) and 0x7FFF (Read Lock), as shown in Figure 16.2. The 512-byte sector con-
taining the lock bytes can be written to, but not erased, by software. An attempted read of a read-locked byte returns undefined data. Debugging code in a read-locked sector is not possible through the JTAG interface. The lock bits can always be read from and written to logic 0 regardless of the security setting applied to the block containing the security bytes. This allows additional blocks to be protected after the block containing the security bytes has been locked.
Important Note: To ensure protection from external access, the block containing the lock bytes must be Write/Erase locked. On the 64 k byte devices (C8051F060/1/2/3/4/5), the page containing the security bytes is 0xFA00-0xFBFF, and is locked by clearing bit 7 of the Write/Erase Lock Byte.
On the 32 k byte devices (C8051F066/7), the page containing the security bytes is 0x7E00-0x7FFF, and is locked by clearing bit 3 of the Write/Erase Lock Byte. If the page containing the security bytes is not Write/Erase locked, it is still possible to erase this page of Flash memory through the
JTAG port and reset the security bytes.
When the page containing the security bytes has been Write/Erase locked, a JTAG full device erase must be performed to unlock any areas of Flash protected by the security bytes. A JTAG full device erase is initiated by performing a normal JTAG erase operation on either of the security byte locations. This operation must be initiated through the JTAG port, and cannot be performed from firmware running on the device.
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C8051F060/1/2/3/4/5/6/7
Figure 16.1. C8051F060/1/2/3/4/5 Flash Program Memory Map and Security Bytes
Read and Write/Erase Security Bits
(Bit 7 is MSB)
Bit Memory Block
5
4
7
6
3
2
1
0
0xE000 - 0xFBFD
0xC000 - 0xDFFF
0xA000 - 0xBFFF
0x8000 - 0x9FFF
0x6000 - 0x7FFF
0x4000 - 0x5FFF
0x2000 - 0x3FFF
0x0000 - 0x1FFF
SFLE = 0
0xFFFF
Reserved
Read Lock Byte
Write/Erase Lock Byte
0xFC00
0xFBFF
0xFBFE
0xFBFD
Flash Access Limit
SFLE = 1
0x0000
0x007F
0x0000
Program/Data
Memory Space
Scratchpad Memory
(Data only)
Flash Read Lock Byte
Bits7-0: Each bit locks a corresponding block of memory. (Bit7 is MSB).
0: Read operations are locked (disabled) for corresponding block across the JTAG interface.
1: Read operations are unlocked (enabled) for corresponding block across the JTAG interface.
Flash Write/Erase Lock Byte
Bits7-0: Each bit locks a corresponding block of memory.
0: Write/Erase operations are locked (disabled) for corresponding block across the JTAG interface.
1: Write/Erase operations are unlocked (enabled) for corresponding block across the JTAG interface.
NOTE: When the block containing the security bytes is locked, the security bytes may be written but not erased.
Flash Access Limit
The Flash Access Limit is defined by the setting of the FLACL register, as described in
Figure 16.3. Firmware running at or above this address is prohibited from using the MOVX
and MOVC instructions to read, write, or erase Flash locations below this address.
180 Rev. 1.2
C8051F060/1/2/3/4/5/6/7
Figure 16.2. C8051F066/7 Flash Program Memory Map and Security Bytes
Read and Write/Erase Security Bits
(Bit 7 is MSB)
Bit Memory Block
1
0
3
2
7
6
5
4
N/A
N/A
N/A
N/A
0x6000 - 0x7FFD
0x4000 - 0x5FFF
0x2000 - 0x3FFF
0x0000 - 0x1FFF
SFLE = 0
Reserved
0xFFFF
Read Lock Byte
Write/Erase Lock Byte
0x8000
0x7FFF
0x7FFE
0x7FFD
Flash Access Limit
SFLE = 1
Program/Data
Memory Space
0x0000
Scratchpad Memory
(Data only)
0x007F
0x0000
Flash Read Lock Byte
Bits7-0: Each bit locks a corresponding block of memory.
0: Read operations are locked (disabled) for corresponding block across the JTAG interface.
1: Read operations are unlocked (enabled) for corresponding block across the JTAG interface.
Flash Write/Erase Lock Byte
Bits7-0: Each bit locks a corresponding block of memory.
0: Write/Erase operations are locked (disabled) for corresponding block across the JTAG interface.
1: Write/Erase operations are unlocked (enabled) for corresponding block across the JTAG interface.
NOTE: When the block containing the security bytes is locked, the security bytes may be written but not erased.
Flash Access Limit Register (FLACL)
The Flash Access Limit is defined by the setting of the FLACL register, as described in
Figure 16.3. Firmware running at or above this address is prohibited from using the MOVX
and MOVC instructions to read, write, or erase Flash locations below this address.
being read by software running on the C8051F060/1/2/3/4/5/6/7. This feature provides support for OEMs that wish to program the MCU with proprietary value-added firmware before distribution. The value-added firmware can be protected while allowing additional code to be programmed in remaining program memory space later.
The Flash Access Limit (FAL) is a 16-bit address that establishes two logical partitions in the program memory space. The first is an upper partition consisting of all the program memory locations at or above the FAL address, and the second is a lower partition consisting of all the program memory locations start-
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C8051F060/1/2/3/4/5/6/7
ing at 0x0000 up to (but excluding) the FAL address. Software in the upper partition can execute code in the lower partition, but is prohibited from reading locations in the lower partition using the MOVC instruction. (Executing a MOVC instruction from the upper partition with a source address in the lower partition will always return a data value of 0x00.) Software running in the lower partition can access locations in both the upper and lower partition without restriction.
The Value-added firmware should be placed in the lower partition. On reset, control is passed to the valueadded firmware via the reset vector. Once the value-added firmware completes its initial execution, it branches to a predetermined location in the upper partition. If entry points are published, software running in the upper partition may execute program code in the lower partition, but it cannot read the contents of the lower partition. Parameters may be passed to the program code running in the lower partition either through the typical method of placing them on the stack or in registers before the call or by placing them in prescribed memory locations in the upper partition.
The FAL address is specified using the contents of the Flash Access Limit Register. The 16-bit FAL address is calculated as 0xNN00, where NN is the contents of the FAL Security Register. Thus, the FAL can be located on 256-byte boundaries anywhere in program memory space. However, the 512-byte erase sector size essentially requires that a 512 boundary be used. The contents of a non-initialized FAL security byte is 0x00, thereby setting the FAL address to 0x0000 and allowing read access to all locations in program memory space by default.
Figure 16.3. FLACL: Flash Access Limit
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
Reset Value
00000000
SFR
Address:
SFR Address: 0xB7
SFR Page: F
Bits 7-0: FLACL: Flash Access Limit.
This register holds the high byte of the 16-bit program memory read/write/erase limit address. The entire 16-bit access limit address value is calculated as 0xNN00 where NN is replaced by contents of FLACL. A write to this register sets the Flash Access Limit. This register can only be written once after any reset. Any subsequent writes are ignored until the next reset. To fully protect all addresses below this limit, bit 0 of FLACL should be
set to ‘0’ to align the FAL on a 512-byte Flash page boundary.
182 Rev. 1.2
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Table of contents
- 7 C8051F
- 19 1. System Overview
- 25 1.1. CIP-51™ Microcontroller Core
- 25 1.1.1. Fully 8051 Compatible
- 25 1.1.2. Improved Throughput
- 26 1.1.3. Additional Features
- 27 1.2. On-Chip Memory
- 28 1.3. JTAG Debug and Boundary Scan
- 29 1.4. Programmable Digital I/O and Crossbar
- 30 1.5. Programmable Counter Array
- 31 1.6. Controller Area Network
- 32 1.7. Serial Ports
- 33 1.8. 16-Bit Analog to Digital Converters
- 34 1.9. 10-Bit Analog to Digital Converter
- 35 1.10.12-bit Digital to Analog Converters
- 36 1.11.Analog Comparators
- 37 2. Absolute Maximum Ratings
- 38 3. Global DC Electrical Characteristics
- 39 4. Pinout and Package Definitions
- 51 5. 16-Bit ADCs (ADC0 and ADC1)
- 52 5.1. Single-Ended or Differential Operation
- 52 5.1.1. Pseudo-Differential Inputs
- 53 5.2. Voltage Reference
- 54 5.3. ADC Modes of Operation
- 54 5.3.1. Starting a Conversion
- 54 5.3.2. Tracking Modes
- 56 5.3.3. Settling Time Requirements
- 66 5.4. Calibration
- 69 5.5. ADC0 Programmable Window Detector
- 75 6. Direct Memory Access Interface (DMA0)
- 75 6.1. Writing to the Instruction Buffer
- 76 6.2. DMA0 Instruction Format
- 76 6.3. XRAM Addressing and Setup
- 77 6.4. Instruction Execution in Mode
- 78 6.5. Instruction Execution in Mode
- 79 6.6. Interrupt Sources
- 79 6.7. Data Buffer Overflow Warnings and Errors
- 87 7. 10-Bit ADC (ADC2, C8051F060/1/2/3)
- 88 7.1. Analog Multiplexer
- 89 7.2. Modes of Operation
- 89 7.2.1. Starting a Conversion
- 90 7.2.2. Tracking Modes
- 91 7.2.3. Settling Time Requirements
- 7 C8051F
- 97 7.3. Programmable Window Detector
- 99 7.3.1. Window Detector In Single-Ended Mode
- 100 7.3.2. Window Detector In Differential Mode
- 103 8. DACs, 12-Bit Voltage Mode (DAC0 and DAC1, C8051F060/1/2/3)
- 104 8.1. DAC Output Scheduling
- 104 8.1.1. Update Output On-Demand
- 104 8.1.2. Update Output Based on Timer Overflow
- 104 8.2. DAC Output Scaling/Justification
- 111 9. Voltage Reference 2 (C8051F060/2)
- 113 10. Voltage Reference 2 (C8051F061/3)
- 115 11. Voltage Reference 2 (C8051F064/5/6/7)
- 117 12. Comparators
- 119 12.1.Comparator Inputs
- 123 13. CIP-51 Microcontroller
- 125 13.1.Instruction Set
- 125 13.1.1.Instruction and CPU Timing
- 125 13.1.2.MOVX Instruction and Program Memory
- 130 13.2.Memory Organization
- 130 13.2.1.Program Memory
- 131 13.2.2.Data Memory
- 131 13.2.3.General Purpose Registers
- 131 13.2.4.Bit Addressable Locations
- 131 13.2.5.Stack
- 132 13.2.6.Special Function Registers
- 132 13.2.6.1.SFR Paging
- 132 13.2.6.2.Interrupts and SFR Paging
- 134 13.2.6.3.SFR Page Stack Example
- 148 13.2.7.Register Descriptions
- 151 13.3.Interrupt Handler
- 151 13.3.1.MCU Interrupt Sources and Vectors
- 151 13.3.2.External Interrupts
- 153 13.3.3.Interrupt Priorities
- 153 13.3.4.Interrupt Latency
- 154 13.3.5.Interrupt Register Descriptions
- 160 13.4.Power Management Modes
- 160 13.4.1.Idle Mode
- 161 13.4.2.Stop Mode
- 163 14. Reset Sources
- 164 14.1.Power-on Reset
- 164 14.2.Power-fail Reset
- 164 14.3.External Reset
- 165 14.4.Missing Clock Detector Reset
- 165 14.5.Comparator0 Reset
- 165 14.6.External CNVSTR2 Pin Reset
- 165 14.7.Watchdog Timer Reset
- 7 C8051F
- 166 14.7.1.Enable/Reset WDT
- 166 14.7.2.Disable WDT
- 166 14.7.3.Disable WDT Lockout
- 166 14.7.4.Setting WDT Interval
- 171 15. Oscillators
- 171 15.1.Programmable Internal Oscillator
- 173 15.2.External Oscillator Drive Circuit
- 173 15.3.System Clock Selection
- 175 15.4.External Crystal Example
- 175 15.5.External RC Example
- 175 15.6.External Capacitor Example
- 177 16. Flash Memory
- 177 16.1.Programming The Flash Memory
- 178 16.2.Non-volatile Data Storage
- 179 16.3.Security Options
- 183 16.3.1.Summary of Flash Security Options
- 187 17. External Data Memory Interface and On-Chip XRAM
- 187 17.1.Accessing XRAM
- 187 17.1.1.16-Bit MOVX Example
- 187 17.1.2.8-Bit MOVX Example
- 188 17.2.Configuring the External Memory Interface
- 188 17.3.Port Selection and Configuration
- 190 17.4.Multiplexed and Non-multiplexed Selection
- 190 17.4.1.Multiplexed Configuration
- 191 17.4.2.Non-multiplexed Configuration
- 192 17.5.Memory Mode Selection
- 192 17.5.1.Internal XRAM Only
- 192 17.5.2.Split Mode without Bank Select
- 193 17.5.3.Split Mode with Bank Select
- 193 17.5.4.External Only
- 194 17.6.Timing
- 196 17.6.1.Non-multiplexed Mode
- 196 17.6.1.1.16-bit MOVX: EMI0CF[4:2] = ‘101’, ‘110’, or
- 197 17.6.1.2.8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘101’ or
- 198 17.6.1.3.8-bit MOVX with Bank Select: EMI0CF[4:2]
- 199 17.6.2.Multiplexed Mode
- 199 17.6.2.1.16-bit MOVX: EMI0CF[4:2] = ‘001’, ‘010’, or
- 200 17.6.2.2.8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘001’ or
- 201 17.6.2.3.8-bit MOVX with Bank Select: EMI0CF[4:2]
- 203 18. Port Input/Output
- 205 18.1.Ports 0 through 3 and the Priority Crossbar Decoder
- 205 18.1.1.Crossbar Pin Assignment and Allocation
- 206 18.1.2.Configuring the Output Modes of the Port Pins
- 207 18.1.3.Configuring Port Pins as Digital Inputs
- 207 18.1.4.Weak Pull-ups
- 7 C8051F
- 207 18.1.5.Configuring Port 1 and 2 pins as Analog Inputs
- 208 18.1.6.Crossbar Pin Assignment Example
- 219 18.2.Ports 4 through 7 (C8051F060/2/4/6 only)
- 219 18.2.1.Configuring Ports which are not Pinned Out
- 219 18.2.2.Configuring the Output Modes of the Port Pins
- 219 18.2.3.Configuring Port Pins as Digital Inputs
- 219 18.2.4.Weak Pull-ups
- 220 18.2.5.External Memory Interface
- 225 19. Controller Area Network (CAN0, C8051F060/1/2/3)
- 227 19.1.Bosch CAN Controller Operation
- 228 19.2.CAN Registers
- 228 19.2.1.CAN Controller Protocol Registers
- 228 19.2.2.Message Object Interface Registers
- 228 19.2.3.Message Handler Registers
- 229 19.2.4.CIP-51 MCU Special Function Registers
- 229 19.2.6.CAN0ADR Autoincrement Feature
- 235 20. System Management BUS / I2C BUS (SMBUS0)
- 236 20.1.Supporting Documents
- 236 20.2.SMBus Protocol
- 237 20.2.1.Arbitration
- 237 20.2.2.Clock Low Extension
- 237 20.2.3.SCL Low Timeout
- 237 20.2.4.SCL High (SMBus Free) Timeout
- 238 20.3.SMBus Transfer Modes
- 238 20.3.1.Master Transmitter Mode
- 238 20.3.2.Master Receiver Mode
- 239 20.3.3.Slave Transmitter Mode
- 239 20.3.4.Slave Receiver Mode
- 241 20.4.SMBus Special Function Registers
- 241 20.4.1.Control Register
- 244 20.4.2.Clock Rate Register
- 245 20.4.3.Data Register
- 245 20.4.4.Address Register
- 246 20.4.5.Status Register
- 251 21. Enhanced Serial Peripheral Interface (SPI0)
- 252 21.1.Signal Descriptions
- 252 21.1.1.Master Out, Slave In (MOSI)
- 252 21.1.2.Master In, Slave Out (MISO)
- 252 21.1.3.Serial Clock (SCK)
- 252 21.1.4.Slave Select (NSS)
- 253 21.2.SPI0 Master Mode Operation
- 255 21.3.SPI0 Slave Mode Operation
- 255 21.4.SPI0 Interrupt Sources
- 7 C8051F
- 256 21.5.Serial Clock Timing
- 258 21.6.SPI Special Function Registers
- 265 22. UART
- 266 22.1.UART0 Operational Modes
- 266 22.1.1.Mode 0: Synchronous Mode
- 267 22.1.2.Mode 1: 8-Bit UART, Variable Baud Rate
- 269 22.1.3.Mode 2: 9-Bit UART, Fixed Baud Rate
- 270 22.1.4.Mode 3: 9-Bit UART, Variable Baud Rate
- 271 22.2.Multiprocessor Communications
- 271 22.2.1.Configuration of a Masked Address
- 271 22.2.2.Broadcast Addressing
- 272 22.3.Frame and Transmission Error Detection
- 277 23. UART
- 278 23.1.Enhanced Baud Rate Generation
- 279 23.2.Operational Modes
- 279 23.2.1.8-Bit UART
- 280 23.2.2.9-Bit UART
- 281 23.3.Multiprocessor Communications
- 287 24. Timers
- 287 24.1.Timer 0 and Timer
- 287 24.1.1.Mode 0: 13-bit Counter/Timer
- 289 24.1.2.Mode 1: 16-bit Counter/Timer
- 289 24.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload
- 290 24.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)
- 295 24.2.Timer 2, Timer 3, and Timer
- 295 24.2.1.Configuring Timer 2, 3, and 4 to Count Down
- 296 24.2.2.Capture Mode
- 297 24.2.3.Auto-Reload Mode
- 298 24.2.4.Toggle Output Mode
- 303 25. Programmable Counter Array
- 304 25.1.PCA Counter/Timer
- 305 25.2.Capture/Compare Modules
- 306 25.2.1.Edge-triggered Capture Mode
- 307 25.2.2.Software Timer (Compare) Mode
- 308 25.2.3.High Speed Output Mode
- 309 25.2.4.Frequency Output Mode
- 310 25.2.5.8-Bit Pulse Width Modulator Mode
- 311 25.2.6.16-Bit Pulse Width Modulator Mode
- 312 25.3.Register Descriptions for PCA
- 317 26. JTAG (IEEE 1149.1)
- 318 26.1.Boundary Scan
- 321 26.1.1.EXTEST Instruction
- 321 26.1.2.SAMPLE Instruction
- 321 26.1.3.BYPASS Instruction
- 321 26.1.4.IDCODE Instruction
- 318 C8051F
- 318 C8051F