C8051F060/1/2/3/4/5/6/7

C8051F060/1/2/3/4/5/6/7

25.2.5. 8-Bit Pulse Width Modulator Mode

Each module can be used independently to generate pulse width modulated (PWM) outputs on its associated CEXn pin. The frequency of the output is dependent on the timebase for the PCA0 counter/timer. The duty cycle of the PWM output signal is varied using the module's PCA0CPLn capture/compare register.

When the value in the low byte of the PCA0 counter/timer (PCA0L) is equal to the value in PCA0CPLn, the output on the CEXn pin will be high. When the count value in PCA0L overflows, the CEXn output will be

low (see Figure 25.8). Also, when the counter/timer low byte (PCA0L) overflows from 0xFF to 0x00,

PCA0CPLn is reloaded automatically with the value stored in the counter/timer's high byte (PCA0H) without software intervention. Setting the ECOMn and PWMn bits in the PCA0CPMn register enables 8-Bit

Pulse Width Modulator mode. The duty cycle for 8-Bit PWM Mode is given by Equation 25.2.

Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/

Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit to ‘0’; writing to PCA0CPHn sets ECOMn to ‘1’.

Equation 25.2. 8-Bit PWM Duty Cycle

DutyCycle

=

(

256 –

PCA0CPHn

256

)

Figure 25.8. PCA 8-Bit PWM Mode Diagram

PCA0CPHn

PCA0CPMn

M

1

P

W

6 n

E

C

O

C

A

P

M P n n n

C M

A A

T

O

P

N

T n

G n

M n

P

W

E

C

C

F n

0 0 0 0 0 0

PCA0CPLn

Enable

PCA Timebase

8-bit

Comparator

PCA0L

Overflow match

S

SET

Q

R

CLR

Q

CEXn

Crossbar Port I/O

310 Rev. 1.2