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C8051F060/1/2/3/4/5/6/7
21.3. SPI0 Slave Mode Operation
When SPI0 is enabled and not configured as a master, it will operate as a SPI slave. As a slave, bytes are shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK signal. A bit counter in the SPI0 logic counts SCK edges. When 8 bits have been shifted through the shift register, the SPIF flag is set to logic 1, and the byte is copied into the receive buffer. Data is read from the receive buffer by reading SPI0DAT. A slave device cannot initiate transfers. Data to be transferred to the master device is pre-loaded into the shift register by writing to SPI0DAT. Writes to SPI0DAT are doublebuffered, and are placed in the transmit buffer first. If the shift register is empty, the contents of the transmit buffer will immediately be transferred into the shift register. When the shift register already contains data, the SPI will load the shift register with the transmit buffer’s contents after the last SCK edge of the next (or current) SPI transfer.
When configured as a slave, SPI0 can be configured for 4-wire or 3-wire operation. The default, 4-wire slave mode, is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 1. In 4-wire mode, the
NSS signal is routed to a port pin and configured as a digital input. SPI0 is enabled when NSS is logic 0, and disabled when NSS is logic 1. The bit counter is reset on a falling edge of NSS. Note that the NSS signal must be driven low at least 2 system clocks before the first active edge of SCK for each byte transfer.
Figure 21.4 shows a connection diagram between two slave devices in 4-wire slave mode and a master
device.
3-wire slave mode is active when NSSMD1 (SPI0CN.3) = 0 and NSSMD0 (SPI0CN.2) = 0. NSS is not used in this mode, and is not mapped to an external port pin through the crossbar. Since there is no way of uniquely addressing the device in 3-wire slave mode, SPI0 must be the only slave device present on the bus. It is important to note that in 3-wire slave mode there is no external means of resetting the bit counter that determines when a full byte has been received. The bit counter can only be reset by disabling and re-
wire slave mode and a master device.
21.4. SPI0 Interrupt Sources
When SPI0 interrupts are enabled, the following four flags will generate an interrupt when they are set to logic 1:
Note that all of the following bits must be cleared by software.
1.
The SPI Interrupt Flag, SPIF (SPI0CN.7) is set to logic 1 at the end of each byte transfer. This flag can occur in all SPI0 modes.
2.
The Write Collision Flag, WCOL (SPI0CN.6) is set to logic 1 if a write to SPI0DAT is attempted when the transmit buffer has not been emptied to the SPI shift register. When this occurs, the write to SPI0DAT will be ignored, and the transmit buffer will not be written.This flag can occur in all SPI0 modes.
3.
The Mode Fault Flag MODF (SPI0CN.5) is set to logic 1 when SPI0 is configured as a master, and for multi-master mode and the NSS pin is pulled low. When a Mode Fault occurs, the
MSTEN and SPIEN bits in SPI0CN are set to logic 0 to disable SPI0 and allow another master device to access the bus.
4.
The Receive Overrun Flag RXOVRN (SPI0CN.4) is set to logic 1 when configured as a slave, and a transfer is completed and the receive buffer still holds an unread byte from a previous transfer. The new byte is not transferred to the receive buffer, allowing the previously received data byte to be read. The data byte which caused the overrun is lost.
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21.5. Serial Clock Timing
Four combinations of serial clock phase and polarity can be selected using the clock control bits in the
SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases
(edge used to latch the data). The CKPOL bit (SPI0CFG.4) selects between an active-high or active-low clock. Both master and slave devices must be configured to use the same clock phase and polarity. SPI0 should be disabled (by clearing the SPIEN bit, SPI0CN.0) when changing the clock phase or polarity. The
the master and slave SPI when communicating between two of the following devices: C8051F04x,
C8051F06x, C8051F12x, C8051F31x, C8051F32x, and C8051F33x
frequency. This register is ignored when operating in slave mode. When the SPI is configured as a master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency or 12.5 MHz, whichever is slower. When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the system clock frequency, provided that the master issues SCK, NSS (in 4-wire slave mode), and the serial input data synchronously with the slave’s system clock. If the master issues SCK,
NSS, and the serial input data asynchronously, the maximum data transfer rate (bits/sec) must be less than 1/10 the system clock frequency. In the special case where the master only wants to transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the SPI slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. This is provided that the master issues SCK, NSS, and the serial input data synchronously with the slave’s system clock.
Figure 21.5. Master Mode Data/Clock Timing
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=0)
SCK
(CKPOL=1, CKPHA=1)
MISO/MOSI
NSS (Must Remain High in Multi-Master Mode)
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
256 Rev. 1.2
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Figure 21.6. Slave Mode Data/Clock Timing (CKPHA = 0)
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=1, CKPHA=0)
MOSI
MISO
NSS (4-Wire Mode)
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Figure 21.7. Slave Mode Data/Clock Timing (CKPHA = 1)
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=1)
MOSI
MISO
NSS (4-Wire Mode)
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
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21.6. SPI Special Function Registers
SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN
Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate
Register. The four special function registers related to the operation of the SPI0 Bus are described in the following figures.
Figure 21.8. SPI0CFG: SPI0 Configuration Register
R
SPIBSY
Bit7
R/W
MSTEN
Bit6
R/W
CKPHA
Bit5
R/W
CKPOL
Bit4
R
SLVSEL
Bit3
R
NSSIN
Bit2
R
SRMT
Bit1
R
RXBMT
Bit0
Reset Value
00000111
SFR Address: 0x9A
SFR Page: 0
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
SPIBSY: SPI Busy (read only).
This bit is set to logic 1 when a SPI transfer is in progress (Master or slave Mode).
MSTEN: Master Mode Enable.
0: Disable master mode. Operate in slave mode.
1: Enable master mode. Operate as a master.
CKPHA: SPI0 Clock Phase.
This bit controls the SPI0 clock phase.
0: Data centered on first edge of SCK period.
†
1: Data centered on second edge of SCK period.
†
CKPOL: SPI0 Clock Polarity.
This bit controls the SPI0 clock polarity.
0: SCK line low in idle state.
1: SCK line high in idle state.
SLVSEL: Slave Selected Flag (read only).
This bit is set to logic 1 whenever the NSS pin is low indicating SPI0 is the selected slave. It is cleared to logic 0 when NSS is high (slave not selected). This bit does not indicate the instantaneous value at the NSS pin, but rather a de-glitched version of the pin input.
NSSIN: NSS Instantaneous Pin Input (read only).
This bit mimics the instantaneous value that is present on the NSS port pin at the time that the register is read. This input is not de-glitched.
SRMT: Shift Register Empty (Valid in Slave Mode, read only).
This bit will be set to logic 1 when all data has been transferred in/out of the shift register, and there is no new information available to read from the transmit buffer or write to the receive buffer. It returns to logic 0 when a data byte is transferred to the shift register from the transmit buffer or by a transition on SCK.
NOTE: SRMT = 1 when in Master Mode.
RXBMT: Receive Buffer Empty (Valid in Slave Mode, read only).
This bit will be set to logic 1 when the receive buffer has been read and contains no new information. If there is new information available in the receive buffer that has not been read, this bit will return to logic 0.
NOTE: RXBMT = 1 when in Master Mode.
†
In slave mode, data on MOSI is sampled in the center of each data bit. In master mode, data on MISO is sampled one SYSCLK before the end of each data bit, to provide maximum settling time for the slave
device. See Table 21.1 for timing parameters.
258 Rev. 1.2
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Figure 21.9. SPI0CN: SPI0 Control Register
R/W
SPIF
Bit7
R/W
WCOL
Bit6
R/W
MODF
Bit5
R/W R/W R/W R
RXOVRN NSSMD1 NSSMD0 TXBMT
Bit4 Bit3 Bit2 Bit1
R/W
SPIEN
Reset Value
00000110
Bit0
Bit
Addressable
SFR Address: 0xF8
SFR Page: 0
Bit 7:
Bit 6:
Bit 5:
Bit 4:
SPIF: SPI0 Interrupt Flag.
This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are enabled, setting this bit causes the CPU to vector to the SPI0 interrupt service routine. This bit is not automatically cleared by hardware. It must be cleared by software.
WCOL: Write Collision Flag.
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) to indicate a write to the SPI0 data register was attempted while a data transfer was in progress. It must be cleared by software.
MODF: Mode Fault Flag.
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when a master mode collision is detected (NSS is low, MSTEN = 1, and NSSMD[1:0] = 01). This bit is not automatically cleared by hardware. It must be cleared by software.
RXOVRN: Receive Overrun Flag (Slave Mode only).
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when the receive buffer still holds unread data from a previous transfer and the last bit of the current transfer is shifted into the SPI0 shift register. This bit is not automatically cleared by hardware. It must be cleared by software.
Bits 3-2: NSSMD1-NSSMD0: Slave Select Mode.
Selects between the following NSS operation modes:
(See
Section “21.2. SPI0 Master Mode Operation” on page 253
Slave Mode Operation” on page 255
).
00: 3-Wire Slave or 3-wire Master Mode. NSS signal is not routed to a port pin.
01: 4-Wire Slave or Multi-Master Mode (Default). NSS is always an input to the device.
1x: 4-Wire Single-Master Mode. NSS signal is mapped as an output from the device and will
Bit 1:
Bit 0: assume the value of NSSMD0.
TXBMT: Transmit Buffer Empty.
This bit will be set to logic 0 when new data has been written to the transmit buffer. When data in the transmit buffer is transferred to the SPI shift register, this bit will be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer.
SPIEN: SPI0 Enable.
This bit enables/disables the SPI.
0: SPI disabled.
1: SPI enabled.
Rev. 1.2
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Figure 21.10. SPI0CKR: SPI0 Clock Rate Register
R/W
SCR7
Bit7
R/W
SCR6
Bit6
R/W
SCR5
Bit5
R/W
SCR4
Bit4
R/W
SCR3
Bit3
R/W
SCR2
Bit2
R/W
SCR1
Bit1
R/W
SCR0
Reset Value
00000000
Bit0
SFR Address: 0x9D
SFR Page: 0
Bits 7-0: SCR7-SCR0: SPI0 Clock Rate.
These bits determine the frequency of the SCK output when the SPI0 module is configured for master mode operation. The SCK clock frequency is a divided version of the system clock, and is given in the following equation, where SYSCLK is the system clock frequency and SPI0CKR is the 8-bit value held in the SPI0CKR register.
f
SCK
=
2
× (
SPI0CKR
+ 1
) for 0 <= SPI0CKR <= 255
Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04,
f
SCK
=
2
× (
4 + 1
)
f
SCK
= 200kHz
260 Rev. 1.2
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Figure 21.11. SPI0DAT: SPI0 Data Register
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W Reset Value
00000000
Bit0
SFR Address: 0x9B
SFR Page: 0
Bits 7-0: SPI0DAT: SPI0 Transmit and Receive Data.
The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to SPI0DAT places the data into the transmit buffer and initiates a transfer when in Master Mode. A read of SPI0DAT returns the contents of the receive buffer.
Rev. 1.2
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Figure 21.12. SPI Master Timing (CKPHA = 0)
SCK*
T
MCKH
T
MCKL
T
MIS
T
MIH
MISO
MOSI
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
Figure 21.13. SPI Master Timing (CKPHA = 1)
SCK*
T
MCKH
T
MIS
T
MCKL
T
MIH
MISO
MOSI
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
262 Rev. 1.2
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Figure 21.14. SPI Slave Timing (CKPHA = 0)
NSS
T
SE
T
CKL
SCK*
T
CKH
T
SIS
T
SIH
MOSI
T
SEZ
T
SOH
MISO
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
T
SD
T
SDZ
Figure 21.15. SPI Slave Timing (CKPHA = 1)
NSS
T
SE
T
CKL
SCK*
T
CKH
T
SIS
T
SIH
MOSI
T
SEZ
MISO
T
SOH
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
T
SLH
T
SD
T
SDZ
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Table 21.1. SPI Slave Timing Parameters
Parameter Description
Master Mode Timing
†
(See Figure 21.12 and Figure 21.13)
T
T
MCKL
T
MCKH
MIS
SCK High Time
SCK Low Time
MISO Valid to SCK Shift Edge
Min
1*T
SYSCLK
1*T
SYSCLK
1*T
SYSCLK
+
20
0
T
MIH
Slave Mode Timing
†
(See Figure 21.14 and Figure 21.15)
T
SE
T
SD
SCK Shift Edge to MISO Change
NSS Falling to First SCK Edge
Last SCK Edge to NSS Rising
NSS Falling to MISO Valid
T
SEZ
T
SDZ
T
CKH
T
CKL
NSS Rising to MISO High-Z
SCK High Time
SCK Low Time
2*T
2*T
SYSCLK
SYSCLK
T
SIS
T
SIH
T
SOH
MOSI Valid to SCK Sample Edge
SCK Sample Edge to MOSI Change
SCK Shift Edge to MISO Change
5*T
SYSCLK
5*T
SYSCLK
2*T
2*T
SYSCLK
SYSCLK
T
SLH
Last SCK Edge to MISO Change (CKPHA = 1
ONLY)
†
T
SYSCLK
is equal to one period of the device system clock (SYSCLK).
6*T
SYSCLK
Max
4*T
SYSCLK
4*T
SYSCLK
4*T
SYSCLK
8*T
SYSCLK
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
264 Rev. 1.2
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22.
UART0
UART0 is an enhanced serial port with frame error detection and address recognition hardware. UART0 may operate in full-duplex asynchronous or half-duplex synchronous modes, and mutiproccessor communication is fully supported. Receive data is buffered in a holding register, allowing UART0 to start reception of a second incoming data byte before software has finished reading the previous data byte. A Receive
Overrun bit indicates when new received data is latched into the receive buffer before the previously received byte has been read.
UART0 is accessed via its associated SFRs, Serial Control (SCON0) and Serial Data Buffer (SBUF0). The single SBUF0 location provides access to both transmit and receive registers. Reading SCON0 accesses the Receive register and writing SCON0 accesses the Transmit register.
UART0 may be operated in polled or interrupt mode. UART0 has two sources of interrupts: a Transmit
Interrupt flag, TI0 (SCON0.1) set when transmission of a data byte is complete, and a Receive Interrupt flag, RI0 (SCON0.0) set when reception of a data byte is complete. UART0 interrupt flags are not cleared by hardware when the CPU vectors to the interrupt service routine; they must be cleared manually by software. This allows software to determine the cause of the UART0 interrupt (transmit complete or receive complete).
Figure 22.1. UART0 Block Diagram
SFR Bus
Write to
SBUF0
TB80
F
E
0 O
V
R
X
0
C
O
T
X
L
0
SSTA0
S
M
O
D
0 L
K
1
S
0
T
C
L
K
1
S
0
T
C
L
K
1
R
C
S
0
L
K
1
S
0
R
C
UART0
Baud Rate Generation
Logic
SET
D
CLR
Q
SBUF0
Zero Detector
Stop Bit
Gen.
Start
Tx Clock
Rx Clock
Start
Shift
Tx Control
Tx IRQ
S
M
0
0
S
M
1
0
SCON0
S
M
2
0
R
E
N
0
T
B
8
0
R
B
8
0
T
I
0
R
I
0
Data
Send
TI0
EN
Rx Control
Shift
Rx IRQ
0x1FF
Load
SBUF
Address
Match
RI0
TX0
Crossbar
Serial Port
(UART0) Interrupt
Port I/O
Frame Error
Detection
Load
SBUF0
Input Shift Register
(9 bits)
SBUF0
RB80
Read
SBUF0
Match Detect
SADDR0
SADEN0
SFR Bus
RX0
Crossbar
Rev. 1.2
265
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22.1. UART0 Operational Modes
UART0 provides four operating modes (one synchronous and three asynchronous) selected by setting configuration bits in the SCON0 register. These four modes offer different baud rates and communication
protocols. The four modes are summarized in Table 22.1.
Mode Synchronization
0
1
Synchronous
Asynchronous
2
3
Asynchronous
Asynchronous
Table 22.1. UART0 Modes
Baud Clock
SYSCLK / 12
Timer 1, 2, 3, or 4 Overflow
SYSCLK / 32 or SYSCLK / 64
Timer 1, 2, 3, or 4 Overflow
Data Bits Start/Stop Bits
8
8
None
1 Start, 1 Stop
9
9
1 Start, 1 Stop
1 Start, 1 Stop
22.1.1. Mode 0: Synchronous Mode
Mode 0 provides synchronous, half-duplex communication. Serial data is transmitted and received on the
RX0 pin. The TX0 pin provides the shift clock for both transmit and receive. The MCU must be the master since it generates the shift clock for transmission in both directions (see the interconnect diagram in
Data transmission begins when an instruction writes a data byte to the SBUF0 register. Eight data bits are
transferred LSB first (see the timing diagram in Figure 22.2), and the TI0 Transmit Interrupt Flag
(SCON0.1) is set at the end of the eighth bit time. Data reception begins when the REN0 Receive Enable bit (SCON0.4) is set to logic 1 and the RI0 Receive Interrupt Flag (SCON0.0) is cleared. One cycle after the eighth bit is shifted in, the RI0 flag is set and reception stops until software clears the RI0 bit. An interrupt will occur if enabled when either TI0 or RI0 are set.
266 Rev. 1.2
C8051F060/1/2/3/4/5/6/7
The Mode 0 baud rate is SYSCLK / 12. RX0 is forced to open-drain in Mode 0, and an external pull-up will typically be required.
Figure 22.2. UART0 Mode 0 Timing Diagram
D0 D1
MODE 0 TRANSMIT
D2 D3 D4 D5 D6 D7
RX (data out)
TX (clk out)
D1
MODE 0 RECEIVE
D2 D3 D4
RX (data in)
D0 D5
TX (clk out)
Figure 22.3. UART0 Mode 0 Interconnect
TX
C8051Fxxx
RX
CLK
DATA
Shift
Reg.
D6 D7
8 Extra Outputs
22.1.2. Mode 1: 8-Bit UART, Variable Baud Rate
Mode 1 provides standard asynchronous, full duplex communication using a total of 10 bits per data byte: one start bit, eight data bits (LSB first), and one stop bit. Data are transmitted from the TX0 pin and received at the RX0 pin. On receive, the eight data bits are stored in SBUF0 and the stop bit goes into
RB80 (SCON0.2).
Data transmission begins when an instruction writes a data byte to the SBUF0 register. The TI0 Transmit
Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to logic 1. After the stop bit is received, the data byte will be loaded into the SBUF0 receive register if the following conditions are met: RI0 must be logic 0, and if SM20 is logic 1, the stop bit must be logic 1.
If these conditions are met, the eight bits of data is stored in SBUF0, the stop bit is stored in RB80 and the
RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not be set. An interrupt will occur if enabled when either TI0 or RI0 are set.
Figure 22.4. UART0 Mode 1 Timing Diagram
MARK
SPACE
BIT TIMES
START
BIT
BIT SAMPLING
D0 D1 D2 D3 D4 D5 D6 D7
STOP
BIT
Rev. 1.2
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The baud rate generated in Mode 1 is a function of timer overflow. UART0 can use Timer 1 operating in 8-
Bit Auto-Reload Mode, or Timer 2, 3, or 4 operating in Auto-reload Mode to generate the baud rate (note that the TX and RX clocks are selected separately). On each timer overflow event (a rollover from all ones
- (0xFF for Timer 1, 0xFFFF for Timer 2, 3, or 4) - to zero) a clock is sent to the baud rate logic.
The transmit baud rate clock is selected using the S0TCLK1 and S0TCLK0 bits, and the receive baud rate clock is selected using the S0RCLK1 and S0RCLK0 bits.
When Timer 1 is selected as a baud rate source, the SMOD0 bit (SSTA0.4) selects whether or not to divide the Timer 1 overflow rate by two. On reset, the SMOD0 bit is logic 0, thus selecting the lower speed baud
rate by default. The SMOD0 bit affects the baud rate generated by Timer 1 as shown in Equation 22.1.
Equation 22.1. Mode 1 Baud Rate using Timer 1
When SMOD0 = 0:
Mode1_BaudRate = 1 32
⋅
Timer1_OverflowRate
When SMOD0 = 1:
Mode1_BaudRate = 1 16
⋅
Timer1_OverflowRate
The Timer 1 overflow rate is determined by the Timer 1 clock source (T1CLK) and reload value (TH1). The
frequency of T1CLK is selected as described in Section “24.1. Timer 0 and Timer 1” on page 287
. The
Timer 1 overflow rate is calculated as shown in Equation 22.2.
Equation 22.2. Timer 1 Overflow Rate
Timer1_OverflowRate = T1CLK
⁄ (
256 – TH1
)
When Timers 2, 3, or 4 are selected as a baud rate source, the baud rate is generated as shown in
Equation 22.3. Mode 1 Baud Rate using Timer 2, 3, or 4
Mode1_BaudRate = 1 16
⋅
Timer234_OverflowRate
The overflow rate for Timer 2, 3, or 4 is determined by the clock source for the timer (TnCLK) and the 16-
bit reload value stored in the RCAPn register (n = 2, 3, or 4), as shown in Equation 22.4.
Equation 22.4. Timer 2, 3, or 4 Overflow Rate
Timer234_OverflowRate = TnCLK
⁄ (
65536 – RCAPn
)
268 Rev. 1.2
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22.1.3. Mode 2: 9-Bit UART, Fixed Baud Rate
Mode 2 provides asynchronous, full-duplex communication using a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programmable ninth data bit, and a stop bit. Mode 2 supports multiprocessor communications and hardware address recognition (see
). On transmit, the ninth data bit is
determined by the value in TB80 (SCON0.3). It can be assigned the value of the parity flag P in the PSW or used in multiprocessor communications. On receive, the ninth data bit goes into RB80 (SCON0.2) and the stop bit is ignored.
Data transmission begins when an instruction writes a data byte to the SBUF0 register. The TI0 Transmit
Interrupt Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data reception can begin any time after the REN0 Receive Enable bit (SCON0.4) is set to logic 1. After the stop bit is received, the data byte will be loaded into the SBUF0 receive register if RI0 is logic 0 and one of the following requirements are met:
1.
SM20 is logic 0
2.
SM20 is logic 1, the received 9th bit is logic 1, and the received address matches the UART0
address as described in Section 22.2
If the above conditions are satisfied, the eight bits of data are stored in SBUF0, the ninth bit is stored in
RB80 and the RI0 flag is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the
RI0 flag will not be set. An interrupt will occur if enabled when either TI0 or RI0 are set.
The baud rate in Mode 2 is either SYSCLK / 32 or SYSCLK / 64, according to the value of the SMOD0 bit in register SSTA0.
Equation 22.5. Mode 2 Baud Rate
BaudRate
= 2
SMOD0
×
----------------------
64
MARK
SPACE
BIT TIMES
START
BIT
BIT SAMPLING
D0
Figure 22.5. UART0 Modes 2 and 3 Timing Diagram
D1 D2 D3 D4 D5 D6 D7 D8
STOP
BIT
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Figure 22.6. UART0 Modes 1, 2, and 3 Interconnect Diagram
RS-232
RS-232
LEVEL
XLTR
TX
RX
C8051Fxxx
OR
MCU
TX
RX
TX
RX
C8051Fxxx
22.1.4. Mode 3: 9-Bit UART, Variable Baud Rate
Mode 3 uses the Mode 2 transmission protocol with the Mode 1 baud rate generation. Mode 3 operation transmits 11 bits: a start bit, 8 data bits (LSB first), a programmable ninth data bit, and a stop bit. The baud
.
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22.2. Multiprocessor Communications
Modes 2 and 3 support multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit and the built-in UART0 address recognition hardware. When a master processor wants to transmit to one or more slaves, it first sends an address byte to select the target(s). An address byte differs from a data byte in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0. UART0 will recognize as “valid” (i.e., capable of causing an interrupt) two types of addresses: (1) a masked address and (2) a broadcast address at any given time. Both are described below.
22.2.1. Configuration of a Masked Address
The UART0 address is configured via two SFRs: SADDR0 (Serial Address) and SADEN0 (Serial Address
Enable). SADEN0 sets the bit mask for the address held in SADDR0: bits set to logic 1 in SADEN0 correspond to bits in SADDR0 that are checked against the received address byte; bits set to logic 0 in SADEN0 correspond to “don’t care” bits in SADDR0.
Example 1, SLAVE #1
SADDR0 = 00110101
SADEN0 = 00001111
UART0 Address = xxxx0101
Example 2, SLAVE #2
SADDR0 = 00110101
SADEN0 = 11110011
UART0 Address = 0011xx01
Example 3, SLAVE #3
SADDR0 = 00110101
SADEN0 = 11000000
UART0 Address = 00xxxxxx
Setting the SM20 bit (SCON0.5) configures UART0 such that when a stop bit is received, UART0 will generate an interrupt only if the ninth bit is logic 1 (RB80 = ‘1’) and the received data byte matches the UART0 slave address. Following the received address interrupt, the slave will clear its SM20 bit to enable interrupts on the reception of the following data byte(s). Once the entire message is received, the addressed slave resets its SM20 bit to ignore all transmissions until it receives the next address byte. While SM20 is logic 1, UART0 ignores all bytes that do not match the UART0 address and include a ninth bit that is logic
1.
22.2.2. Broadcast Addressing
Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. The broadcast address is the logical OR of registers SADDR0 and SADEN0, and ‘0’s of the result are treated as “don’t cares”. Typically a broadcast address of 0xFF (hexadecimal) is acknowledged by all slaves, assuming
“don’t care” bits as ‘1’s. The master processor can be configured to receive all transmissions or a protocol can be implemented such that the master/slave role is temporarily reversed to enable half-duplex transmission between the original master and slave(s)..
Example 4, SLAVE #1
SADDR0
SADEN0
Broadcast
Address
= 00110101
= 00001111
= 00111111
Example 5, SLAVE #2
SADDR0
SADEN0
Broadcast
Address
= 00110101
= 11110011
= 11110111
Example 6, SLAVE #3
SADDR0
SADEN0
Broadcast
Address
Where all ZEROES in the Broadcast address are don’t cares.
= 00110101
= 11000000
= 11110101
Note in the above examples 4, 5, and 6, each slave would recognize as “valid” an address of 0xFF as a broadcast address. Also note that examples 4, 5, and 6 uses the same SADDR0 and SADEN0 register values as shown in the examples 1, 2, and 3 respectively (slaves #1, 2, and 3). Thus, a master could address each slave device individually using a masked address, and also broadcast to all three slave devices. For example, if a Master were to send an address “11110101”, only slave #1 would recognize the
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address as valid. If a master were to then send an address of “11111111”, all three slave devices would recognize the address as a valid broadcast address.
Figure 22.7. UART Multi-Processor Mode Interconnect Diagram
Master
Device
RX TX
Slave
Device
RX TX
Slave
Device
RX TX
Slave
Device
RX TX
+5V
22.3. Frame and Transmission Error Detection
All Modes:
The Transmit Collision bit (TXCOL0 bit in register SCON0) reads ‘1’ if user software writes data to the
SBUF0 register while a transmit is in progress. Note that the TXCOL0 bit is also used as the SM20 bit when written by user software. This bit does not generate an interrupt.
Modes 1, 2, and 3:
The Receive Overrun bit (RXOV0 in register SCON0) reads ‘1’ if a new data byte is latched into the receive buffer before software has read the previous byte. Note that the RXOV0 bit is also used as the SM10 bit when written by user software. The Frame Error bit (FE0 in register SSTA0) reads ‘1’ if an invalid (low)
STOP bit is detected. Note that the FE0 bit is also used as the SM00 bit when written by user software.
The RXOV0 and FE0 bits do not generate interrupts.
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(MHz)
Table 22.2. Oscillator Frequencies for Standard Baud Rates
Oscillator frequency Divide Factor
24.0
22.1184
18.432
11.0592
3.6864
1.8432
24.0
22.1184
18.432
11.0592
3.6864
1.8432
208
192
160
96
32
16
832
768
640
348
128
64
24.0
22.1184
18.432
11.0592
2496
2304
1920
1152
0x64
0x70
0x88
0xB8
3.6864
1.8432
384
192
0xE8
0xF4
* Assumes SMOD0=1 and T1M=1.
** Numbers in parenthesis show the actual baud rate.
0xF3
0xF4
0xF6
0xFA
0xFE
0xFF
0xCC
0xD0
0xD8
0xE8
0xF8
0xFC
Timer 1 Reload
Value*
Timer 2, 3, or
4 Reload
Value
0xFFF3
0xFFF4
0xFFF6
0xFFFA
0xFFFE
0xFFFF
0xFFCC
0xFFD0
0xFFD8
0xFFE8
0xFFF8
0xFFFC
0xFF64
0xFF70
0xFF88
0xFFB8
0xFFE8
0xFFF4
Resulting Baud Rate (Hz)**
115200 (115384)
115200
115200
115200
115200
115200
28800 (28846)
28800
28800
28800
28800
28800
9600 (9615)
9600
9600
9600
9600
9600
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Figure 22.8. SCON0: UART0 Control Register
R/W
SM00
Bit7
R/W
SM10
Bit6
R/W
SM20
Bit5
R/W
REN0
Bit4
R/W
TB80
Bit3
R/W
RB80
Bit2
R/W
TI0
Bit1
R/W
RI0
Reset Value
00000000
Bit0
Bit
Addressable
SFR Address: 0x98
SFR Page: 0
Bits7-6: SM00-SM10: Serial Port Operation Mode:
Write:
When written, these bits select the Serial Port Operation Mode as follows:
SM00
0
0
1
1
SM10
0
1
0
1
Mode
Mode 0: Synchronous Mode
Mode 1: 8-Bit UART, Variable Baud Rate
Mode 2: 9-Bit UART, Fixed Baud Rate
Mode 3: 9-Bit UART, Variable Baud Rate
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
Reading these bits returns the current UART0 mode as defined above.
SM20: Multiprocessor Communication Enable.
The function of this bit is dependent on the Serial Port Operation Mode.
Mode 0: No effect.
Mode 1: Checks for valid stop bit.
0: Logic level of stop bit is ignored.
1: RI0 will only be activated if stop bit is logic level 1.
Mode 2 and 3: Multiprocessor Communications Enable.
0: Logic level of ninth bit is ignored.
1: RI0 is set and an interrupt is generated only when the ninth bit is logic 1 and the received address matches the UART0 address or the broadcast address.
REN0: Receive Enable.
This bit enables/disables the UART0 receiver.
0: UART0 reception disabled.
1: UART0 reception enabled.
TB80: Ninth Transmission Bit.
The logic level of this bit will be assigned to the ninth transmission bit in Modes 2 and 3. It is not used in Modes 0 and 1. Set or cleared by software as required.
RB80: Ninth Receive Bit.
The bit is assigned the logic level of the ninth bit received in Modes 2 and 3. In Mode 1, if
SM20 is logic 0, RB80 is assigned the logic level of the received stop bit. RB8 is not used in
Mode 0.
TI0: Transmit Interrupt Flag.
Set by hardware when a byte of data has been transmitted by UART0 (after the 8th bit in
Mode 0, or at the beginning of the stop bit in other modes). When the UART0 interrupt is enabled, setting this bit causes the CPU to vector to the UART0 interrupt service routine.
This bit must be cleared manually by software.
RI0: Receive Interrupt Flag.
Set by hardware when a byte of data has been received by UART0 (as selected by the
SM20 bit). When the UART0 interrupt is enabled, setting this bit causes the CPU to vector to the UART0 interrupt service routine. This bit must be cleared manually by software.
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Figure 22.9. SSTA0: UART0 Status and Clock Selection Register
R/W
FE0
Bit7
R/W R/W R/W R/W R/W R/W R/W Reset Value
RXOV0 TXCOL0 SMOD0 S0TCLK1 S0TCLK0 S0RCLK1 S0RCLK0 00000000
Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address: 0x91
SFR Page: 0
Bit7:
Bit6:
Bit5:
Bit4:
FE0: Frame Error Flag.
†
This flag indicates if an invalid (low) STOP bit is detected.
0: Frame Error has not been detected.
1: Frame Error has been detected.
RXOV0: Receive Overrun Flag.
†
This flag indicates new data has been latched into the receive buffer before software has read the previous byte.
0: Receive overrun has not been detected.
1: Receive Overrun has been detected.
TXCOL0: Transmit Collision Flag.
†
This flag indicates user software has written to the SBUF0 register while a transmission is in progress.
0: Transmission Collision has not been detected.
1: Transmission Collision has been detected.
SMOD0: UART0 Baud Rate Doubler Enable.
This bit enables/disables the divide-by-two function of the UART0 baud rate logic for configurations described in the UART0 section.
0: UART0 baud rate divide-by-two enabled.
1: UART0 baud rate divide-by-two disabled.
Bits3-2: UART0 Transmit Baud Rate Clock Selection Bits.
S0TCLK1 S0TCLK0
0
0
0
1
1
1
0
1
Serial Transmit Baud Rate Clock Source
Timer 1 generates UART0 TX Baud Rate
Timer 2 Overflow generates UART0 TX baud rate
Timer 3 Overflow generates UART0 TX baud rate
Timer 4 Overflow generates UART0 TX baud rate
Bits1-0: UART0 Receive Baud Rate Clock Selection Bits.
S0RCLK1 S0RCLK0
0 0
0
1
1
1
0
1
Serial Receive Baud Rate Clock Source
Timer 1 generates UART0 RX Baud Rate
Timer 2 Overflow generates UART0 RX baud rate
Timer 3 Overflow generates UART0 RX baud rate
Timer 4 Overflow generates UART0 RX baud rate
†
Note: FE0, RXOV0, and TXCOL0 are flags only, and no interrupt is generated by these conditions.
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Figure 22.10. SBUF0: UART0 Data Buffer Register
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W Reset Value
00000000
Bit0
SFR Address: 0x99
SFR Page: 0
Bits7-0: SBUF0.[7:0]: UART0 Buffer Bits 7-0 (MSB-LSB).
This is actually two registers; a transmit and a receive buffer register. When data is moved to
SBUF0, it goes to the transmit buffer and is held for serial transmission. Moving a byte to
SBUF0 is what initiates the transmission. When data is moved from SBUF0, it comes from the receive buffer.
Figure 22.11. SADDR0: UART0 Slave Address Register
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W Reset Value
00000000
Bit0
SFR Address: 0xA9
SFR Page: 0
Bits7-0: SADDR0.[7:0]: UART0 Slave Address.
The contents of this register are used to define the UART0 slave address. Register SADEN0 is a bit mask to determine which bits of SADDR0 are checked against a received address: corresponding bits set to logic 1 in SADEN0 are checked; corresponding bits set to logic 0 are “don’t cares”.
Figure 22.12. SADEN0: UART0 Slave Address Enable Register
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W Reset Value
00000000
Bit0
SFR Address: 0xB9
SFR Page: 0
Bits7-0: SADEN0.[7:0]: UART0 Slave Address Enable.
Bits in this register enable corresponding bits in register SADDR0 to determine the UART0 slave address.
0: Corresponding bit in SADDR0 is a “don’t care”.
1: Corresponding bit in SADDR0 is checked against a received address.
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23.
UART1
UART1 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART.
Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in
Section “23.1. Enhanced Baud Rate Generation” on page 278
). Received data buffering allows UART1 to start reception of a second incoming data byte before software has finished reading the previous data byte.
UART1 has two associated SFRs: Serial Control Register 1 (SCON1) and Serial Data Buffer 1 (SBUF1).
The single SBUF1 location provides access to both transmit and receive registers. Reading SBUF1 accesses the buffered Receive register; writing SBUF1 accesses the Transmit register.
With UART1 interrupts enabled, an interrupt is generated each time a transmit is completed (TI1 is set in
SCON1), or a data byte has been received (RI1 is set in SCON1). The UART1 interrupt flags are not cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually by software, allowing software to determine the cause of the UART1 interrupt (transmit complete or receive complete).
Figure 23.1. UART1 Block Diagram
SFR Bus
Write to
SBUF1
TB81
D
SET
Q
CLR
SBUF1
(TX Shift)
Zero Detector
Stop Bit
Start
Tx Clock
Shift
Tx Control
Data
Tx IRQ
Send
TX1
Crossbar
SCON1
UART1 Baud
Rate Generator
TI1
RI1
Serial
Port
Interrupt
Port I/O
Rx Clock
Start
Shift
Rx Control
0x1FF RB81
Rx IRQ
Load
SBUF1
Read
SBUF1
Input Shift Register
(9 bits)
Load SBUF1
SBUF1
(RX Latch)
SFR Bus
RX1
Crossbar
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23.1. Enhanced Baud Rate Generation
The UART1 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by
accessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates.
The RX Timer runs when Timer 1 is enabled, and uses the same reload value (TH1). However, an
RX Timer reload is forced when a START condition is detected on the RX pin. This allows a receive to begin any time a START is detected, independent of the TX Timer state.
Figure 23.2. UART1 Baud Rate Logic
Timer 1 UART1
Overflow
TL1
2
TX Clock
TH1
Start
Detected
RX Timer
Overflow
2
RX Clock
at two times the desired baud rate. Note that Timer 1 may be clocked by one of five sources: SYSCLK,
SYSCLK / 4, SYSCLK / 12, SYSCLK / 48, or the external oscillator clock / 8. For any given Timer 1 clock source, the UART1 baud rate is determined by Equation 23.1.
Equation 23.1. UART1 Baud Rate
UartBaudRate
=
(
T1
256 –
T1H
)
×
2
Where T1
CLK
is the frequency of the clock supplied to Timer 1, and T1H is the high byte of Timer 1 (reload value). Timer 1 clock frequency is selected as described in
Section “24.1. Timer 0 and Timer 1” on page 287
. A quick reference for typical baud rates and system clock frequencies is given in Table 23.1
oscillator is driving Timer 1 (see Section “24.1. Timer 0 and Timer 1” on page 287
for more details).
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23.2. Operational Modes
UART1 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is selected by the S1MODE bit (SCON1.7). Typical UART connection options are shown below.
Figure 23.3. UART Interconnect Diagram
RS-232
RS-232
LEVEL
XLTR
TX
RX
C8051Fxxx
OR
MCU
TX
RX
TX
RX
C8051Fxxx
23.2.1. 8-Bit UART
8-Bit UART mode uses a total of 10 bits per data byte: one start bit, eight data bits (LSB first), and one stop bit. Data are transmitted LSB first from the TX1 pin and received at the RX1 pin. On receive, the eight data bits are stored in SBUF1 and the stop bit goes into RB81 (SCON1.2).
Data transmission begins when software writes a data byte to the SBUF1 register. The TI1 Transmit Interrupt Flag (SCON1.1) is set at the end of the transmission (the beginning of the stop-bit time). Data reception can begin any time after the REN1 Receive Enable bit (SCON1.4) is set to logic 1. After the stop bit is received, the data byte will be loaded into the SBUF1 receive register if the following conditions are met:
RI1 must be logic 0, and if MCE1 is logic 1, the stop bit must be logic 1. In the event of a receive data overrun, the first received 8 bits are latched into the SBUF1 receive register and the following overrun data bits are lost.
If these conditions are met, the eight bits of data is stored in SBUF1, the stop bit is stored in RB81 and the
RI1 flag is set. If these conditions are not met, SBUF1 and RB81 will not be loaded and the RI1 flag will not be set. An interrupt will occur if enabled when either TI1 or RI1 is set.
Figure 23.4. 8-Bit UART Timing Diagram
MARK
SPACE
BIT TIMES
START
BIT
BIT SAMPLING
D0 D1 D2 D3 D4 D5 D6 D7
STOP
BIT
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23.2.2. 9-Bit UART
9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programmable ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB81
(SCON1.3), which is assigned by user software. It can be assigned the value of the parity flag (bit P in register PSW) for error detection, or used in multiprocessor communications. On receive, the ninth data bit goes into RB81 (SCON1.2) and the stop bit is ignored.
Data transmission begins when an instruction writes a data byte to the SBUF1 register. The TI1 Transmit
Interrupt Flag (SCON1.1) is set at the end of the transmission (the beginning of the stop-bit time). Data reception can begin any time after the REN1 Receive Enable bit (SCON1.4) is set to ‘1’. After the stop bit is received, the data byte will be loaded into the SBUF1 receive register if the following conditions are met:
(1) RI1 must be logic 0, and (2) if MCE1 is logic 1, the 9th bit must be logic 1 (when MCE1 is logic 0, the state of the ninth data bit is unimportant). If these conditions are met, the eight bits of data are stored in
SBUF1, the ninth bit is stored in RB81, and the RI1 flag is set to ‘1’. If the above conditions are not met,
SBUF1 and RB81 will not be loaded and the RI1 flag will not be set to ‘1’. A UART1 interrupt will occur if enabled when either TI1 or RI1 is set to ‘1’.
Figure 23.5. 9-Bit UART Timing Diagram
MARK
SPACE
BIT TIMES
START
BIT
BIT SAMPLING
D0 D1 D2 D3 D4 D5 D6 D7 D8
STOP
BIT
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23.3. Multiprocessor Communications
9-Bit UART mode supports multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or more slaves, it first sends an address byte to select the target(s). An address byte differs from a data byte in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0.
Setting the MCE1 bit (SCON.5) of a slave processor configures its UART such that when a stop bit is received, the UART will generate an interrupt only if the ninth bit is logic one (RB81 = 1) signifying an address byte has been received. In the UART interrupt handler, software should compare the received address with the slave's own assigned 8-bit address. If the addresses match, the slave should clear its
MCE1 bit to enable interrupts on the reception of the following data byte(s). Slaves that weren't addressed leave their MCE1 bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the data. Once the entire message is received, the addressed slave should reset its
MCE1 bit to ignore all transmissions until it receives the next address byte.
Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. The master processor can be configured to receive all transmissions or a protocol can be implemented such that the master/slave role is temporarily reversed to enable half-duplex transmission between the original master and slave(s).
Figure 23.6. UART Multi-Processor Mode Interconnect Diagram
Master
Device
RX TX
Slave
Device
RX TX
Slave
Device
RX TX
Slave
Device
RX TX
+5V
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Figure 23.7. SCON1: Serial Port 1 Control Register
R/W
S1MODE
Bit7
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
R/W
-
Bit6
R/W
MCE1
Bit5
R/W
REN1
Bit4
R/W
TB81
Bit3
R/W
RB81
Bit2
R/W
TI1
Bit1
R/W
RI1
Reset Value
01000000
Bit0
Bit
Addressable
SFR Address: 0x98
SFR Page: 1
S1MODE: Serial Port 1 Operation Mode.
This bit selects the UART1 Operation Mode.
0: 8-bit UART with Variable Baud Rate.
1: 9-bit UART with Variable Baud Rate.
UNUSED. Read = 1b. Write = don’t care.
MCE1: Multiprocessor Communication Enable.
The function of this bit is dependent on the Serial Port 0 Operation Mode.
S1MODE = 0: Checks for valid stop bit.
0: Logic level of stop bit is ignored.
1: RI1 will only be activated if stop bit is logic level 1.
S1MODE = 1: Multiprocessor Communications Enable.
0: Logic level of ninth bit is ignored.
1: RI1 is set and an interrupt is generated only when the ninth bit is logic 1.
REN1: Receive Enable.
This bit enables/disables the UART receiver.
0: UART1 reception disabled.
1: UART1 reception enabled.
TB81: Ninth Transmission Bit.
The logic level of this bit will be assigned to the ninth transmission bit in 9-bit UART Mode. It is not used in 8-bit UART Mode. Set or cleared by software as required.
RB81: Ninth Receive Bit.
RB81 is assigned the value of the STOP bit in Mode 0; it is assigned the value of the 9th data bit in Mode 1.
TI1: Transmit Interrupt Flag.
Set by hardware when a byte of data has been transmitted by UART1 (after the 8th bit in 8bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When the UART1 interrupt is enabled, setting this bit causes the CPU to vector to the UART1 interrupt service routine. This bit must be cleared manually by software.
RI1: Receive Interrupt Flag.
Set to ‘1’ by hardware when a byte of data has been received by UART1 (set at the STOP bit sampling time). When the UART1 interrupt is enabled, setting this bit to ‘1’ causes the CPU to vector to the UART1 interrupt service routine. This bit must be cleared manually by software.
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Figure 23.8. SBUF1: Serial (UART1) Port Data Buffer Register
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W Reset Value
00000000
Bit0
SFR Address: 0x99
SFR Page: 1
Bits7-0: SBUF1[7:0]: Serial Data Buffer Bits 7-0 (MSB-LSB).
This SFR accesses two registers; a transmit shift register and a receive latch register. When data is written to SBUF1, it goes to the transmit shift register and is held for serial transmission. Writing a byte to SBUF1 is what initiates the transmission. A read of SBUF1 returns the contents of the receive latch.
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Table 23.1. Timer Settings for Standard Baud Rates Using the Internal Oscillator
Frequency: 24.5 MHz
Target
Baud Rate
(bps)
Baud Rate
% Error
Oscillator Divide
Factor
Timer Clock
Source
SCA1-SCA0
(pre-scale select)
†
T1M
†
230400
115200
57600
28800
14400
9600
2400
1200
-0.32%
-0.32%
0.15%
-0.32%
0.15%
-0.32%
-0.32%
0.15%
X = Don’t care
106
212
426
SYSCLK
SYSCLK
SYSCLK
848
1704
SYSCLK / 4
SYSCLK / 12
2544 SYSCLK / 12
10176 SYSCLK / 48
20448 SYSCLK / 48
XX
XX
XX
01
00
00
10
10
0
0
0
0
0
1
1
1
Timer 1
Reload
Value
(hex)
0xCB
0x96
0x2B
0x96
0xB9
0x96
0x96
0x2B
†
SCA1-SCA0 and T1M bit definitions can be found in
Table 23.2. Timer Settings for Standard Baud Rates Using an External Oscillator
Frequency: 25.0 MHz
Target
Baud Rate
(bps)
Baud Rate
% Error
Oscillator Divide
Factor
Timer Clock
Source
SCA1-SCA0
(pre-scale select)
†
T1M
†
Timer 1
Reload
Value
(hex)
230400
115200
57600
28800
14400
9600
2400
1200
57600
28800
14400
-0.47%
0.45%
-0.01%
0.45%
-0.01%
0.15%
0.45%
-0.01%
-0.47%
-0.47%
0.45%
108
218
434
872
SYSCLK
SYSCLK
SYSCLK
SYSCLK / 4
1736
2608
SYSCLK / 4
EXTCLK / 8
10464 SYSCLK / 48
20832 SYSCLK / 48
432
864
1744
EXTCLK / 8
EXTCLK / 8
EXTCLK / 8
01
11
10
10
XX
XX
XX
01
11
11
11
0
0
0
0
1
0
1
1
0
0
0
0xCA
0x93
0x27
0x93
0x27
0x5D
0x93
0x27
0xE5
0xCA
0x93
9600 0x5D 0.15% 2608 EXTCLK / 8 11 0
X = Don’t care
†
SCA1-SCA0 and T1M bit definitions can be found in
284 Rev. 1.2
C8051F060/1/2/3/4/5/6/7
Table 23.3. Timer Settings for Standard Baud Rates Using an External Oscillator
Frequency: 22.1184 MHz
Target
Baud Rate
(bps)
Baud Rate
% Error
Oscillator Divide
Factor
Timer Clock
Source
SCA1-SCA0
(pre-scale select)
†
T1M
†
230400
115200
57600
28800
14400
9600
2400
1200
230400
115200
57600
28800
14400
9600
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
X = Don’t care
96
192
384
768
1536
2304
9216
SYSCLK
SYSCLK
SYSCLK
SYSCLK / 12
SYSCLK / 12
SYSCLK / 12
SYSCLK / 48
18432 SYSCLK / 48
96 EXTCLK / 8
192
384
EXTCLK / 8
EXTCLK / 8
768
1536
2304
EXTCLK / 8
EXTCLK / 8
EXTCLK / 8
10
11
11
11
11
11
11
XX
XX
XX
00
00
00
10
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0xA0
0xA0
0x40
0xFA
0xF4
0xE8
0xD0
0xA0
0x70
Timer 1
Reload
Value
(hex)
0xD0
0xA0
0x40
0xE0
0xC0
†
SCA1-SCA0 and T1M bit definitions can be found in
Table 23.4. Timer Settings for Standard Baud Rates Using an External Oscillator
Frequency: 18.432 MHz
Target
Baud Rate
(bps)
Baud Rate
% Error
Oscillator Divide
Factor
Timer Clock
Source
SCA1-SCA0
(pre-scale select)
†
T1M
†
Timer 1
Reload
Value
(hex)
230400
115200
57600
28800
14400
9600
2400
1200
230400
115200
57600
28800
14400
9600
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
X = Don’t care
80
160
320
640
SYSCLK
SYSCLK
SYSCLK
SYSCLK / 4
1280
1920
SYSCLK / 4
SYSCLK / 12
7680 SYSCLK / 48
15360 SYSCLK / 48
80
160
320
640
1280
1920
EXTCLK / 8
EXTCLK / 8
EXTCLK / 8
EXTCLK / 8
EXTCLK / 8
EXTCLK / 8
11
11
11
11
11
11
01
00
10
10
XX
XX
XX
01
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0xD8
0xB0
0x60
0xB0
0x60
0xB0
0xB0
0x60
0xFB
0xF6
0xEC
0xD8
0xB0
0x88
†
SCA1-SCA0 and T1M bit definitions can be found in Section 24.1
Rev. 1.2
285
C8051F060/1/2/3/4/5/6/7
Table 23.5. Timer Settings for Standard Baud Rates Using an External Oscillator
Frequency: 11.0592 MHz
Target
Baud Rate
(bps)
Baud Rate
% Error
Oscillator Divide
Factor
Timer Clock
Source
SCA1-SCA0
(pre-scale select)
†
T1M
†
230400
115200
57600
28800
14400
9600
2400
1200
230400
115200
57600
28800
14400
9600
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
X = Don’t care
9216
48
96
192
384
768
1152
48
96
192
384
768
1152
4608
SYSCLK
SYSCLK
SYSCLK
SYSCLK
SYSCLK / 12
SYSCLK / 12
SYSCLK / 12
SYSCLK / 48
EXTCLK / 8
EXTCLK / 8
EXTCLK / 8
EXTCLK / 8
EXTCLK / 8
EXTCLK / 8
10
11
11
11
11
11
11
XX
XX
XX
XX
00
00
00
0
0
0
0
0
0
0
0
0
1
0
1
1
1
0xD0
0x40
0xA0
0xFD
0xFA
0xF4
0xE8
0xD0
0xB8
Timer 1
Reload
Value
(hex)
0xE8
0xD0
0xA0
0x40
0xE0
†
SCA1-SCA0 and T1M bit definitions can be found in
Table 23.6. Timer Settings for Standard Baud Rates Using an External Oscillator
Frequency: 3.6864 MHz
Target
Baud Rate
(bps)
Baud Rate
% Error
Oscillator Divide
Factor
Timer Clock
Source
SCA1-SCA0
(pre-scale select)
†
T1M
†
Timer 1
Reload
Value
(hex)
230400
115200
57600
28800
14400
9600
2400
1200
230400
115200
57600
28800
14400
9600
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
X = Don’t care
16
32
64
128
256
384
16
32
64
128
256
384
1536
3072
SYSCLK
SYSCLK
SYSCLK
SYSCLK
SYSCLK
SYSCLK
SYSCLK / 12
SYSCLK / 12
EXTCLK / 8
EXTCLK / 8
EXTCLK / 8
EXTCLK / 8
EXTCLK / 8
EXTCLK / 8
11
11
11
11
11
11
XX
XX
00
00
XX
XX
XX
XX
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0xF8
0xF0
0xE0
0xC0
0x80
0x40
0xC0
0x80
0xFF
0xFE
0xFC
0xF8
0xF0
0xE8
†
SCA1-SCA0 and T1M bit definitions can be found in
286 Rev. 1.2
C8051F060/1/2/3/4/5/6/7
24.
Timers
Each MCU includes 5 counter/timers: Timer 0 and Timer 1 are 16-bit counter/timers compatible with those found in the standard 8051. Timer 2, Timer 3, and Timer 4 are 16-bit auto-reload and capture counter/timers for use with the ADC’s, DAC’s, square-wave generation, or for general-purpose use. These timers can be used to measure time intervals, count external events and generate periodic interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary modes of operation. Timers 2, 3, and 4 are identical, and offer not only 16-bit auto-reload and capture, but have the ability to produce a 50% duty-cycle square-wave (toggle output) at an external port pin.
Timer 0 and Timer 1 Modes:
13-bit counter/timer
16-bit counter/timer
8-bit counter/timer with auto-reload
Two 8-bit counter/timers (Timer 0 only)
Timer 2, 3, and 4 Modes:
16-bit counter/timer with auto-reload
16-bit counter/timer with capture
Toggle Output
Timers 0 and 1 may be clocked by one of five sources, determined by the Timer Mode Select bits (T1M-
T0M) and the Clock Scale bits (SCA1-SCA0). The Clock Scale bits define a pre-scaled clock by which
can be configured to use either the pre-scaled clock signal or the system clock directly. Timers 2, 3, and 4 may be clocked by the system clock, the system clock divided by 12, or the external oscillator clock source divided by 8.
Timer 0 and Timer 1 may also be operated as counters. When functioning as a counter, a counter/timer register is incremented on each high-to-low transition at the selected input pin. Events with a frequency of up to one-fourth the system clock's frequency can be counted. The input signal need not be periodic, but it should be held at a given logic level for at least two full system clock cycles to ensure the level is properly sampled.
24.1. Timer 0 and Timer 1
Each timer is implemented as a 16-bit register accessed as two separate 8-bit SFRs: a low byte (TL0 or
TL1) and a high byte (TH0 or TH1). The Counter/Timer Control register (TCON) is used to enable Timer 0 and Timer 1 as well as indicate their status. Timer 0 interrupts can be enabled by setting the ET0 bit in the
). Both counter/timers operate in one of four
primary modes selected by setting the Mode Select bits T1M1-T0M0 in the Counter/Timer Mode register
(TMOD). Both timers can be configured independently.
24.1.1. Mode 0: 13-bit Counter/Timer
Timer 0 and Timer 1 operate as 13-bit counter/timers in Mode 0. The following describes the configuration and operation of Timer 0. However, both timers operate identically, and Timer 1 is configured in the same manner as described for Timer 0.
The TH0 register holds the eight MSBs of the 13-bit counter/timer. TL0 holds the five LSBs in bit positions
TL0.4-TL0.0. The three upper bits of TL0 (TL0.7-TL0.5) are indeterminate and should be masked out or ignored when reading the TL0 register. As the 13-bit timer register increments and overflows from 0x1FFF
(all ones) to 0x0000, the timer overflow flag TF0 (TCON.5) is set and an interrupt will occur if Timer 0 interrupts are enabled.
Rev. 1.2
287
C8051F060/1/2/3/4/5/6/7
The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low
transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to Section
configuring external I/O pins). Clearing C/T selects the clock defined by the T0M bit (CKCON.3). When
T0M is set, Timer 0 is clocked by the system clock. When T0M is cleared, Timer 0 is clocked by the source
selected by the Clock Scale bits in CKCON (see Figure 24.6).
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or the input signal
/INT0 is logic-level 1. Setting GATE0 to ‘1’ allows the timer to be controlled by the external input signal /
INT0 (see Section “13.3.5. Interrupt Register Descriptions” on page 154
), facilitating pulse width measurements.
TR0
0
1
GATE0
X
0
1
1
X = Don't Care
1
1
/INT0
X
X
0
1
Counter/Timer
Disabled
Enabled
Disabled
Enabled
Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial value before the timer is enabled.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The input signal /INT1 is used with Timer 1.
Pre-scaled Clock
SYSCLK
Figure 24.1. T0 Mode 0 Block Diagram
CKCON
T
1
T
0
M M
S
C
S
C
A A
1 0
TMOD
T
E
G
A
1
C
/
T
1
T
1
T
1
M M
1 0
G
A
T
E
0
T
0
C
/
T
0
M
1
T
0
M
0
0
0
1
1
T0
Crossbar
GATE0
TR0
TCLK
TL0
(5 bits)
TH0
(8 bits)
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Interrupt
/INT0
288 Rev. 1.2
C8051F060/1/2/3/4/5/6/7
24.1.2. Mode 1: 16-bit Counter/Timer
Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The counter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0.
24.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload
Mode 2 configures Timer 0 or Timer 1 to operate as 8-bit counter/timers with automatic reload of the start value. TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from 0xFF to 0x00, the timer overflow flag TF0 (TCON.5) is set and the counter in TL0 is reloaded from TH0. If Timer
0 interrupts are enabled, an interrupt will occur when the TF0 flag is set. The reload value in TH0 is not changed. TL0 must be initialized to the desired value before enabling the timer for the first count to be correct. When in Mode 2, Timer 1 operates identically to Timer 0.
Both counter/timers are enabled and configured in Mode 2 in the same manner as Mode 0. Setting the
TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or when the input signal /INT0 is low.
Figure 24.2. T0 Mode 2 Block Diagram
CKCON
T
1
T
0
M M
S
C
A
S
C
A
1 0
TMOD
G
A
T
E
1
C
/
T
1
T
1
T
1
M M
1 0
G
A
T
E
0
T
0
C
/
T
0
T
0
M M
1 0
Pre-scaled Clock
0
0
SYSCLK 1
1
T0
Crossbar
GATE0
TR0
TCLK
TL0
(8 bits)
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Interrupt
TH0
(8 bits)
Reload
/INT0
Rev. 1.2
289
C8051F060/1/2/3/4/5/6/7
24.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)
In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The counter/ timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0, GATE0 and
TF0. TL0 can use either the system clock or an external input signal as its timebase. The TH0 register is restricted to a timer function sourced by the system clock or prescaled clock. TH0 is enabled using the
Timer 1 run control bit TR1. TH0 sets the Timer 1 overflow flag TF1 on overflow and thus controls the
Timer 1 interrupt.
Timer 1 is inactive in Mode 3. When Timer 0 is operating in Mode 3, Timer 1 can be operated in Modes 0,
1 or 2, but cannot be clocked by external signals nor set the TF1 flag and generate an interrupt. However, the Timer 1 overflow can be used to generate baud rates for the SMBus and/or UART, and/or initiate ADC conversions. While Timer 0 is operating in Mode 3, Timer 1 run control is handled through its mode settings. To run Timer 1 while Timer 0 is in Mode 3, set the Timer 1 Mode as 0, 1, or 2. To disable Timer 1, configure it for Mode 3.
Pre-scaled Clock
SYSCLK
Figure 24.3. T0 Mode 3 Block Diagram
CKCON
T T
1
M
0
M
C
A
1
S S
C
A
0
TMOD
G
A
T
E
1
C
/
T
1
T
1
T
1
M
1
M
0
G
A
T
E
0
C
/
T
0
T
0
T
0
M
1
M
0
0
TR1
TH0
(8 bits)
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Interrupt
Interrupt
1
T0
TL0
(8 bits)
TR0
Crossbar
GATE0
/INT0
290 Rev. 1.2
C8051F060/1/2/3/4/5/6/7
Figure 24.4. TCON: Timer Control Register
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
R/W
TF1
Bit7
R/W
TR1
Bit6
R/W
TF0
Bit5
R/W
TR0
Bit4
R/W
IE1
Bit3
R/W
IT1
Bit2
R/W
IE0
Bit1
R/W
IT0
Reset Value
00000000
Bit0
Bit
Addressable
SFR Address:
0x88
SFR Page: 0
TF1: Timer 1 Overflow Flag.
Set by hardware when Timer 1 overflows. This flag can be cleared by software but is automatically cleared when the CPU vectors to the Timer 1 interrupt service routine.
0: No Timer 1 overflow detected.
1: Timer 1 has overflowed.
TR1: Timer 1 Run Control.
0: Timer 1 disabled.
1: Timer 1 enabled.
TF0: Timer 0 Overflow Flag.
Set by hardware when Timer 0 overflows. This flag can be cleared by software but is automatically cleared when the CPU vectors to the Timer 0 interrupt service routine.
0: No Timer 0 overflow detected.
1: Timer 0 has overflowed.
TR0: Timer 0 Run Control.
0: Timer 0 disabled.
1: Timer 0 enabled.
IE1: External Interrupt 1.
This flag is set by hardware when an edge/level of type defined by IT1 is detected. It can be cleared by software but is automatically cleared when the CPU vectors to the External Interrupt 1 service routine if IT1 = 1. This flag is the inverse of the /INT1 signal.
IT1: Interrupt 1 Type Select.
This bit selects whether the configured /INT1 interrupt will be falling-edge sensitive or active-low.
0: /INT1 is level triggered, active-low.
1: /INT1 is edge triggered, falling-edge.
IE0: External Interrupt 0.
This flag is set by hardware when an edge/level of type defined by IT0 is detected. It can be cleared by software but is automatically cleared when the CPU vectors to the External Interrupt 0 service routine if IT0 = 1. This flag is the inverse of the /INT0 signal.
IT0: Interrupt 0 Type Select.
This bit selects whether the configured /INT0 interrupt will be falling-edge sensitive or active-low.
0: /INT0 is level triggered, active logic-low.
1: /INT0 is edge triggered, falling-edge.
Rev. 1.2
291
C8051F060/1/2/3/4/5/6/7
Figure 24.5. TMOD: Timer Mode Register
R/W
GATE1
Bit7
R/W
C/T1
Bit6
R/W
T1M1
Bit5
R/W
T1M0
Bit4
R/W
GATE0
Bit3
R/W
C/T0
Bit2
R/W
T0M1
Bit1
R/W
T0M0
Bit0
Reset Value
00000000
SFR Address:
0x89
SFR Page: 0
Bit7:
Bit6:
GATE1: Timer 1 Gate Control.
0: Timer 1 enabled when TR1 = 1 irrespective of /INT1 logic level.
1: Timer 1 enabled only when TR1 = 1 AND /INT1 = logic 1.
C/T1: Counter/Timer 1 Select.
0: Timer Function: Timer 1 incremented by clock defined by T1M bit (CKCON.4).
1: Counter Function: Timer 1 incremented by high-to-low transitions on external input pin
(T1).
Bits5-4: T1M1-T1M0: Timer 1 Mode Select.
These bits select the Timer 1 operation mode.
T1M1
0
0
1
1
T1M0
0
1
0
1
Mode
Mode 0: 13-bit counter/timer
Mode 1: 16-bit counter/timer
Mode 2: 8-bit counter/timer with autoreload
Mode 3: Timer 1 inactive
Bit3:
Bit2:
GATE0: Timer 0 Gate Control.
0: Timer 0 enabled when TR0 = 1 irrespective of /INT0 logic level.
1: Timer 0 enabled only when TR0 = 1 AND /INT0 = logic 1.
C/T0: Counter/Timer Select.
0: Timer Function: Timer 0 incremented by clock defined by T0M bit (CKCON.3).
1: Counter Function: Timer 0 incremented by high-to-low transitions on external input pin
(T0).
Bits1-0: T0M1-T0M0: Timer 0 Mode Select.
These bits select the Timer 0 operation mode.
T0M1
0
0
1
1
T0M0
0
1
0
1
Mode
Mode 0: 13-bit counter/timer
Mode 1: 16-bit counter/timer
Mode 2: 8-bit counter/timer with autoreload
Mode 3: Two 8-bit counter/timers
292 Rev. 1.2
C8051F060/1/2/3/4/5/6/7
Figure 24.6. CKCON: Clock Control Register
R/W
-
Bit7
R/W
-
Bit6
R/W
-
Bit5
R/W
T1M
Bit4
R/W
T0M
Bit3
R/W
-
Bit2
R/W
SCA1
Bit1
R/W
SCA0
Reset Value
00000000
Bit0
SFR Address:
0x8E
SFR Page: 0
Bits7-5: UNUSED. Read = 000b, Write = don’t care.
Bit4: T1M: Timer 1 Clock Select.
This select the clock source supplied to Timer 1. T1M is ignored when C/T1 is set to logic 1.
0: Timer 1 uses the clock defined by the prescale bits, SCA1-SCA0.
Bit3:
1: Timer 1 uses the system clock.
T0M: Timer 0 Clock Select.
This bit selects the clock source supplied to Timer 0. T0M is ignored when C/T0 is set to logic 1.
0: Counter/Timer 0 uses the clock defined by the prescale bits, SCA1-SCA0.
1: Counter/Timer 0 uses the system clock.
Bit2: UNUSED. Read = 0b, Write = don’t care.
Bits1-0: SCA1-SCA0: Timer 0/1 Prescale Bits
These bits control the division of the clock supplied to Timer 0 and/or Timer 1 if configured to use prescaled clock inputs.
SCA1
0
0
1
1
SCA0
0
1
0
1
Prescaled Clock
System clock divided by 12
System clock divided by 4
System clock divided by 48
External clock divided by 8†
†Note: External clock divided by 8 is synchronized with the system clock, and external clock must be less than or equal to the system clock frequency to operate the timer in this mode.
Rev. 1.2
293
C8051F060/1/2/3/4/5/6/7
R/W
Bit7
R/W
Bit6
R/W
Bit5
Figure 24.7. TL0: Timer 0 Low Byte
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W Reset Value
00000000
Bit0
SFR Address:
0x8A
SFR Page: 0
Bits 7-0: TL0: Timer 0 Low Byte.
The TL0 register is the low byte of the 16-bit Timer 0
R/W
Bit7
R/W
Bit6
R/W
Bit5
Figure 24.8. TL1: Timer 1 Low Byte
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W Reset Value
00000000
Bit0
SFR Address:
0x8B
SFR Page: 0
Bits 7-0: TL1: Timer 1 Low Byte.
The TL1 register is the low byte of the 16-bit Timer 1.
Figure 24.9. TH0: Timer 0 High Byte
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
Bits 7-0: TH0: Timer 0 High Byte.
The TH0 register is the high byte of the 16-bit Timer 0.
Figure 24.10. TH1: Timer 1 High Byte
R/W
Bit1
R/W Reset Value
00000000
Bit0
SFR Address:
0x8C
SFR Page: 0
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W Reset Value
00000000
Bit0
SFR Address:
0x8D
SFR Page: 0
Bits 7-0: TH1: Timer 1 High Byte.
The TH1 register is the high byte of the 16-bit Timer 1.
294 Rev. 1.2
C8051F060/1/2/3/4/5/6/7
24.2. Timer 2, Timer 3, and Timer 4
Timers 2, 3, and 4 are 16-bit counter/timers, each formed by two 8-bit SFRs: TMRnL (low byte) and
TMRnH (high byte) where n = 2, 3, and 4 for timers 2, 3, and 4 respectively. These timers feature autoreload, capture, and toggle output modes with the ability to count up or down. Capture Mode and Autoreload mode are selected using bits in the Timer 2, 3, and 4 Control registers (TMRnCN). Toggle output mode is selected using the Timer 2, 3, and 4 Configuration registers (TMRnCF). These timers may also be used to generate a square-wave at an external pin. Timers 2, 3, and 4 can use either the system clock
(divided by one, two, or twelve), external clock (divided by eight) or transitions on an external input pin as its clock source. Timer 2 and 3 can be used to start an ADC Data Conversion and Timers 2, 3, and 4 can schedule DAC outputs. Timers 1, 2, 3, or 4 may be used to generate baud rates for UART 0. Only Timer 1 can be used to generate baud rates for UART 1.
The Counter/Timer Select bit C/Tn bit (TMRnCN.1) configures the peripheral as a counter or timer. Clearing C/Tn configures the Timer to be in a timer mode (i.e., the selected timer clock source as the input for the timer). When C/Tn is set to 1, the timer is configured as a counter (i.e., high-to-low transitions at the Tn
for digital peripherals, such as the Tn pin.
Timer 2, 3, and 4 can use either SYSCLK, SYSCLK divided by 2, SYSCLK divided by 12, an external clock divided by 8, or high-to-low transitions on the Tn input pin as its clock source when operating in Counter/
Timer with Capture mode. Clearing the C/Tn bit (TnCON.1) selects the system clock/external clock as the input for the timer. The Timer Clock Select bits TnM0 and TnM1 in TMRnCF can be used to select the system clock undivided, system clock divided by two, system clock divided by 12, or an external clock pro-
transition at the Tn input pin increments the counter/timer register (i.e., configured as a counter).
24.2.1. Configuring Timer 2, 3, and 4 to Count Down
Timers 2, 3, and 4 have the ability to count down. When the timer’s respective Decrement Enable Bit
down. When DCENn = 1, the direction of the timer’s count is controlled by the TnEX pin’s logic level. When
TnEX = 1, the counter/timer will count up; when TnEX = 0, the counter/timer will count down. To use this feature, TnEX must be enabled in the digital crossbar and configured as a digital input.
Note: When DCENn = 1, other functions of the TnEX input (i.e., capture and auto-reload) are not available. TnEX will only control the direction of the timer when DCENn = 1.
Rev. 1.2
295
C8051F060/1/2/3/4/5/6/7
24.2.2. Capture Mode
In Capture Mode, Timer 2, 3, and 4 will operate as a 16-bit counter/timer with capture facility. When the
Timer External Enable bit (found in the TMRnCN register) is set to ‘1’, a high-to-low transition on the TnEX input pin causes the 16-bit value in the associated timer (THn, TLn) to be loaded into the capture registers
(RCAPnH, RCAPnL). If a capture is triggered in the counter/timer, the Timer External Flag (TMRnCN.6)
for further information concerning the configuration of interrupt sources.
As the 16-bit timer register increments and overflows TMRnH:TMRnL, the TFn Timer Overflow/Underflow
Flag (TMRnCN.7) is set to ‘1’ and an interrupt will occur if the interrupt is enabled. The timer can be configured to count down by setting the Decrement Enable Bit (TMRnCF.0) to ‘1’. This will cause the timer to decrement with every timer clock/count event and underflow when the timer transitions from 0x0000 to
0xFFFF. Just as in overflows, the Overflow/Underflow Flag (TFn) will be set to ‘1’, and an interrupt will occur if enabled.
Counter/Timer with Capture mode is selected by setting the Capture/Reload Select bit CP/RLn
(TMRnCN.0) and the Timer 2, 3, and 4 Run Control bit TRn (TnCON.2) to logic 1. The Timer 2, 3, and 4 respective External Enable EXENn (TnCON.3) must also be set to logic 1 to enable a captures. If EXENn is cleared, transitions on TnEX will be ignored.
Figure 24.11. T2, 3, and 4 Capture Mode Block Diagram
TMRnCF
T n
T n
T
O
T n
D
C
M
1
M G
0 n
O E
E N
2
12 SYSCLK
External Clock
(XTAL1)
8
Tn
TnEX
Crossbar
EXENn
Crossbar
TRn
0
1
0xFF 0xFF
Toggle Logic
0
1
TCLK
TMRnL TMRnH
OVF
Capture
RCAPnL RCAPnH
CP/RLn
C/Tn
TRn
EXENn
EXFn
TFn
Interrupt
Tn
(Port Pin)
296 Rev. 1.2
C8051F060/1/2/3/4/5/6/7
24.2.3. Auto-Reload Mode
In Auto-Reload Mode, the counter/timer can be configured to count up or down and cause an interrupt/flag to occur upon an overflow/underflow event. When counting up, the counter/timer will set its overflow/underflow flag (TFn) and cause an interrupt (if enabled) upon overflow/underflow, and the values in the Reload/
Capture Registers (RCAPnH and RCAPnL) are loaded into the timer and the timer is restarted. When the
Timer External Enable Bit (EXENn) bit is set to ‘1’ and the Decrement Enable Bit (DCENn) is ‘0’, a falling edge (‘1’-to-‘0’ transition) on the TnEX pin (configured as an input in the digital crossbar) will cause a timer reload (in addition to timer overflows causing auto-reloads). When DCENn is set to ‘1’, the state of the
TnEX pin controls whether the counter/timer counts up (increments) or down (decrements), and will not
cause an auto-reload or interrupt event. See Section 24.2.1
for information concerning configuration of a timer to count down.
When counting down, the counter/timer will set its overflow/underflow flag (TFn) and cause an interrupt (if enabled) when the value in the timer (TMRnH and TMRnL registers) matches the 16-bit value in the
Reload/Capture Registers (RCAPnH and RCAPnL). This is considered an underflow event, and will cause the timer to load the value 0xFFFF. The timer is automatically restarted when an underflow occurs.
.
Counter/Timer with Auto-Reload mode is selected by clearing the CP/RLn bit. Setting TRn to logic 1 enables and starts the timer.
In Auto-Reload Mode, the External Flag (EXFn) toggles upon every overflow or underflow and does not cause an interrupt. The EXFn flag can be thought of as the most significant bit (MSB) of a 17-bit counter.
Figure 24.12. T2, 3, and 4 Auto-reload Mode Block Diagram
TMRnCF
M
1
T n
M
0
T n
T
O
G n
T n
O
E
E
N
D
C
Toggle Logic
SYSCLK
2
12
External Clock
(XTAL1)
8
Tn
TnEX
Crossbar
EXENn
TRn
Crossbar
SMBus
(Timer 4 Only)
0
1
0xFF 0xFF
TCLK
TMRnL TMRnH
OVF
Reload
RCAPnL RCAPnH
CP/RLn
C/Tn
TRn
EXENn
EXFn
TFn
0
1
Interrupt
Tn
(Port Pin)
Rev. 1.2
297
C8051F060/1/2/3/4/5/6/7
24.2.4. Toggle Output Mode
Timer 2, 3, and 4 have the capability to toggle the state of their respective output port pins (T2, T3, or T4) to produce a 50% duty cycle waveform output. The port pin state will change upon the overflow or underflow of the respective timer (depending on whether the timer is counting up or down). The toggle frequency is determined by the clock source of the timer and the values loaded into RCAPnH and RCAPnL. When counting DOWN, the auto-reload value for the timer is 0xFFFF, and underflow will occur when the value in the timer matches the value stored in RCAPnH:RCAPnL. When counting UP, the auto-reload value for the timer is RCAPnH:RCAPnL, and overflow will occur when the value in the timer transitions from 0xFFFF to the reload value.
To output a square wave, the timer is placed in reload mode (the Capture/Reload Select Bit in TMRnCN and the Timer/Counter Select Bit in TMRnCN are cleared to ‘0’). The timer output is enabled by setting the
Timer Output Enable Bit in TMRnCF to ‘1’. The timer should be configured via the timer clock source and reload/underflow values such that the timer overflow/underflows at 1/2 the desired output frequency. The port pin assigned by the crossbar as the timer’s output pin should be configured as a digital output (see
the pin. A Read/Write of the Timer’s Toggle Output State Bit (TMRnCF.2) is used to read the state of the toggle output, or to force a value of the output. This is useful when it is desired to start the toggle of a pin in a known state, or to force the pin into a desired state when the toggle mode is halted.
Equation 24.1. Toggle Mode Square Wave Frequency
F
sq
=
2
⋅ (
F
65536 –
RCAPn
)
298 Rev. 1.2
C8051F060/1/2/3/4/5/6/7
Figure 24.13. TMRnCN: Timer 2, 3, and 4 Control Registers
R/W
TFn
Bit7
R/W
EXFn
Bit6
R/W
-
Bit5
R/W
-
Bit4
R/W
EXENn
Bit3
SFR Address: TMR2CN: 0xC8; TMR3CN: 0xC8; TMR4CN: 0xC8
SFR Page: TMR2CN: page 0; TMR3CN: page 1; TMR4CN: page 2
R/W
TRn
Bit2
R/W
C/Tn
Bit1
R/W Reset Value
CP/RLn 00000000
Bit0
Bit
Addressable
Bit7:
Bit6:
TFn: Timer 2, 3, and 4 Overflow/Underflow Flag.
Set by hardware when either the Timer overflows from 0xFFFF to 0x0000, underflows from the value placed in RCAPnH:RCAPnL to 0XFFFF (in Auto-reload Mode), or underflows from
0x0000 to 0xFFFF (in Capture Mode). When the Timer interrupt is enabled, setting this bit causes the CPU to vector to the Timer interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software.
EXFn: Timer 2, 3, and 4 External Flag.
Set by hardware when either a capture or reload is caused by a high-to-low transition on the
TnEX input pin and EXENn is logic 1. When the Timer interrupt is enabled, setting this bit causes the CPU to vector to the Timer Interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software.
Bit5-4: Reserved.
Bit3: EXENn: Timer 2, 3, and 4 External Enable.
Enables high-to-low transitions on TnEX to trigger captures, reloads, and control the direction of the timer/counter (up or down count). If DCENn = 1, TnEX will determine if the timer counts up or down when in Auto-reload Mode. If EXENn = 1, TnEX should be configured as a digital input.
0: Transitions on the TnEX pin are ignored.
Bit2:
Bit1:
Bit0:
1: Transitions on the TnEX pin cause capture, reload, or control the direction of timer count
(up or down) as follows:
Capture Mode: ‘1’-to-’0’ Transition on TnEX pin causes RCAPnH:RCAPnL to capture timer value.
Auto-Reload Mode:
DCENn = 0: ‘1’-to-’0’ transition causes reload of timer and sets the EXFn Flag.
DCENn = 1: TnEX logic level controls direction of timer (up or down).
TRn: Timer 2, 3, and 4 Run Control.
This bit enables/disables the respective Timer.
0: Timer disabled.
1: Timer enabled and running/counting.
C/Tn: Counter/Timer Select.
0: Timer Function: Timer incremented by clock defined by TnM1:TnM0
(TMRnCF.4:TMRnCF.3).
1: Counter Function: Timer incremented by high-to-low transitions on external input pin.
CP/RLn: Capture/Reload Select.
This bit selects whether the Timer functions in capture or auto-reload mode.
0: Timer is in Auto-Reload Mode.
1: Timer is in Capture Mode.
Rev. 1.2
299
C8051F060/1/2/3/4/5/6/7
Figure 24.14. TMRnCF: Timer 2, 3, and 4 Configuration Registers
-
R/W
TnM1
R/W
TnM0
Bit7 Bit6 Bit5 Bit4 Bit3
SFR Address: TMR2CF: 0xC9; TMR3CF: 0xC9; TMR4CF: 0xC9
SFR Page TMR2CF: page 0; TMR3CF: page 1; TMR4CF: page 2
R/W
TOGn
Bit2
R/W
TnOE
Bit1
R/W Reset Value
DCENn 00000000
Bit0
Bit7-5: Reserved.
Bit4-3: TnM1 and TnM0: Timer Clock Mode Select Bits.
Bits used to select the Timer clock source. The sources can be the System Clock
(SYSCLK), SYSCLK divided by 2 or 12, or an external clock signal routed to Tn (port pin) divided by 8. Clock source is selected as follows:
00: SYSCLK/12
01: SYSCLK
10: EXTERNAL CLOCK/8
Bit2:
Bit1:
11: SYSCLK/2
TOGn: Toggle output state bit.
When timer is used to toggle a port pin, this bit can be used to read the state of the output, or can be written to in order to force the state of the output.
TnOE: Timer output enable bit.
This bit enables the timer to output a 50% duty cycle output to the timer’s assigned external port pin.
NOTE: A timer is configured for Square Wave Output as follows:
Bit0:
CP/RLn = 0
C/Tn = 0
TnOE = 1
Load RCAPnH:RCAPnL (See “Toggle Mode Square Wave Frequency” on page 298.)
Configure Port Pin to output squarewave (See
Section “18. Port Input/Output” on page 203
0: Output of toggle mode not available at Timers’s assigned port pin.
1: Output of toggle mode available at Timers’s assigned port pin.
DCENn: Decrement Enable Bit.
This bit enables the timer to count up or down as determined by the state of TnEX.
0: Timer will count up, regardless of the state of TnEX.
1: Timer will count up or down depending on the state of TnEX as follows: if TnEX = 0, the timer counts DOWN if TnEX = 1, the timer counts UP.
300 Rev. 1.2
C8051F060/1/2/3/4/5/6/7
Figure 24.15. RCAPnL: Timer 2, 3, and 4 Capture Register Low Byte
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3
SFR Address: RCAP2L: 0xCA; RCAP3L: 0xCA; RCAP4L: 0xCA
SFR Page: RCAP2L: page 0; RCAP3L: page 1; RCAP4L: page 2
Bit2 Bit1 Bit0
Bits 7-0: RCAP2, 3, and 4L: Timer 2, 3, and 4 Capture Register Low Byte.
The RCAP2, 3, and 4L register captures the low byte of Timer 2, 3, and 4 when Timer 2, 3, and 4 is configured in capture mode. When Timer 2, 3, and 4 is configured in auto-reload mode, it holds the low byte of the reload value.
Figure 24.16. RCAPnH: Timer 2, 3, and 4 Capture Register High Byte
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3
SFR Address: RCAP2H: 0xCB; RCAP3H: 0xCB; RCAP4H: 0xCB
SFR Page: RCAP2H: page 0; RCAP3H: page 1; RCAP4H: page 2
Bit2 Bit1 Bit0
Bits 7-0: RCAP2, 3, and 4H: Timer 2, 3, and 4 Capture Register High Byte.
The RCAP2, 3, and 4H register captures the high byte of Timer 2, 3, and 4 when Timer 2, 3, and 4 is configured in capture mode. When Timer 2, 3, and 4 is configured in auto-reload mode, it holds the high byte of the reload value.
Figure 24.17. TMRnL: Timer 2, 3, and 4 Low Byte
R/W R/W R/W R/W R/W R/W R/W R/W
Bit7 Bit6 Bit5 Bit4
SFR Address: TMR2L: 0xCC; TMR3L: 0xCC; TMR4L: 0xCC
Bit3
SFR Page: TMR2L: page 0; TMR3L: page 1; TMR4L: page 2
Bit2 Bit1 Bit0
Bits 7-0: TL2, 3, and 4: Timer 2, 3, and 4 Low Byte.
The TL2, 3, and 4 register contains the low byte of the 16-bit Timer 2, 3, and 4
Reset Value
00000000
Rev. 1.2
301
C8051F060/1/2/3/4/5/6/7
Figure 24.18. TMRnH: Timer 2, 3, and 4 High Byte
R/W R/W R/W R/W R/W R/W R/W R/W
Bit7 Bit6 Bit5 Bit4
SFR Address: TMR2H: 0xCD; TMR3H: 0xCD; TMR4H: 0xCD
Bit3
SFR Page: TMR2H: page 0; TMR3H: page 1; TMR4H: page 2
Bit2 Bit1 Bit0
Bits 7-0: TH2, 3, and 4: Timer 2, 3, and 4 High Byte.
The TH2, 3, and 4 register contains the high byte of the 16-bit Timer 2, 3, and 4
Reset Value
00000000
302 Rev. 1.2
C8051F060/1/2/3/4/5/6/7
25.
Programmable Counter Array
The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU intervention than the standard 8051 counter/timers. PCA0 consists of a dedicated 16-bit counter/timer and six 16-bit capture/compare modules. Each capture/compare module has its own associated I/O line
(CEXn) which is routed through the Crossbar to Port I/O when enabled (See
Section “18.1. Ports 0 through
base that can select between six inputs as its source: system clock, system clock divided by four, system clock divided by twelve, the external oscillator clock source divided by 8, Timer 0 overflow, or an external clock signal on the ECI line. Each capture/compare module may be configured to operate independently in one of six modes: Edge-Triggered Capture, Software Timer, High-Speed Output, Frequency Output, 8-Bit
PWM, or 16-Bit PWM (each is described in Section 25.2
). The PCA is configured and controlled through
Figure 25.1. PCA Block Diagram
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
External Clock/8
PCA
CLOCK
MUX
16-Bit Counter/Timer
Capture/Compare
Module 0
Capture/Compare
Module 1
Capture/Compare
Module 2
Capture/Compare
Module 3
Capture/Compare
Module 4
Capture/Compare
Module 5
Crossbar
Port I/O
Rev. 1.2
303
C8051F060/1/2/3/4/5/6/7
25.1. PCA Counter/Timer
The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte
(MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” register.
Reading the PCA0L Register first guarantees an accurate reading of the entire 16-bit PCA0 counter. Reading PCA0H or PCA0L does not disturb the counter operation. The CPS2-CPS0 bits in the PCA0MD regis-
ter select the timebase for the counter/timer as shown in Table 25.1.
When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is set to logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in
PCA0MD to logic 1 enables the CF flag to generate an interrupt request. The CF bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by software (Note: PCA0 interrupts must be globally enabled before CF interrupts are recognized. PCA0 interrupts are globally enabled by setting the EA bit (IE.7) and the EPCA0 bit in EIE1 to logic 1). Clearing the
CIDL bit in the PCA0MD register allows the PCA to continue normal operation while the CPU is in Idle mode.
CPS2
0
0
0
0
1
1
CPS1
0
0
1
1
0
0
Table 25.1. PCA Timebase Input Options
CPS0 Timebase
0
1
0
System clock divided by 12
System clock divided by 4
1
Timer 0 overflow
High-to-low transitions on ECI (max rate = system clock divided by 4)
0
1
System clock
External oscillator source divided by 8 (synchronized with system clock)
Figure 25.2. PCA Counter/Timer Block Diagram
IDLE
304
PCA0MD
C
I
D
L
T
E
W
D
W
D
L
C
K
C
P
S
2
C
P
C
P
S
1
S
0
E
C
F
PCA0CN
C
F
C
R
C
C
F
5
C
C
F
4
C
C
F
3
C
C
F
2
C
C
C
C
F
1
F
0
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
External Clock/8
000
001
010
011
100
101
To SFR Bus
0
1
PCA0L read
Snapshot
Register
PCA0H PCA0L
Overflow
CF
To PCA Interrupt System
To PCA Modules
Rev. 1.2
C8051F060/1/2/3/4/5/6/7
25.2. Capture/Compare Modules
Each module can be configured to operate independently in one of six operation modes: Edge-triggered
Capture, Software Timer, High Speed Output, Frequency Output, 8-Bit Pulse Width Modulator, or 16-Bit
Pulse Width Modulator. Each module has Special Function Registers (SFRs) associated with it in the CIP-
51 system controller. These registers are used to exchange data with a module and configure the module's mode of operation.
pare module’s operating modes. Setting the ECCFn bit in a PCA0CPMn register enables the module's
CCFn interrupt. Note: PCA0 interrupts must be globally enabled before individual CCFn interrupts are recognized. PCA0 interrupts are globally enabled by setting the EA bit (IE.7) and the EPCA0 bit (EIE1.3) to
logic 1. See Figure 25.3 for details on the PCA interrupt configuration.
Table 25.2. PCA0CPM Register Settings for PCA Capture/Compare Modules
PWM16 ECOM CAPP CAPN
X
X
X
X
X
X
0
1
X
X
X
1
1
1
1
1
1
0
1
0
0
0
0
0
X = Don’t Care
0
1
1
0
0
0
0
0
MAT
0
0
0
1
1
0
0
0
TOG
0
0
0
0
1
1
0
0
PWM ECCF
0
0
0
0
0
1
1
1
X
X
Operation Mode
Capture triggered by positive edge on
CEXn
Capture triggered by negative edge on
CEXn
X
Capture triggered by transition on
CEXn
X Software Timer
X High Speed Output
X Frequency Output
0 8-Bit Pulse Width Modulator
0 16-Bit Pulse Width Modulator
Figure 25.3. PCA Interrupt Block Diagram
(for n = 0 to 5)
PCA0CPMn
1
6 n
P
W
M
E
C
O
M n
C n
A
P
P
A
P
N n
C M
A
T n
T
O
G n
P
W
M n
E
C
C
F n
PCA Counter/
Timer Overflow
PCA0CN
C
F
C
R
C C C C C C
C
F
5
C
F
4
C
F
3
C
F
2
C
F
1
C
F
0
C
I
D
L
PCA0MD
C
P
S
2
C C E
P
S
1
P
S
0
C
F
0
1
ECCF0
EPCA0
(EIE.3)
PCA Module 0
0
1
ECCF1
PCA Module 1
0
1
ECCF2
PCA Module 2
0
1
ECCF3
PCA Module 3
0
1
ECCF4
PCA Module 4
0
1
ECCF5
PCA Module 5
0
1
0
1
EA
(IE.7)
0
1
Interrupt
Priority
Decoder
Rev. 1.2
305
C8051F060/1/2/3/4/5/6/7
25.2.1. Edge-triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes PCA0 to capture the value of the PCA0 counter/ timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and
PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transition that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge), or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by software.
Figure 25.4. PCA Capture Mode Diagram
PCA Interrupt
PCA0CPMn
P
W
M
1
6 n
E
C
O
C
A
P
M P n n
C M
A
P
N
A
T n
T
O
G n
P
W
M n n n
E
C
C
F
PCA0CN
C
F
C
R
C
C
F
C
C
F
5 4
C
C
F
C
C
F
C
C
F
3 2 1
C
C
F
0
PCA0CPLn PCA0CPHn
0
1
Port I/O Crossbar
CEXn
Capture
0
1
PCA
Timebase
PCA0L PCA0H
Note: The signal at CEXn must be high or low for at least 2 system clock cycles in order to be valid.
306 Rev. 1.2
C8051F060/1/2/3/4/5/6/7
25.2.2. Software Timer (Compare) Mode
In Software Timer mode, the PCA0 counter/timer is compared to the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by software. Setting the ECOMn and MATn bits in the PCA0CPMn register enables Software
Timer mode.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/
Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit to ‘0’; writing to PCA0CPHn sets ECOMn to ‘1’.
Figure 25.5. PCA Software Timer Mode Diagram
Write to
PCA0CPLn
Reset
0
ENB
Write to
PCA0CPHn ENB
1
PCA
Interrupt
PCA0CPMn
P
W
M
1
6 n
E
C
C
A
O P
M n
P n
C
A
P
N n
M
A
T n
T
O
G n
M n
P
W
E
C
C
F n x 0 0 0 0 x
Enable
PCA0CPLn PCA0CPHn
16-bit Comparator
Match
PCA0CN
C C C C C C C C
F R C
F
5
C
F
4
C
F
3
C
F
2
C
F
1
C
F
0
0
1
PCA
Timebase
PCA0L PCA0H
Rev. 1.2
307
C8051F060/1/2/3/4/5/6/7
25.2.3. High Speed Output Mode
In High Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and
PCA0CPLn) Setting the TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the High-
Speed Output mode.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/
Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit to ‘0’; writing to PCA0CPHn sets ECOMn to ‘1’.
Figure 25.6. PCA High Speed Output Mode Diagram
Write to
PCA0CPLn
Reset
0
ENB
Write to
PCA0CPHn
ENB
1
PCA0CPMn
P
1
6
W
M n
E
C
O
M n x
C
A
P
P n
0 0
C
A
P
N n
M
A
T n
T
O
G n
P
W
M n
E
C
C
F n
0 x
PCA
Interrupt
PCA0CPLn PCA0CPHn
PCA0CN
C
F
C
R
C
C
C
C
C
C
C
C
F
5
F
4
F
3
F
2
C
C
C
C
F
1
F
0
Enable
16-bit Comparator
PCA
Timebase
PCA0L PCA0H
Match
Toggle
0
1
TOGn
0
CEXn
1
Crossbar Port I/O
308 Rev. 1.2
C8051F060/1/2/3/4/5/6/7
25.2.4. Frequency Output Mode
Frequency Output Mode produces a programmable-frequency square wave on the module’s associated
CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the output is toggled. The frequency of the square wave is then defined by Equation 25.1.
Equation 25.1. Square Wave Frequency Output
F
sqr
=
F
-----------------------------------------
2
×
PCA0CPHn
Note: A value of 0x00 in the PCA0CPHn register is equal to 256 for this equation.
Where F
PCA
is the frequency of the clock selected by the CPS2-0 bits in the PCA mode register, PCA0MD.
The lower byte of the capture/compare module is compared to the PCA0 counter low byte; on a match,
CEXn is toggled and the offset held in the high byte is added to the matched value in PCA0CPLn. Frequency Output Mode is enabled by setting the ECOMn, TOGn, and PWMn bits in the PCA0CPMn register.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/
Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit to ‘0’; writing to PCA0CPHn sets ECOMn to ‘1’.
Figure 25.7. PCA Frequency Output Mode
PCA0CPMn
P
W
M
1
6 n
E
C
O
M n
C
A
P
P n
C
A
P
N n
M
A
T n
T
O
G n
P
W
M n
E
C
C
F n
0 0 0 0 1 0
PCA0CPLn
Enable
8-bit
Comparator
8-bit Adder
Adder
Enable
Toggle match
PCA0CPHn
TOGn
0
CEXn
1
Crossbar Port I/O
PCA Timebase
PCA0L
Rev. 1.2
309
C8051F060/1/2/3/4/5/6/7
25.2.5. 8-Bit Pulse Width Modulator Mode
Each module can be used independently to generate pulse width modulated (PWM) outputs on its associated CEXn pin. The frequency of the output is dependent on the timebase for the PCA0 counter/timer. The duty cycle of the PWM output signal is varied using the module's PCA0CPLn capture/compare register.
When the value in the low byte of the PCA0 counter/timer (PCA0L) is equal to the value in PCA0CPLn, the output on the CEXn pin will be high. When the count value in PCA0L overflows, the CEXn output will be
low (see Figure 25.8). Also, when the counter/timer low byte (PCA0L) overflows from 0xFF to 0x00,
PCA0CPLn is reloaded automatically with the value stored in the counter/timer's high byte (PCA0H) without software intervention. Setting the ECOMn and PWMn bits in the PCA0CPMn register enables 8-Bit
Pulse Width Modulator mode. The duty cycle for 8-Bit PWM Mode is given by Equation 25.2.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/
Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit to ‘0’; writing to PCA0CPHn sets ECOMn to ‘1’.
Equation 25.2. 8-Bit PWM Duty Cycle
DutyCycle
=
(
256 –
PCA0CPHn
256
)
Figure 25.8. PCA 8-Bit PWM Mode Diagram
PCA0CPHn
PCA0CPMn
M
1
P
W
6 n
E
C
O
C
A
P
M P n n n
C M
A A
T
O
P
N
T n
G n
M n
P
W
E
C
C
F n
0 0 0 0 0 0
PCA0CPLn
Enable
PCA Timebase
8-bit
Comparator
PCA0L
Overflow match
S
SET
Q
R
CLR
Q
CEXn
Crossbar Port I/O
310 Rev. 1.2
C8051F060/1/2/3/4/5/6/7
25.2.6. 16-Bit Pulse Width Modulator Mode
Each PCA0 module may also be operated in 16-Bit PWM mode. In this mode, the 16-bit capture/compare module defines the number of PCA0 clocks for the low time of the PWM signal. When the PCA0 counter matches the module contents, the output on CEXn is asserted high; when the counter overflows, CEXn is asserted low. To output a varying duty cycle, new value writes should be synchronized with PCA0 CCFn match interrupts. 16-Bit PWM Mode is enabled by setting the ECOMn, PWMn, and PWM16n bits in the
PCA0CPMn register. For a varying duty cycle, CCFn should also be set to logic 1 to enable match inter-
rupts. The duty cycle for 16-Bit PWM Mode is given by Equation 25.3.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/
Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit to ‘0’; writing to PCA0CPHn sets ECOMn to ‘1’.
Equation 25.3. 16-Bit PWM Duty Cycle
DutyCycle
=
(
65536 –
PCA0CPn
65536
)
Figure 25.9. PCA 16-Bit PWM Mode
PCA0CPMn
6 n
P
W
M
1
E
C
O
M n
C
A
P
P n
C
A
P
N
M
A
T n
T
O
G n
P
W
M n n
E
C
C
F n
1 0 0 0 0 0
PCA0CPHn PCA0CPLn
PCA Timebase
Enable
16-bit Comparator
PCA0H PCA0L
Overflow match
S
SET
Q
CEXn
Crossbar
R
CLR
Q
Port I/O
Rev. 1.2
311
C8051F060/1/2/3/4/5/6/7
25.3. Register Descriptions for PCA0
Following are detailed descriptions of the special function registers related to the operation of PCA0.
Figure 25.10. PCA0CN: PCA Control Register
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
R/W
CF
Bit7
Bit7:
R/W
CR
Bit6
R/W
CCF5
Bit5
R/W
CCF4
Bit4
R/W
CCF3
Bit3
R/W
CCF2
Bit2
R/W
CCF1
Bit1
R/W
CCF0
Bit0
Reset Value
00000000
SFR Address: 0xD8
SFR Page: 0
CF: PCA Counter/Timer Overflow Flag.
Set by hardware when the PCA0 Counter/Timer overflows from 0xFFFF to 0x0000. When the Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the CPU to vector to the CF interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software.
CR: PCA0 Counter/Timer Run Control.
This bit enables/disables the PCA0 Counter/Timer.
0: PCA0 Counter/Timer disabled.
1: PCA0 Counter/Timer enabled.
CCF5: PCA0 Module 5 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software.
CCF4: PCA0 Module 4 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software.
CCF3: PCA0 Module 3 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software.
CCF2: PCA0 Module 2 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software.
CCF1: PCA0 Module 1 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software.
CCF0: PCA0 Module 0 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software.
312 Rev. 1.2
C8051F060/1/2/3/4/5/6/7
Figure 25.11. PCA0MD: PCA0 Mode Register
R/W
CIDL
Bit7
R/W
-
Bit6
R/W
-
Bit5
R/W
-
Bit4
R/W
CPS2
Bit3
R/W
CPS1
Bit2
R/W
CPS0
Bit1
R/W
ECF
Reset Value
00000000
Bit0
SFR Address: 0xD9
SFR Page: 0
Bit7: CIDL: PCA0 Counter/Timer Idle Control.
Specifies PCA0 behavior when CPU is in Idle Mode.
0: PCA0 continues to function normally while the system controller is in Idle Mode.
1: PCA0 operation is suspended while the system controller is in Idle Mode.
Bits6-4: UNUSED. Read = 000b, Write = don't care.
Bits3-1: CPS2-CPS0: PCA0 Counter/Timer Pulse Select.
These bits select the timebase source for the PCA0 counter
CPS2
0
0
0
0
1
1
1
1
CPS1
0
0
1
1
1
1
0
0
CPS0
0
1
0
1
0
1
0
1
Timebase
System clock divided by 12
System clock divided by 4
Timer 0 overflow
High-to-low transitions on ECI (max rate = system clock divided by 4)
System clock
External clock divided by 8†
Reserved
Reserved
Bit0: ECF: PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA0 Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA0 Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is set.
†Note: External clock divided by 8 is synchronized with the system clock, and external clock must be less than or equal to the system clock frequency to operate in this mode.
Rev. 1.2
313
C8051F060/1/2/3/4/5/6/7
Figure 25.12. PCA0CPMn: PCA0 Capture/Compare Mode Registers
R/W
PWM16n
R/W
ECOMn
R/W
CAPPn
R/W
CAPNn
R/W
MATn
R/W
TOGn
R/W
PWMn
R/W
ECCFn
Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
PCA0CPM0: 0xDA, PCA0CPM1: 0xDB, PCA0CPM2: 0xDC, PCA0CPM3: 0xDD, PCA0CPM4: 0xDE, PCA0CPM5:
0xDF
SFR Page:
PCA0CPM0: page 0, PCA0CPM1: page 0, PCA0CPM2: page 0, PCA0CPM3: 0, PCA0CPM4: page 0, PCA0CPM5: page 0
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
PWM16n: 16-bit Pulse Width Modulation Enable.
This bit selects 16-bit mode when Pulse Width Modulation mode is enabled (PWMn = 1).
0: 8-bit PWM selected.
1: 16-bit PWM selected.
ECOMn: Comparator Function Enable.
This bit enables/disables the comparator function for PCA0 module n.
0: Disabled.
1: Enabled.
CAPPn: Capture Positive Function Enable.
This bit enables/disables the positive edge capture for PCA0 module n.
0: Disabled.
1: Enabled.
CAPNn: Capture Negative Function Enable.
This bit enables/disables the negative edge capture for PCA0 module n.
0: Disabled.
1: Enabled.
MATn: Match Function Enable.
This bit enables/disables the match function for PCA0 module n. When enabled, matches of the PCA0 counter with a module's capture/compare register cause the CCFn bit in PCA0MD register to be set to logic 1.
0: Disabled.
1: Enabled.
TOGn: Toggle Function Enable.
This bit enables/disables the toggle function for PCA0 module n. When enabled, matches of the PCA0 counter with a module's capture/compare register cause the logic level on the
CEXn pin to toggle. If the PWMn bit is also set to logic 1, the module operates in Frequency
Output Mode.
0: Disabled.
1: Enabled.
PWMn: Pulse Width Modulation Mode Enable.
This bit enables/disables the PWM function for PCA0 module n. When enabled, a pulse width modulated signal is output on the CEXn pin. 8-bit PWM is used if PWM16n is logic 0;
16-bit mode is used if PWM16n logic 1. If the TOGn bit is also set, the module operates in
Frequency Output Mode.
0: Disabled.
1: Enabled.
ECCFn: Capture/Compare Flag Interrupt Enable.
This bit sets the masking of the Capture/Compare Flag (CCFn) interrupt.
0: Disable CCFn interrupts.
1: Enable a Capture/Compare Flag interrupt request when CCFn is set.
314 Rev. 1.2
C8051F060/1/2/3/4/5/6/7
Figure 25.13. PCA0L: PCA0 Counter/Timer Low Byte
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W Reset Value
00000000
Bit0
SFR Address: 0xF9
SFR Page: 0
Bits 7-0: PCA0L: PCA0 Counter/Timer Low Byte.
The PCA0L register holds the low byte (LSB) of the 16-bit PCA0 Counter/Timer.
Figure 25.14. PCA0H: PCA0 Counter/Timer High Byte
R/W
Bit7
R/W
Bit6
R/W
Bit5
R/W
Bit4
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W Reset Value
00000000
Bit0
SFR Address: 0xFA
SFR Page: 0
Bits 7-0: PCA0H: PCA0 Counter/Timer High Byte.
The PCA0H register holds the high byte (MSB) of the 16-bit PCA0 Counter/Timer.
Rev. 1.2
315
316
C8051F060/1/2/3/4/5/6/7
Figure 25.15. PCA0CPLn: PCA0 Capture Module Low Byte
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7
SFR Page:
Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
PCA0CPL0: 0xFB, PCA0CPL1: 0xFD, PCA0CPL2: 0xE9, PCA0CPL3: 0xEB, PCA0CPL4: 0xED, PCA0CPL5:
0xE1
PCA0CPL0: page 0, PCA0CPL1: page 0, PCA0CPL2: page 0, PCA0CPL3: page 0, PCA0CPL4: page 0,
PCA0CPL5: page 0
\
Bits7-0: PCA0CPLn: PCA0 Capture Module Low Byte.
The PCA0CPLn register holds the low byte (LSB) of the 16-bit capture module n.
Figure 25.16. PCA0CPHn: PCA0 Capture Module High Byte
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SFR Address:
PCA0CPH0: 0xFC, PCA0CPH1: 0xFD, PCA0CPH2: 0xEA, PCA0CPH3: 0xEC, PCA0CPH4: 0xEE, PCA0CPH5:
0xE2
SFR Page:
PCA0CPH0: page 0, PCA0CPH1: page 0, PCA0CPH2: page 0, PCA0CPH3: page 0, PCA0CPH4: page 0,
PCA0CPH5: page 0
Bits7-0: PCA0CPHn: PCA0 Capture Module High Byte.
The PCA0CPHn register holds the high byte (MSB) of the 16-bit capture module n.
Rev. 1.2
C8051F060/1/2/3/4/5/6/7
26.
JTAG (IEEE 1149.1)
Each MCU has an on-chip JTAG interface and logic to support boundary scan for production and in-system testing, Flash read/write operations, and non-intrusive in-circuit debug. The JTAG interface is fully compliant with the IEEE 1149.1 specification. Refer to this specification for detailed descriptions of the Test
Interface and Boundary-Scan Architecture. Access of the JTAG Instruction Register (IR) and Data Registers (DR) are as described in the Test Access Port and Operation of the IEEE 1149.1 specification.
The JTAG interface is accessed via four dedicated pins on the MCU: TCK, TMS, TDI, and TDO.
be commanded. There are three DR’s associated with JTAG Boundary-Scan, and four associated with
Flash read/write operations on the MCU.
Figure 26.1. IR: JTAG Instruction Register
Reset Value
0x0000
Bit15 Bit0
IR Value
0x0000
0x0002
0x0004
0xFFFF
0x0082
0x0083
SAMPLE/
PRELOAD
IDCODE
BYPASS
0x0084 Flash Address
0x0085
Instruction
EXTEST
Flash Control
Flash Data
Flash Scale
Description
Selects the Boundary Data Register for control and observability of all device pins
Selects the Boundary Data Register for observability and presetting the scan-path latches
Selects device ID Register
Selects Bypass Data Register
Selects FLASHCON Register to control how the interface logic responds to reads and writes to the FLASHDAT Register
Selects FLASHDAT Register for reads and writes to the Flash memory
Selects FLASHADR Register which holds the address of all Flash read, write, and erase operations
Selects FLASHSCL Register which controls the Flash one-shot timer and read-always enable
Rev. 1.2
317
C8051F060/1/2/3/4/5/6/7
26.1. Boundary Scan
The DR in the Boundary Scan path is a 126-bit shift register for the
C8051F060/2/4/6
and a 118-bit shift register for the C8051F061/3/5/7. The Boundary DR provides control and observability of all the device pins as well as the SFR bus and Weak Pullup feature via the EXTEST and SAMPLE commands.
Table 26.1. Boundary Data Register Bit Definitions (C8051F060/2/4/6)
EXTEST provides access to both capture and update actions, while Sample only performs a capture.
Bit Action Target
0 Capture Reset Enable from MCU
Update Reset Enable to /RST pin
1
2
Capture Reset Input from /RST pin
Update Not used
Capture CAN RX Output Enable to pin
Update CAN RX Output Enable to pin
3
4
5
6
Capture CAN RX Input from pin
Update CAN RX Output to pin
Capture CAN TX Output Enable to pin
Update CAN TX Output Enable to pin
Capture CAN TX Input from pin
Update CAN TX Output to pin
Capture External Clock from XTAL1 pin
Update Not used
7
8, 10, 12, 14, 16,
18, 20, 22
9, 11, 13, 15, 17,
19, 21, 23
24, 26, 28, 30, 32,
34, 36, 38
25, 27, 29, 31, 33,
35, 37, 39
40, 42, 44, 46, 48,
50, 52, 54
41, 43, 45, 47, 49,
51, 53, 55
56, 58, 60, 62, 64,
66, 68, 70
Capture Weak Pullup Enable from MCU
Update Weak Pullup Enable to Port Pins
Capture P0.n output enable from MCU (e.g. Bit 8 = P0.0, Bit 10 = P0.1, etc.)
Update P0.n output enable to pin (e.g. Bit 8 = P0.0oe, Bit 10 = P0.1oe, etc.)
Capture P0.n input from pin (e.g. Bit 9 = P0.0, Bit 11 = P0.1, etc.)
Update P0.n output to pin (e.g. Bit 9 = P0.0, Bit 11 = P0.1, etc.)
Capture P1.n output enable from MCU (follows P0.n numbering scheme)
Update P1.n output enable to pin (follows P0.n numbering scheme)
Capture P1.n input from pin (follows P0.n numbering scheme)
Update P1.n output to pin (follows P0.n numbering scheme)
Capture P2.n output enable from MCU (follows P0.n numbering scheme)
Update P2.n output enable to pin (follows P0.n numbering scheme)
Capture P2.n input from pin (follows P0.n numbering scheme)
Update P2.n output to pin (follows P0.n numbering scheme)
Capture P3.n output enable from MCU (follows P0.n numbering scheme)
Update P3.n output enable to pin (follows P0.n numbering scheme)
57, 59, 61, 63, 65,
67, 69, 71
72, 74, 76
73, 75, 77
78, 80, 82, 84, 86,
88, 90, 92
Capture P3.n input from pin (follows P0.n numbering scheme)
Update P3.n output to pin (follows P0.n numbering scheme)
Capture P4.5, P4.6, P4.7 (respectively) output enable from MCU
Update P4.5, P4.6, P4.7 (respectively) output enable to pin
Capture P4.5, P4.6, P4.7 (respectively) input from pin
Update P4.5, P4.6, P4.7 (respectively) output to pin
Capture P5.n output enable from MCU (follows P0.n numbering scheme)
Update P5.n output enable to pin (follows P0.n numbering scheme)
318 Rev. 1.2
C8051F060/1/2/3/4/5/6/7
Table 26.1. Boundary Data Register Bit Definitions (C8051F060/2/4/6) (Continued)
EXTEST provides access to both capture and update actions, while Sample only performs a capture.
Bit
79, 81, 83, 85, 87,
89, 91, 93
Action Target
Capture P5.n input from pin (follows P0.n numbering scheme)
94, 96, 98, 100,
102, 104, 106, 108
95, 97, 99, 101,
103, 105, 107, 109
Update P5.n output to pin (follows P0.n numbering scheme)
Capture P6.n output enable from MCU (follows P0.n numbering scheme)
Update P6.n output enable to pin (follows P0.n numbering scheme)
Capture P6.n input from pin (follows P0.n numbering scheme)
110, 112, 114, 116,
118, 120, 122, 124
111, 113, 115, 117,
119, 121, 123, 125
Update P6.n output to pin (follows P0.n numbering scheme)
Capture P7.n output enable from MCU (follows P0.n numbering scheme)
Update P7.n output enable to pin (follows P0.n numbering scheme)
Capture P7.n input from pin (follows P0.n numbering scheme)
Update P7.n output to pin (follows P0.n numbering scheme)
Rev. 1.2
319
C8051F060/1/2/3/4/5/6/7
Table 26.2. Boundary Data Register Bit Definitions (C8051F061/3/5/7)
EXTEST provides access to both capture and update actions, while Sample only performs a capture.
Bit
0
Action
Capture
Target
Not used
1
2
Update Not used
Capture Not used
Update Not used
Capture CAN RX Output Enable to pin
3
4
5
6
Update CAN RX Output Enable to pin
Capture CAN RX Input from pin
Update CAN RX Output to pin
Capture CAN TX Output Enable to pin
Update CAN TX Output Enable to pin
Capture CAN TX Input from pin
Update CAN TX Output to pin
Capture External Clock from XTAL1 pin
7
8, 10, 12, 14, 16,
18, 20, 22
9, 11, 13, 15, 17,
19, 21, 23
24, 26, 28, 30, 32,
34, 36, 38
25, 27, 29, 31, 33,
35, 37, 39
40, 42, 44, 46, 48,
50, 52, 54
41, 43, 45, 47, 49,
51, 53, 55
56, 58, 60, 62, 64,
66, 68, 70
57, 59, 61, 63, 65,
67, 69, 71
72
73
74, 76, 78, 80, 82,
84
75, 77, 79, 81, 83,
85
86, 88, 90, 92, 94,
96, 98, 100
Update Not used
Capture Weak Pullup Enable from MCU
Update Weak Pullup Enable to Port Pins
Capture P0.n output enable from MCU (e.g. Bit 8 = P0.0, Bit 10 = P0.1, etc.)
Update P0.n output enable to pin (e.g. Bit 8 = P0.0oe, Bit 10 = P0.1oe, etc.)
Capture P0.n input from pin (e.g. Bit 9 = P0.0, Bit 11 = P0.1, etc.)
Update P0.n output to pin (e.g. Bit 9 = P0.0, Bit 11 = P0.1, etc.)
Capture P1.n output enable from MCU (follows P0.n numbering scheme)
Update P1.n output enable to pin (follows P0.n numbering scheme)
Capture P1.n input from pin (follows P0.n numbering scheme)
Update P1.n output to pin (follows P0.n numbering scheme)
Capture P2.n output enable from MCU (follows P0.n numbering scheme)
Update P2.n output enable to pin (follows P0.n numbering scheme)
Capture P2.n input from pin (follows P0.n numbering scheme)
Update P2.n output to pin (follows P0.n numbering scheme)
Capture P3.n output enable from MCU (follows P0.n numbering scheme)
Update P3.n output enable to pin (follows P0.n numbering scheme)
Capture P3.n input from pin (follows P0.n numbering scheme)
Update P3.n output to pin (follows P0.n numbering scheme)
Capture Reset Enable from MCU
Update Reset Enable to /RST pin
Capture Reset Input from /RST pin
Update Not used
Capture P5.0, P5.1, P5.2, P5.3, P5.5, P5.7 (respectively) output enable from
MCU†
Update P5.0, P5.1, P5.2, P5.3, P5.5, P5.7 (respectively) output enable to pin†
Capture P5.0, P5.1, P5.2, P5.3, P5.5, P5.7 (respectively) input from pin†
Update P5.0, P5.1, P5.2, P5.3, P5.5, P5.7 (respectively) output to pin†
Capture P6.n output enable from MCU (follows P0.n numbering scheme)†
Update P6.n output enable to pin (follows P0.n numbering scheme)†
320 Rev. 1.2
C8051F060/1/2/3/4/5/6/7
Table 26.2. Boundary Data Register Bit Definitions (C8051F061/3/5/7) (Continued)
EXTEST provides access to both capture and update actions, while Sample only performs a capture.
Bit
87, 89, 91, 93, 95,
97, 99, 101
Action Target
Capture P6.n input from pin (follows P0.n numbering scheme)†
102, 104, 106,
108, 110, 112, 114,
116
Update P6.n output to pin (follows P0.n numbering scheme)†
Capture P7.n output enable from MCU (follows P0.n numbering scheme)†
Update P7.n output enable to pin (follows P0.n numbering scheme)†
103, 105, 107,
109, 111, 113, 115,
117
Capture
Update
P7.n input from pin (follows P0.n numbering scheme)†
P7.n output to pin (follows P0.n numbering scheme)†
† Not connected to pins in this device package.
26.1.1. EXTEST Instruction
The EXTEST instruction is accessed via the IR. The Boundary DR provides control and observability of all the device pins as well as the Weak Pullup feature. All inputs to on-chip logic are set to logic 1.
26.1.2. SAMPLE Instruction
The SAMPLE instruction is accessed via the IR. The Boundary DR provides observability and presetting of the scan-path latches.
26.1.3. BYPASS Instruction
The BYPASS instruction is accessed via the IR. It provides access to the standard JTAG Bypass data register.
26.1.4. IDCODE Instruction
The IDCODE instruction is accessed via the IR. It provides access to the 32-bit Device ID register.
Figure 26.2. DEVICEID: JTAG Device ID Register
Bit31
Version
Bit28 Bit27
Part Number
Bit12 Bit11
Manufacturer ID
Bit1
1
Bit0
Reset Value
0xn0006243
Version = 0000b
Part Number = 0000 0000 0000 0110b (C8051F060/1/2/3/4/5/6/7)
Manufacturer ID = 0010 0100 001b (Silicon Labs)
Rev. 1.2
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26.2. Flash Programming Commands
The Flash memory can be programmed directly over the JTAG interface using the Flash Control, Flash
Data, Flash Address, and Flash Scale registers. These Indirect Data Registers are accessed via the JTAG
Instruction Register. Read and write operations on indirect data registers are performed by first setting the appropriate DR address in the IR register. Each read or write is then initiated by writing the appropriate
Indirect Operation Code (IndOpCode) to the selected data register. Incoming commands to this register have the following format:
19:18
IndOpCode
17:0
WriteData
IndOpCode: These bit set the operation to perform according to the following table:
IndOpCode
0x
10
11
Operation
Poll
Read
Write
The Poll operation is used to check the Busy bit as described below. Although a Capture-DR is performed, no Update-DR is allowed for the Poll operation. Since updates are disabled, polling can be accomplished by shifting in/out a single bit.
The Read operation initiates a read from the register addressed by the DRAddress. Reads can be initiated by shifting only 2 bits into the indirect register. After the read operation is initiated, polling of the Busy bit must be performed to determine when the operation is complete.
The write operation initiates a write of WriteData to the register addressed by DRAddress. Registers of any width up to 18 bits can be written. If the register to be written contains fewer than 18 bits, the data in Write-
Data should be left-justified, i.e. its MSB should occupy bit 17 above. This allows shorter registers to be written in fewer JTAG clock cycles. For example, an 8-bit register could be written by shifting only 10 bits.
After a Write is initiated, the Busy bit should be polled to determine when the next operation can be initiated. The contents of the Instruction Register should not be altered while either a read or write operation is busy.
Outgoing data from the indirect Data Register has the following format:
19
0
18:1
ReadData
0
Busy
The Busy bit indicates that the current operation is not complete. It goes high when an operation is initiated and returns low when complete. Read and Write commands are ignored while Busy is high. In fact, if polling for Busy to be low will be followed by another read or write operation, JTAG writes of the next operation can be made while checking for Busy to be low. They will be ignored until Busy is read low, at which time the new operation will initiate. This bit is placed at bit 0 to allow polling by single-bit shifts. When waiting for a Read to complete and Busy is 0, the following 18 bits can be shifted out to obtain the resulting data.
ReadData is always right-justified. This allows registers shorter than 18 bits to be read using a reduced number of shifts. For example, the results from a byte-read requires 9 bit shifts (Busy + 8 bits).
322 Rev. 1.2
C8051F060/1/2/3/4/5/6/7
Figure 26.3. FLASHCON: JTAG Flash Control Register
SFLE
Bit7
WRMD2 WRMD1 WRMD0
Bit6 Bit5 Bit4
RDMD3
Bit3
RDMD2
Bit2
RDMD1
Bit1
RDMD0
Bit0
Reset Value
00000000
This register determines how the Flash interface logic will respond to reads and writes to the
FLASHDAT Register.
Bit7: SFLE: Scratchpad Flash Memory Access Enable
When this bit is set, Flash reads and writes through the JTAG port are directed to the 128byte Scratchpad Flash sector. When SFLE is set to logic 1, Flash accesses out of the address range 0x00-0x7F should not be attempted. Reads/Writes out of this range will yield undefined results.
0: Flash access from JTAG directed to the Program/Data Flash sector.
1: Flash access from JTAG directed to the Scratchpad sector.
Bits6-4: WRMD2-0: Write Mode Select Bits.
The Write Mode Select Bits control how the interface logic responds to writes to the FLASH-
DAT Register per the following values:
000: A FLASHDAT write replaces the data in the FLASHDAT register, but is otherwise ignored.
001: A FLASHDAT write initiates a write of FLASHDAT into the memory address by the
FLASHADR register. FLASHADR is incremented by one when complete.
010: A FLASHDAT write initiates an erasure (sets all bytes to 0xFF) of the Flash page containing the address in FLASHADR. The data written must be 0xA5 for the erase to occur.
FLASHADR is not affected. If FLASHADR = 0x7BFE - 0x7BFF, the entire user space will be erased (i.e. entire Flash memory except for Reserved area 0x7C00 - 0x7FFF).
(All other values for WRMD2-0 are reserved.)
Bits3-0: RDMD3-0: Read Mode Select Bits.
The Read Mode Select Bits control how the interface logic responds to reads to the FLASH-
DAT Register per the following values:
0000: A FLASHDAT read provides the data in the FLASHDAT register, but is otherwise ignored.
0001: A FLASHDAT read initiates a read of the byte addressed by the FLASHADR register if no operation is currently active. This mode is used for block reads.
0010: A FLASHDAT read initiates a read of the byte addressed by FLASHADR only if no operation is active and any data from a previous read has already been read from FLASH-
DAT. This mode allows single bytes to be read (or the last byte of a block) without initiating an extra read.
(All other values for RDMD3-0 are reserved.)
Rev. 1.2
323
C8051F060/1/2/3/4/5/6/7
Figure 26.5. FLASHADR: JTAG Flash Address Register
Reset Value
0x0000
Bit15 Bit0
This register holds the address for all JTAG Flash read, write, and erase operations. This register autoincrements after each read or write, regardless of whether the operation succeeded or failed.
Bits15-0: Flash Operation 16-bit Address.
Figure 26.4. FLASHDAT: JTAG Flash Data Register
Bit0
Reset Value
0000000000
Bit9
This register is used to read or write data to the Flash memory across the JTAG interface.
Bits9-2: DATA7-0: Flash Data Byte.
Bit1: FAIL: Flash Fail Bit.
0: Previous Flash memory operation was successful.
1: Previous Flash memory operation failed. Usually indicates the associated memory loca-
Bit0: tion was locked.
BUSY: Flash Busy Bit.
0: Flash interface logic is not busy.
1: Flash interface logic is processing a request. Reads or writes while BUSY = 1 will not initiate another operation
324 Rev. 1.2
C8051F060/1/2/3/4/5/6/7
26.3. Debug Support
Each MCU has on-chip JTAG and debug logic that provides non-intrusive, full speed, in-circuit debug support using the production part installed in the end application, via the four pin JTAG I/F. Silicon Labs' debug system supports inspection and modification of memory and registers, breakpoints, and single stepping.
No additional target RAM, program memory, or communications channels are required. All the digital and analog peripherals are functional and work correctly (remain synchronized) while debugging. The Watchdog Timer (WDT) is disabled when the MCU is halted during single stepping or at a breakpoint.
The C8051F060DK is a development kit with all the hardware and software necessary to develop application code and perform in-circuit debug with each MCU in the C8051F06x family. Each kit includes development software for the PC, a Serial Adapter (for connection to JTAG) and a target application board with a
C8051F060 installed. Serial cables and wall-mount power supply are also included.
Rev. 1.2
325
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326 Rev. 1.2
C8051F060/1/2/3/4/5/6/7
Document Change List
Revision 1.1 to Revision 1.2
• Added four part numbers: C8051F064, C8051F065, C8051F066, and C8051F067.
• Modified all sections to describe functionality of the four new parts.
• Revised and expanded Flash Chapter with clearer descriptions of Flash security features.
• UART0 Chapter, Section 22.3: “FE0 in register SCON0” changed to “FE0 in register SSTA0”.
• UART0 Chapter: Updated and clarified baud rate equations.
• Port I/O Chapter, Section 18.2: Added a note in text body that Port 4-7 registers are all on SFR Page F.
• Comparators Chapter: Updated Table 12.1 “Comparator Electrical Characteristics”.
• CIP51 Chapter: Section 13.4.1: Added note regarding IDLE mode operation.
• ADC2 Chapter: AD2LJST bit removed from ADC2CF register description (AD2LJST is in the ADC2CN register).
• ADC2 Chapter: Updated Table 7.1 “ADC2 Electrical Characteristics” and Figure 7.2 “Temperature Sensor Transfer Function” with temperature sensor information.
• ADC0/ADC1 Chapter: Tracking/Conversion timing when ADnTM = 1 is shown in Figure 5.4 and Table
5.1. References to “18” or “16” SAR clocks of tracking were removed.
• DACs Chapter, Table 8.1 “DAC Electrical Characteristics”: Changed “Gain Error” to “Full-Scale Error”.
• SMBus Chapter, Figure 20.9 SMB0CR: Changed “1.125” to “1.125 * 10^6”.
• PCA Chapter, Figure 25.12 PCA0CPMn: Bit 0 name changed to “ECCFn” (from incorrect “EECFn”).
• JTAG Chapter, Figure 26.3 FLASHCON: Bit 7 description corrected. Bit 7 is SFLE, allowing access to the Scratchpad memory area.
• CAN Chapter: Added text “The CAN controller’s clock (f sys
, or CAN_CLK in the C_CAN User’s Guide) is equal to the CIP-51 MCU’s clock (SYSCLK).”
• Table 4.1 “Pin Descriptions”, MONEN: Added text “Recommended configuration is to connect directly to VDD.”
• Timers Chapter: All references to “DCEN” and “DECEN” corrected to “DCENn”.
• Timers Chapter, Equation 24.1: Equation was corrected to “Fsq = Ftclk / (2*(65536-RCAPn))”. This equation is valid for a timer counting up or down.
• Timers Chapter, Figure 24.14 TMRnCF: Corrected Bit 1 description. For square-wave output, CP/RLn
= 0, C/Tn = 0, TnOE = 1.
• VREF Chapters: Added VREF Power Supply Current to VREF Electrical Characteristics Tables.
• PCA Chapter: Added Note about writing PCA0CPLn and PCA0CPHn to sections for SW Timer Mode,
High-Speed Output Mode, Frequency Output Mode, 8-bit PWM Mode, and 16-bit PWM Mode.
• Oscillators Chapter, Table 15.1 “Internal Oscillator Electrical Characteristics”: Updated typical supply current.
• Table 3.1 “Global DC Electrical Characteristics”, Updated supply current numbers with additional characterization data.
• ADC0/ADC1 Chapter: Table 5.2 “ADC0 and ADC1 Electrical Characteristics”, Updated supply current numbers with additional characterization data.
• ADC0/ADC1 Chapter: Table 5.3 “Voltage Reference 0 and 1 Electrical Characteristics”, Updated Output Voltage numbers with characterization data.
• Figure 4.3 “TQFP-100 Package Drawing”, Added “L” Dimension.
• Figure 4.6 “TQFP-64 Package Drawing”, Added “L” Dimension.
Rev. 1.2
327
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Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific written consent of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. Silicon Laboratories products are generally not intended for military applications. Silicon Laboratories products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.
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